SN74LVC2G126-EP [TI]

具有三态输出的增强型产品 2 通道、1.65V 至 5.5V 缓冲器;


型号：	SN74LVC2G126-EP
厂家：	TEXAS INSTRUMENTS
描述：	具有三态输出的增强型产品 2 通道、1.65V 至 5.5V 缓冲器驱动总线驱动器总线收发器
文件：	总13页 (文件大小：767K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74LVC2G126-EP

www.ti.com

SCES856 –DECEMBER 2013

DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

Check for Samples: SN74LVC2G126-EP

FEATURES

•

Supports 5-V V_CCOperation

SUPPORTS DEFENSE, AEROSPACE,

AND MEDICAL APPLICATIONS

Inputs Accept Voltages to 5.5 V

Max t_pdof 6.8 ns at 3.3 V

•

Controlled Baseline

One Assembly and Test Site

One Fabrication Site

Low Power Consumption, 10-μA Max I_CC

±24-mA Output Drive at 3.3 V

Available in Military (–55°C to 125°C)

Temperature Range

Typical V_OLP(Output Ground Bounce)

<0.8 V at V_CC= 3.3 V, T_A= 25°C

•

Extended Product Life Cycle

Extended Product-Change Notification

Product Traceability

•

Typical V_OHV(Output V_OHUndershoot)

>2 V at V_CC= 3.3 V, T_A= 25°C

I_offSupports Partial-Power-Down Mode

Operation

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

DCU PACKAGE

(TOP VIEW)

ESD Protection Exceeds JESD 22

V_CC

2OE

1OE

–

2000-V Human-Body Model (A114-A)

200-V Machine Model (A115-A)

GND

1000-V Charged-Device Model (C101)

DESCRIPTION

This dual bus buffer gate is designed for 1.65-V to 5.5-V V_CCoperation.

The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the

associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a

pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION⁽¹⁾

T_J

PACKAGE⁽²⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

VID NUMBER

–55°C to 125°C

VSSOP - DCU Tape of 250

CLVC2G126MDCUTEP

CEPR

V62/14604-01XE

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Function Table

(Each Buffer)

INPUTS

OUTPUT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SN74LVC2G126-EP

SCES856 –DECEMBER 2013

www.ti.com

Logic Diagram (Positive Logic)

1OE

2OE

ABSOLUTE MAXIMUM RATINGs⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX UNIT

V_CCSupply voltage range

6.5

V_I

Input voltage range⁽²⁾

V_O

I_IK

Voltage range applied to any output in the high-impedance or power-off state⁽²⁾

Voltage range applied to any output in the high or low state^{(2) (3)}

–0.5 V_CC+ 0.5

Input clamp current

V_I< 0

–50

°C

I_OK

I_O

Output clamp current

V_O< 0

Continuous output current

±50

Continuous current through V_CCor GND

Absolute maximum junction temperature range

Storage temperature range

±100

T_J

–55

–65

150

T_stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

(3) The value of V_CCis provided in the recommended operating conditions table.

THERMAL INFORMATION

SN74LVC2G126-EP

THERMAL METRIC⁽¹⁾

DCU

8 PINS

204.3

UNITS

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

θ_JCtop

θ_JB

°C/W

ψ_JT

7.6

ψ_JB

82.6

N/A

θ_JCbot

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

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SCES856 –DECEMBER 2013

RECOMMENDED OPERATING CONDITIONS⁽¹⁾

MIN

MAX UNIT

Operating

1.65

1.5

5.5

V_CC

Supply voltage

Data retention only

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3 V to 3.6 V

V_CC= 4.5 V to 5.5 V

V_CC= 1.65 V to 1.95 V

V_CC= 2.3 V to 2.7 V

V_CC= 3 V to 3.6 V

V_CC= 4.5 V to 5.5 V

0.65 × V_CC

1.7

V_IH

High-level input voltage

0.7 × V_CC

0.35 × V_CC

0.7

0.8

V_IL

Low-level input voltage

0.3 × V_CC

5.5

V_I

Input voltage

High or low state

3-state

V_CC

5.5

V_O

Output voltage

V_CC= 1.65 V

V_CC= 2.3 V

–4

–8

I_OH

High-level output current

Low-level output current

–16

–24

–32

V_CC= 3 V

V_CC= 4.5 V

V_CC= 1.65 V

V_CC= 2.3 V

I_OL

V_CC= 3 V

V_CC= 4.5 V

V_CC= 1.8 V ± 0.15 V, 2.5 V ± 0.2 V

V_CC= 3.3 V ± 0.3 V

V_CC= 5 V ± 0.5 V

Δt/Δv

Input transition rise or fall rate

ns/V

°C

T_J

Operating virtual junction temperature

–55

125

(1) All unused inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

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SN74LVC2G126-EP

SCES856 –DECEMBER 2013

www.ti.com

ELECTRICAL CHARACTERISTICS

These specifications apply for –55°C ≤ T_J≤ 125°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

1.65 V to 5.5 V

1.65 V

MIN

V_CC– 0.1

1.2

TYP⁽¹⁾

MAX

UNIT

I_OH= –100 μA

I_OH= –4 mA

I_OH= –8 mA

I_OH= –16 mA

I_OH= –24 mA

I_OH= –32 mA

I_OL= 100 μA

I_OL= 4 mA

2.3 V

1.9

V_OH

2.4

3 V

2.3

4.5 V

1.65 V to 5.5 V

1.65 V

3.8

0.1

0.45

0.3

I_OL= 8 mA

2.3 V

V_OL

I_OL= 16 mA

I_OL= 24 mA

I_OL= 32 mA

0.4

3 V

0.55

4.5 V

A or OE

inputs

I_I

V_I= 5.5 V or GND

0 to 5.5 V

±5

μA

I_off

V_Ior V_O= 5.5 V

V_O= 0 to 5.5 V

V_I= 5.5 V or GND,

±10

μA

I_OZ

3.6 V

I_CC

ΔI_CC

I_O= 0

1.65 V to 5.5 V

3 V to 5.5 V

One input at V_CC– 0.6 V,

Other inputs at V_CCor GND

500

Data inputs

3.5

C_I

V_I= V_CCor GND

3.3 V

Control

inputs

C_o

V_O= V_CCor GND

6.5

(1) All typical values are at V_CC= 3.3 V, T_J= 25°C.

SWITCHING CHARACTERISTICS

These specifications apply for –55°C ≤ T_J≤ 125°C (unless otherwise noted) (see Figure 2)

V_CC= 1.8 V

± 0.15 V

V_CC= 2.5 V

± 0.2 V

V_CC= 3.3 V

± 0.3 V

V_CC= 5 V

± 0.5 V

FROM

(INPUT)

(OUTPUT)

PARAMETER

UNIT

MIN

3.5

1.7

MAX

MIN

1.7

MAX

MIN

1.4

1.5

MAX

MIN

MAX

5.5

t_pd

t_en

t_dis

15.2

12.6

8.6

5.7

6.8

4.5

5.5

0.1

3.3

OPERATING CHARACTERISTICS

T_J= 25°

V_CC= 1.8 V

V_CC= 2.5 V

V_CC= 3.3 V

V_CC= 5 V

TEST

CONDITIONS

PARAMETER

UNIT

TYP

Outputs enabled

Outputs disabled

Power dissipation

capacitance

C_pd

f = 10 MHz

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SCES856 –DECEMBER 2013

1000000

100000

10000

EM Voiding Fail Mode

1000

100

110

Junction Temperature, T_J(°C)

(1) See datasheet for absolute maximum and minimum recommended operating conditions.

120

130

140

150

(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect

life).

(3) Enhanced plastic product disclaimer applies.

Figure 1. SN74LVC2G126-EP Operating Life Derating Chart

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SN74LVC2G126-EP

SCES856 –DECEMBER 2013

www.ti.com

PARAMETER MEASUREMENT INFORMATION

V_LOAD

Open

GND

R_L

From Output

Under Test

TEST

t_PLH/t_PHL

t_PLZ/t_PZL

t_PHZ/t_PZH

Open

V_LOAD

GND

C_L

(see Note A)

R_L

LOAD CIRCUIT

INPUTS

V_CC

V_M

V_LOAD

C_L

R_L

V_I

t_r/t_f

V_CC

3 V

V_CC

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

5 V ± 0.5 V

£2 ns

V_CC/2

1.5 V

V_CC/2

2 × V_CC

6 V

30 pF

50 pF

1 kW

0.15 V

0.3 V

500 W

£2.5 ns

2 × V_CC

0.3 V

V_I

Timing Input

Data Input

V_M

0 V

t_W

t_su

t_h

V_I

Input

V_M

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

V_I

Output

Control

V_M

Input

V_M

0 V

t_PZL

t_PLZ

t_PLH

t_PHL

V_M

Output

Waveform 1

S1 at V_LOAD

V_OH

V_OL

V_LOAD/2

V_OL

V_M

Output

V_OL+ V

(see Note B)

t_PHL

t_PLH

t_PZH

t_PHZ

V_OH

V_OL

Output

Waveform 2

S1 at GND

V_OH

V_OH– V

V_M

»0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A. C_Lincludes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, Z_O= 50 W.

D. The outputs are measured one at a time, with one transition per measurement.

E. t_PLZand t_PHZare the same as t_dis.

F. t_PZLand t_PZHare the same as t_en.

G. t_PLHand t_PHLare the same as t_pd.

H. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

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PACKAGE OPTION ADDENDUM

www.ti.com

24-Dec-2013

PACKAGING INFORMATION

Orderable Device

CLVC2G126MDCUTEP

V62/14604-01XE

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-55 to 125

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

US8

DCU

250

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

CEPR

ACTIVE

DCU

250

TBD

Call TI

-55 to 125

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-Dec-2013

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVC2G126-EP :

Catalog: SN74LVC2G126

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Dec-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CLVC2G126MDCUTEP

US8

DCU

250

180.0

8.4

2.25

3.35

1.05

4.0

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

20-Dec-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

US8 DCU

SPQ

Length (mm) Width (mm) Height (mm)

202.0 201.0 28.0

CLVC2G126MDCUTEP

250

Pack Materials-Page 2

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SN74LVC2G126-EP [TI]

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