SN74LVC574ANSRE4_技术文档

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SCAS301R − JANUARY 1993 − REVISED MARCH 2005

D

Operate From 1.65 V to 3.6 V

Inputs Accept Voltages to 5.5 V

D

Support Mixed-Mode Signal Operation on

All Ports (5-V Input/Output Voltage With

3.3-V V

)

CC

Specified From −40°C to 85°C,

−40°C to 125°C, and −55°C to 125°C

Max t of 7 ns at 3.3 V

pd

D

I

Supports Partial-Power-Down Mode

off

Operation

D

Latch-Up Performance Exceeds 250 mA Per

JESD 17

D

Typical V

<0.8 V at V

(Output Ground Bounce)

OLP

CC

= 3.3 V, T = 25°C

A

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

D

Typical V

(Output V

Undershoot)

OHV

OH

>2 V at V

= 3.3 V, T = 25°C

CC

A

− 1000-V Charged-Device Model (C101)

SN54LVC574A . . . FK PACKAGE

SN54LVC574A . . . J OR W PACKAGE

SN74LVC574A . . . DB, DGV, DW, N, NS,

OR PW PACKAGE

SN74LVC574A . . . RGY PACKAGE

(TOP VIEW)

1

20

3

2 1 20 19

18

OE

1D

2D

3D

4D

5D

6D

7D

8D

V

CC

1Q

1

2

3

4

5

6

7

8

9

10

20

19

2Q

3Q

4Q

5Q

6Q

3D

4D

5D

6D

7D

4

5

6

7

8

1D

2D

3D

4D

5D

6D

7D

8D

1Q

2

3

4

5

6

7

8

9

19

17

16

15

14

18 2Q

17 3Q

16 4Q

17

16

15

14

13

12

3Q

4Q

5Q

6Q

7Q

8Q

15

14

13

12

11

5Q

6Q

7Q

8Q

CLK

9 10 11 12 13

10

11

GND

description/ordering information

The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V

operation, and the

operation.

CC

SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V

CC

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively

low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional

bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high

or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive

the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus

lines without interface or pullup components.

OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

These devices are fully specified for partial-power-down applications using I . The I circuitry disables the

off

outputs, preventing damaging current backflow through the device when it is powered down.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2005, Texas Instruments Incorporated

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1

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SCAS301R − JANUARY 1993 − REVISED MARCH 2005

description/ordering information (continued)

To ensure the high-impedance state during power up or power down, OE should be tied to V

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

through a pullup

CC

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

QFN − RGY

Reel of 1000

SN74LVC574ARGYR

SN74LVC574AGQNR

SN74LVC574AZQNR

SN74LVC574AN

LC574A

VFBGA − GQN

VFBGA − ZQN (Pb-free)

PDIP − N

−40°C to 85°C

−40°C to 125°C

−55°C to 125°C

LC574A

Tube of 20

Tube of 25

Reel of 2000

Tube of 70

Reel of 2000

Reel of 250

Reel of 2000

Tube of 20

Tube of 85

Tube of 55

SN74LVC574AN

SN74LVC574ADW

SN74LVC574ADWR

SN74LVC574ANSR

SN74LVC574ADBR

SN74LVC574APW

SN74LVC574APWR

SN74LVC574APWT

SN74LVC574ADGVR

SNJ54LVC574AJ

SOIC − DW

LVC574A

SOP − NS

LVC574A

LC574A

SSOP − DB

TSSOP − PW

LC574A

TVSOP − DGV

CDIP − J

LC574A

SNJ54LVC574AJ

SNJ54LVC574AW

SNJ54LVC574AFK

CFP − W

SNJ54LVC574AW

SNJ54LVC574AFK

LCCC − FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

GQN OR ZQN PACKAGE

(TOP VIEW)

terminal assignments

1

2

3

4

1

1D

2

3

4

A

B

C

D

E

A

B

C

D

E

OE

3Q

4D

7Q

8D

V

1Q

2Q

4Q

6Q

8Q

CC

3D

2D

5Q

5D

7D

6D

GND

CLK

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

Q

OE

L

CLK

↑

D

H

L

H

L

↑

L

X

Q

0

H

X

Z

2

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SCAS301R − JANUARY 1993 − REVISED MARCH 2005

logic diagram (positive logic)

1

OE

11

CLK

C1

1D

19

1Q

2

1D

To Seven Other Channels

Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V

CC

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V

I

Voltage range applied to any output in the high-impedance or power-off state, V

O

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V

Voltage range applied to any output in the high or low state, V

O

(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

CC

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

IK

I

Output clamp current, I

OK

O

Continuous current through V

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

CC

Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W

JA

(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W

(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W

(see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W

(see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W

(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W

(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W

(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Power dissipation, P (T = −40°C to 125°C) (see Notes 5 and 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW

tot

A

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The value of V is provided in the recommended operating conditions table.

CC

3. The package thermal impedance is calculated in accordance with JESD 51-7.

4. The package thermal impedance is calculated in accordance with JESD 51-5.

5. For the DW package: above 70°C the value of P derates linearly with 8 mW/K.

tot

6. For the DB, DGV, N, NS, and PW packages: above 60°C the value of P derates linearly with 5.5 mW/K.

tot

3

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SCAS301R − JANUARY 1993 − REVISED MARCH 2005

recommended operating conditions (see Note 7)

SN54LVC574A

−55 TO 125°C

UNIT

MIN

2

MAX

Operating

3.6

V

Supply voltage

V

CC

Data retention only

1.5

2

V

IH

V

IL

V

I

High-level input voltage

Low-level input voltage

Input voltage

V

= 2.7 V to 3.6 V

V

CC

0.8

5.5

CC

0

High or low state

3−state

V

CC

5.5

V

O

Output voltage

V

CC

V

CC

V

CC

V

CC

= 2.7 V

= 3 V

−12

−24

12

I

High-level output current

mA

OH

OL

= 2.7 V

= 3 V

I

Low-level output current

mA

24

∆t/∆v

Input transition rise or fall rate

6

ns/V

NOTE 7: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

recommended operating conditions (see Note 7)

SN74LVC574A

T

= 25°C

−40 TO 85°C

−40 TO 125°C

UNIT

V

A

MIN

MAX

MIN

MAX

MIN

MAX

Operating

1.65

1.5

3.6

1.65

1.5

3.6

1.65

1.5

3.6

V

Supply voltage

CC

Data retention only

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 1.65 V to 1.95 V

= 2.3 V to 2.7 V

= 2.7 V to 3.6 V

= 1.65 V to 1.95 V

= 2.3 V to 2.7 V

= 2.7 V to 3.6 V

0.65 × V

1.7

0.65 × V

1.7

CC

High-level input

voltage

1.7

2

V

IH

2

0.35 × V

0.7

0.35 × V

0.7

0.35 × V

0.7

CC

Low-level input

voltage

V

IL

V

0.8

V

Input voltage

0

5.5

0

5.5

0

5.5

V

I

High or low state

3−state

V

CC

5.5

CC

5.5

CC

5.5

Output voltage

O

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 1.65 V

= 2.3 V

= 2.7 V

= 3 V

−4

−8

−4

−8

−4

−8

High-level

output current

I

mA

OH

OL

−12

−24

4

−12

−24

4

−12

−24

4

= 1.65 V

= 2.3 V

= 2.7 V

= 3 V

8

Low-level

output current

I

mA

12

24

12

24

12

24

∆t/∆v

Input transition rise or fall rate

6

ns/V

NOTE 7: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

4

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SCAS301R − JANUARY 1993 − REVISED MARCH 2005

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LVC574A

−55 TO 125°C

PARAMETER

TEST CONDITIONS

UNIT

V

CC

†

MIN TYP

MAX

I

= −100 µA

2.7 V to 3.6 V

2.7 V

V

CC

− 0.2

2.2

OH

V

= −12 mA

V

OH

3 V

2.4

I

= −24 mA

= 100 µA

= 12 mA

= 24 mA

3 V

2.2

OH

OL

2.7 V to 3.6 V

2.7 V

0.2

0.4

0.55

5

V

OL

3 V

I

V = 5.5 V or GND

3.6 V

µA

I

V

= 0 to 5.5 V

3.6 V

15

OZ

O

V = V

CC

or GND

10

I

O

= 0

3.6 V

µA

CC

‡

3.6 V ≤ V ≤ 5.5 V

10

I

∆I

CC

One input atV

CC

− 0.6 V, Other inputs at V

or GND

2.7 V to 3.6 V

3.3 V

500

µA

pF

CC

C

V = V

CC

or GND

4

5.5

i

I

C

V = V

O CC

3.3 V

o

†

‡

T

= 25°C

A

This applies in the disabled state only.

5

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SCAS301R − JANUARY 1993 − REVISED MARCH 2005

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN74LVC574A

T

A

= 25°C

−40 TO 85°C

−40 TO 125°C

PARAMETER

TEST CONDITIONS

UNIT

V

CC

MIN

− 0.2

1.29

1.9

TYP MAX

MIN MAX

I

= −100 µA

= −4 mA

= −8 mA

1.65 V to 3.6 V

1.65 V

2.3 V

V

CC

V

CC

− 0.2

1.2

1.7

2.2

2.4

2.2

V

CC

− 0.2

1.2

1.7

2.2

2.4

2.2

OH

V

OH

2.7 V

2.2

I

= −12 mA

OH

3 V

2.4

I

= −24 mA

= 100 µA

= 4 mA

3 V

2.3

OH

OL

1.65 V to 3.6 V

1.65 V

2.3 V

0.1

0.24

0.3

0.4

0.55

1

0.2

0.45

0.7

0.4

0.55

5

0.2

0.45

0.7

0.4

0.55

5

= 8 mA

V

OL

= 12 mA

= 24 mA

2.7 V

3 V

I

V = 5.5 V or GND

3.6 V

µA

I

V or V = 5.5 V

0

4

10

off

I

O

V = 0 to 5.5 V

3.6 V

1

10

OZ

I

V = V

CC

or GND

1.5

10

I

= 0

3.6 V

µA

CC

O

†

3.6 V ≤ V ≤ 5.5 V

10

I

One input at V

Other inputs at V

GND

− 0.6 V,

or

CC

∆I

CC

2.7 V to 3.6 V

500

C

V = V

CC

or GND

3.3 V

4

pF

i

I

V = V

O CC

5.5

o

†

This applies in the disabled state only.

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 1)

SN54LVC574A

−55 TO 125°C

V

CC

UNIT

MIN

MAX

150

2.7 V

3.3 V 0.3 V

2.7 V

f

t

Clock frequency

MHz

ns

clock

150

3.3

2

Pulse duration, CLK high or low

Setup time, data before CLK↑

Hold time, data after CLK↑

w

3.3 V 0.3 V

2.7 V

ns

su

h

3.3 V 0.3 V

2.7 V

2

ns

3.3 V 0.3 V

2

6

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ꢕ ꢑꢋ ꢖ ꢗ ꢏꢀꢋꢈꢋ ꢌ ꢊ ꢘꢋ ꢓꢘ ꢋꢀ

SCAS301R − JANUARY 1993 − REVISED MARCH 2005

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 1)

SN54LVC574A

FROM

(INPUT)

TO

(OUTPUT)

−55 TO 125°C

PARAMETER

V

UNIT

CC

MIN

150

MAX

2.7 V

3.3 V 0.3 V

2.7 V

f

t

MHz

ns

max

8

7

Q

CLK

OE

pd

1

3.3 V 0.3 V

2.7 V

9

ns

en

7.5

7

3.3 V 0.3 V

2.7 V

OE

ns

dis

0.5

6.4

3.3 V 0.3 V

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 1)

SN74LVC574A

T

A

= 25°C

−40 TO 85°C −40 TO 125°C

V

CC

UNIT

MIN

TYP

MAX

55

MIN

MAX

55

MIN

MAX

40

1.8 V 0.15 V

2.5 V 0.2 V

2.7 V

95

80

f

t

Clock frequency

MHz

clock

150

3.3 V 0.3 V

1.8 V 0.15 V

2.5 V 0.2 V

2.7 V

9

4

9

4

9

4

Pulse duration, CLK high or low

Setup time, data before CLK↑

ns

w

3.3

6

3.3

6

3.3

6

3.3 V 0.3 V

1.8 V 0.15 V

2.5 V 0.2 V

2.7 V

4

su

h

2

3.3 V 0.3 V

1.8 V 0.15 V

2.5 V 0.2 V

2.7 V

2

4

2

Hold time, data after CLK↑

1.5

3.3 V 0.3 V

1.5

7

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ꢊꢆ ꢋꢈ ꢄ ꢌꢍ ꢎꢌꢏꢋ ꢐꢑ ꢎꢎ ꢌꢐ ꢌꢍ ꢍꢏꢋ ꢒ ꢓꢌ ꢔꢄ ꢑ ꢓꢏꢔ ꢄ ꢊ ꢓꢀ

ꢕꢑ ꢋ ꢖ ꢗ ꢏꢀꢋꢈꢋ ꢌ ꢊꢘꢋ ꢓ ꢘꢋꢀ

SCAS301R − JANUARY 1993 − REVISED MARCH 2005

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figure 1)

SN74LVC574A

FROM

(INPUT)

TO

(OUTPUT)

T

A

= 25°C

−40 TO 85°C −40 TO 125°C

PARAMETER

V

UNIT

CC

MIN

55

TYP

MAX

MIN

55

95

150

1

MAX

MIN

40

MAX

1.8 V 0.15 V

2.5 V 02 V

2.7 V

95

80

f

t

MHz

max

150

1.0

2.2

1.0

1.5

1.0

1.7

150

1.0

2.2

1.0

1.5

1.0

1.7

3.3 V 0.3 V

1.8 V 0.15 V

2.5 V 0.2 V

2.7 V

7.1

4.9

5.0

4.6

6.6

4.8

5.5

4.4

5.4

3.0

4.0

3.9

21.5

10.0

7.8

21.6

10.5

8

21.6

10.5

8.0

1

Q

CLK

OE

ns

pd

1

6.8

2.2

1

7

7.0

3.3 V 0.3 V

1.8 V 0.15 V

2.5 V 0.2 V

2.7 V

19.0

10.0

8.3

19.5

10.5

8.5

7.5

18.8

7.8

7

19.5

10.5

8.5

1

en

1

7.3

1.5

1

7.5

3.3 V 0.3 V

1.8 V 0.15 V

2.5 V 0.2 V

2.7 V

18.3

7.3

18.8

7.8

1

t

OE

ns

dis

6.8

1

7.3

6.2

1.7

6.4

1

6.6

3.3 V 0.3 V

1

sk(o)

operating characteristics, T = 25°C

A

TEST

CONDITIONS

PARAMETER

V

CC

TYP

UNIT

1.8 V

2.5 V

3.3 V

1.8 V

2.5 V

3.3 V

25

29

30

9

Outputs enabled

Outputs disabled

C

Power dissipation capacitance per flip−flop

f = 10 MHz

pF

pd

9

11

8

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ꢕ ꢑꢋ ꢖ ꢗ ꢏꢀꢋꢈꢋ ꢌ ꢊ ꢘꢋ ꢓꢘ ꢋꢀ

SCAS301R − JANUARY 1993 − REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION

V

LOAD

Open

S1

R

L

From Output

Under Test

TEST

S1

GND

t

/t

Open

PLH PHL

/t

C

L

t

V

R

PLZ PZL

LOAD

GND

L

(see Note A)

/t

PHZ PZH

LOAD CIRCUIT

INPUTS

V

CC

V

M

V

C

R

L

V

LOAD

L

∆

V

I

t /t

r f

1.8 V 0.15 V

2.5 V 0.2 V

2.7 V

V

≤2 ns

≤2.5 ns

V

/2

2 × V

6 V

30 pF

50 pF

1 kΩ

500 Ω

0.15 V

0.3 V

CC

2.7 V

1.5 V

3.3 V 0.3 V

6 V

0.3 V

V

I

Timing Input

Data Input

V

M

0 V

t

w

t

su

h

V

I

V

I

Input

V

M

V

M

V

M

V

M

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

V

I

V

I

Output

Control

V

M

V

M

Input

V

M

V

M

0 V

V

0 V

t

PHL

PZL

PLZ

+ V

PLH

PHL

Output

Waveform 1

V

/2

OH

LOAD

V

M

Output

M

V

M

S1 at V

(see Note B)

V

LOAD

OL

∆

V

OL

V

OL

t

PLH

t

PZH

PHZ

− V

Output

Waveform 2

S1 at GND

V

OH

V

OH

V

M

OH

∆

M

Output

M

≈0 V

OL

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A. includes probe and jig capacitance.

C

L

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.

O

D. The outputs are measured one at a time, with one transition per measurement.

E.

F.

G.

t

and t

PHL

are the same as t

.

dis

PLZ

PZL

PLH

PHZ

PZH

are the same as t

.

en

are the same as t .

pd

H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

9

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ꢕꢑ ꢋ ꢖ ꢗ ꢏꢀꢋꢈꢋ ꢌ ꢊꢘꢋ ꢓ ꢘꢋꢀ

SCAS301R − JANUARY 1993 − REVISED MARCH 2005

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

CFP

Drawing

5962-9757601Q2A

5962-9757601QRA

5962-9757601QSA

SN74LVC574ADBLE

SN74LVC574ADBR

ACTIVE

FK

J

20

1

TBD

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

Call TI

ACTIVE

W

OBSOLETE

ACTIVE

SSOP

DB

Call TI

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVC574ADBRE4

SN74LVC574ADGVR

SN74LVC574ADGVRE4

SN74LVC574ADW

ACTIVE

SSOP

TVSOP

SOIC

DB

DGV

DW

20

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVC574ADWE4

SN74LVC574ADWR

SN74LVC574ADWRE4

SN74LVC574AGQNR

SOIC

DW

25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

DW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

DW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

BGA MI

CROSTA

R JUNI

OR

GQN

1000

TBD

SNPB

Level-1-240C-UNLIM

SN74LVC574AN

SN74LVC574ANE4

SN74LVC574ANSR

SN74LVC574ANSRE4

SN74LVC574APW

SN74LVC574APWE4

ACTIVE

PDIP

SO

N

20

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

N

Pb-Free

(RoHS)

NS

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVC574APWLE

SN74LVC574APWR

OBSOLETE TSSOP

PW

20

TBD

Call TI

ACTIVE

TSSOP

QFN

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVC574APWRE4

SN74LVC574APWRG4

SN74LVC574APWT

PW

20

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

PW

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVC574APWTE4

SN74LVC574ARGYR

PW

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

RGY

1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR

no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

6-Dec-2006

Orderable Device

SN74LVC574ARGYRG4

SN74LVC574AZQNR

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

QFN

RGY

20

1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR

no Sb/Br)

BGA MI

CROSTA

R JUNI

OR

ZQN

20

1000 Green (RoHS &

no Sb/Br)

SNAGCU

Level-1-260C-UNLIM

SNJ54LVC574AFK

SNJ54LVC574AJ

SNJ54LVC574AW

ACTIVE

LCCC

CDIP

CFP

FK

J

20

1

TBD

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

M

0,07

0,40

24

13

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

1

12

0,50

A

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

14

16

20

24

38

48

56

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

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型号：	SN74LVC574ANSRE4
厂家：	TEXAS INSTRUMENTS
描述：	OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS 八路边沿触发D型触发器具有三态输出触发器输出元件
文件：	总25页 (文件大小：915K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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