SN74LVC574ANSRG4 [TI]
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS; 八路边沿触发D型触发器具有三态输出
| 型号： | SN74LVC574ANSRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 文件： | 总30页 (文件大小：1169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
D
D
D
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
D
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V V
)
CC
Specified From −40°C to 85°C,
−40°C to 125°C, and −55°C to 125°C
D
D
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Max t of 7 ns at 3.3 V
pd
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Typical V
(Output Ground Bounce)
OLP
<0.8 V at V = 3.3 V, T = 25°C
CC
A
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
D
Typical V
(Output V Undershoot)
OHV
OH
>2 V at V = 3.3 V, T = 25°C
CC
A
− 1000-V Charged-Device Model (C101)
SN54LVC574A . . . FK PACKAGE
SN54LVC574A . . . J OR W PACKAGE
SN74LVC574A . . . DB, DGV, DW, N, NS,
OR PW PACKAGE
SN74LVC574A . . . RGY PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1
20
3
2 1 20 19
18
OE
1D
2D
3D
4D
5D
6D
7D
8D
VCC
1Q
18 2Q
17 3Q
16 4Q
1
20
19
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
4
5
6
7
8
1D
2D
3D
4D
5D
6D
7D
8D
1Q
18 2Q
2
3
4
5
6
7
8
9
19
2
17
16
15
14
3
17
16
15
14
13
12
3Q
4Q
5Q
6Q
7Q
8Q
4
5
6
15
14
13
12
11
5Q
6Q
7Q
8Q
CLK
9 10 11 12 13
7
8
9
10
11
10
GND
description/ordering information
The SN54LVC574A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V V operation, and the
CC
SN74LVC574A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V V operation.
CC
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
unless otherwise noted. On all other products, production
testing of all parameters.
processing does not necessarily include testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
QFN − RGY
Reel of 1000
Reel of 1000
SN74LVC574ARGYR
SN74LVC574AGQNR
SN74LVC574AZQNR
SN74LVC574AN
LC574A
VFBGA − GQN
VFBGA − ZQN (Pb-free)
PDIP − N
−40°C to 85°C
−40°C to 125°C
−55°C to 125°C
LC574A
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
Reel of 2000
Reel of 250
Reel of 2000
Tube of 20
Tube of 85
Tube of 55
SN74LVC574AN
SN74LVC574ADW
SN74LVC574ADWR
SN74LVC574ANSR
SN74LVC574ADBR
SN74LVC574APW
SN74LVC574APWR
SN74LVC574APWT
SN74LVC574ADGVR
SNJ54LVC574AJ
SOIC − DW
LVC574A
SOP − NS
LVC574A
LC574A
SSOP − DB
TSSOP − PW
LC574A
TVSOP − DGV
CDIP − J
LC574A
SNJ54LVC574AJ
SNJ54LVC574AW
SNJ54LVC574AFK
CFP − W
SNJ54LVC574AW
SNJ54LVC574AFK
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
GQN OR ZQN PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
1
1D
2
3
4
A
B
C
D
E
A
B
C
D
E
OE
3Q
4D
7Q
8D
V
1Q
2Q
4Q
6Q
8Q
CC
3D
2D
5Q
5D
7D
6D
GND
CLK
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
↑
D
H
L
H
L
L
↑
L
L
X
X
Q
0
H
X
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
logic diagram (positive logic)
1
OE
11
CLK
C1
1D
19
1Q
2
1D
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, FK, J, N, NS, PW, RGY, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
I
Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Power dissipation, P (T = −40°C to 125°C) (see Notes 5 and 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
tot
A
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
5. For the DW package: above 70°C the value of P derates linearly with 8 mW/K.
tot
6. For the DB, DGV, N, NS, and PW packages: above 60°C the value of P derates linearly with 5.5 mW/K.
tot
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
recommended operating conditions (see Note 7)
SN54LVC574A
−55 TO 125°C
UNIT
MIN
2
MAX
Operating
3.6
V
Supply voltage
V
CC
Data retention only
1.5
2
V
IH
V
IL
V
I
High-level input voltage
Low-level input voltage
Input voltage
V
CC
V
CC
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
V
V
V
0.8
5.5
0
0
0
High or low state
3−state
V
CC
V
O
Output voltage
V
5.5
−12
−24
12
V
V
V
V
= 2.7 V
= 3 V
CC
CC
CC
I
High-level output current
mA
OH
= 2.7 V
= 3 V
I
OL
Low-level output current
mA
24
CC
Δt/Δv
Input transition rise or fall rate
6
ns/V
NOTE 7: All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
recommended operating conditions (see Note 7)
SN74LVC574A
T = 25°C
−40 TO 85°C
−40 TO 125°C
UNIT
V
A
MIN
MAX
MIN
MAX
MIN
MAX
Operating
1.65
1.5
3.6
1.65
1.5
3.6
1.65
1.5
3.6
V
V
Supply voltage
CC
Data retention only
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
0.65 × V
1.7
0.65 × V
1.7
CC
CC
CC
High-level input
voltage
V
IH
2
2
2
0.35 × V
0.7
0.35 × V
0.7
0.35 × V
0.7
CC
CC
CC
Low-level input
voltage
V
IL
V
0.8
0.8
0.8
V
V
Input voltage
0
0
0
5.5
0
0
0
5.5
0
0
0
5.5
V
V
I
High or low state
3−state
V
CC
V
CC
V
CC
Output voltage
O
5.5
−4
−8
−12
−24
4
5.5
−4
−8
−12
−24
4
5.5
−4
−8
−12
−24
4
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
High-level
output current
I
mA
OH
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
8
8
8
Low-level
output current
I
OL
mA
12
24
12
24
12
24
Δt/Δv
Input transition rise or fall rate
6
6
6
ns/V
NOTE 7: All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVC574A
−55 TO 125°C
PARAMETER
TEST CONDITIONS
UNIT
V
CC
†
MIN TYP
MAX
I
I
= −100 μA
2.7 V to 3.6 V
2.7 V
V
CC
− 0.2
2.2
OH
V
V
= −12 mA
V
OH
OH
3 V
2.4
I
I
I
I
= −24 mA
= 100 μA
= 12 mA
= 24 mA
3 V
2.2
OH
OL
OL
OL
2.7 V to 3.6 V
2.7 V
0.2
0.4
0.55
5
V
OL
3 V
I
I
V = 5.5 V or GND
3.6 V
μA
μA
I
I
V
= 0 to 5.5 V
3.6 V
15
OZ
O
V = V or GND
10
I
CC
I
I
O
= 0
3.6 V
μA
CC
‡
3.6 V ≤ V ≤ 5.5 V
10
I
ΔI
One input atV − 0.6 V, Other inputs at V or GND
2.7 V to 3.6 V
3.3 V
500
μA
pF
pF
CC
CC
CC
C
C
V = V or GND
4
i
I
CC
V
O
= V or GND
3.3 V
5.5
o
CC
†
‡
T = 25°C
A
This applies in the disabled state only.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74LVC574A
T = 25°C
−40 TO 85°C
MIN MAX
− 0.2
−40 TO 125°C
PARAMETER
TEST CONDITIONS
UNIT
V
A
CC
MIN
TYP MAX
MIN MAX
I
I
I
= −100 μA
= −4 mA
= −8 mA
1.65 V to 3.6 V
1.65 V
2.3 V
V
CC
− 0.2
1.29
1.9
V
CC
V
− 0.2
OH
OH
OH
CC
1.2
1.7
2.2
2.4
2.2
1.2
1.7
2.2
2.4
2.2
0.2
0.45
0.7
0.4
0.55
5
V
V
V
OH
2.7 V
2.2
I
= −12 mA
OH
3 V
2.4
I
I
I
I
I
I
= −24 mA
= 100 μA
= 4 mA
3 V
2.3
OH
OL
OL
OL
OL
OL
1.65 V to 3.6 V
1.65 V
2.3 V
0.1
0.24
0.3
0.4
0.55
1
0.2
0.45
0.7
0.4
0.55
5
= 8 mA
V
OL
= 12 mA
= 24 mA
2.7 V
3 V
I
I
V = 5.5 V or GND
3.6 V
μA
μA
μA
I
I
off
V or V = 5.5 V
0
4
10
10
I
O
I
V = 0 to 5.5 V
3.6 V
1
10
10
OZ
I
V = V or GND
1.5
1.5
10
10
I
CC
I
I
O
= 0
3.6 V
μA
μA
CC
†
3.6 V ≤ V ≤ 5.5 V
10
10
I
One input at V − 0.6 V,
CC
ΔI
Other inputs at V or
2.7 V to 3.6 V
500
500
500
CC
CC
GND
C
C
V = V or GND
3.3 V
3.3 V
4
pF
pF
i
I
CC
V
O
= V or GND
5.5
o
CC
†
This applies in the disabled state only.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVC574A
−55 TO 125°C
V
CC
UNIT
MIN
MAX
150
2.7 V
3.3 V 0.3 V
2.7 V
f
t
t
t
Clock frequency
MHz
ns
clock
150
3.3
3.3
2
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
w
3.3 V 0.3 V
2.7 V
ns
su
h
3.3 V 0.3 V
2.7 V
2
2
ns
3.3 V 0.3 V
2
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
SN54LVC574A
FROM
(INPUT)
TO
(OUTPUT)
−55 TO 125°C
PARAMETER
V
UNIT
CC
MIN
150
150
MAX
2.7 V
3.3 V 0.3 V
2.7 V
f
t
t
t
MHz
ns
max
8
7
Q
Q
Q
CLK
OE
pd
en
dis
1
1
3.3 V 0.3 V
2.7 V
9
ns
7.5
7
3.3 V 0.3 V
2.7 V
OE
ns
0.5
6.4
3.3 V 0.3 V
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN74LVC574A
T = 25°C
A
−40 TO 85°C −40 TO 125°C
V
CC
UNIT
MIN
TYP
MAX
55
MIN
MAX
55
MIN
MAX
40
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
95
95
80
f
t
t
t
Clock frequency
MHz
clock
150
150
150
150
150
150
3.3 V 0.3 V
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
9
4
9
4
9
4
Pulse duration, CLK high or low
Setup time, data before CLK↑
ns
ns
ns
w
3.3
3.3
6
3.3
3.3
6
3.3
3.3
6
3.3 V 0.3 V
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
4
4
4
su
2
2
2
3.3 V 0.3 V
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
2
2
2
4
4
4
2
2
2
Hold time, data after CLK↑
h
1.5
1.5
1.5
3.3 V 0.3 V
1.5
1.5
1.5
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
SN74LVC574A
FROM
(INPUT)
TO
(OUTPUT)
T = 25°C
−40 TO 85°C −40 TO 125°C
PARAMETER
V
UNIT
A
CC
MIN
55
TYP
MAX
MIN
55
95
150
150
1
MAX
MIN
40
MAX
1.8 V 0.15 V
2.5 V 02 V
2.7 V
95
80
f
t
t
MHz
max
150
150
1.0
1.0
1.0
2.2
1.0
1.0
1.0
1.5
1.0
1.0
1.0
1.7
150
150
1.0
1.0
1.0
2.2
1.0
1.0
1.0
1.5
1.0
1.0
1.0
1.7
3.3 V 0.3 V
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
7.1
4.9
5.0
4.6
6.6
4.8
5.5
4.4
5.4
3.0
4.0
3.9
21.5
10.0
7.8
21.6
10.5
8
21.6
10.5
8.0
1
Q
Q
Q
CLK
OE
ns
ns
pd
1
6.8
2.2
1
7
7.0
3.3 V 0.3 V
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
19.0
10.0
8.3
19.5
10.5
8.5
7.5
18.8
7.8
7
19.5
10.5
8.5
1
en
1
7.3
1.5
1
7.5
3.3 V 0.3 V
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
18.3
7.3
18.8
7.8
1
t
t
OE
ns
ns
dis
6.8
1
7.3
6.2
1.7
6.4
1
6.6
3.3 V 0.3 V
3.3 V 0.3 V
1
sk(o)
operating characteristics, TA = 25°C
TEST
CONDITIONS
PARAMETER
V
CC
TYP
UNIT
1.8 V
2.5 V
3.3 V
1.8 V
2.5 V
3.3 V
25
29
30
9
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per flip−flop
f = 10 MHz
pF
pd
9
11
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVC574A, SN74LVC574A
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCAS301R − JANUARY 1993 − REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
V
LOAD
GND
PLH PHL
t
C
L
/t
R
PLZ PZL
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
R
V
Δ
L
L
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
V
V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
1.5 V
1.5 V
/2
/2
2 × V
2 × V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
3.3 V 0.3 V
6 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
PLZ
t
t
t
PHL
PZL
PLH
PHL
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
V
V
Output
M
S1 at V
LOAD
V
+ V
Δ
OL
OL
(see Note B)
OL
t
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
Δ
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
dis
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9757601Q2A
5962-9757601QRA
5962-9757601QSA
SN74LVC574ADBLE
SN74LVC574ADBR
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
1
1
1
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42
N / A for Pkg Type
N / A for Pkg Type
Call TI
ACTIVE
W
Call TI
Call TI
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC574ADBRE4
SN74LVC574ADBRG4
SN74LVC574ADGVR
SN74LVC574ADGVRE4
SN74LVC574ADGVRG4
SN74LVC574ADW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
SSOP
SSOP
TVSOP
TVSOP
TVSOP
SOIC
DB
DB
20
20
20
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGV
DGV
DGV
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC574ADWE4
SN74LVC574ADWG4
SN74LVC574ADWR
SN74LVC574ADWRE4
SN74LVC574ADWRG4
SN74LVC574AGQNR
SOIC
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
GQN
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74LVC574AN
SN74LVC574ANE4
SN74LVC574ANSR
SN74LVC574ANSRE4
SN74LVC574ANSRG4
SN74LVC574APW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
SO
N
20
20
20
20
20
20
20
20
20
20
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
N
Pb-Free
(RoHS)
NS
NS
NS
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC574APWE4
SN74LVC574APWG4
SN74LVC574APWLE
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
OBSOLETE TSSOP
TBD
Call TI
Call TI
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2009
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74LVC574APWR
SN74LVC574APWRE4
SN74LVC574APWRG4
SN74LVC574APWT
TSSOP
PW
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC574APWTE4
SN74LVC574APWTG4
SN74LVC574ARGYR
SN74LVC574ARGYRG4
SN74LVC574AZQNR
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGY
RGY
ZQN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
VQFN
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
SNJ54LVC574AFK
SNJ54LVC574AJ
SNJ54LVC574AW
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42
N / A for Pkg Type
N / A for Pkg Type
W
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2009
OTHER QUALIFIED VERSIONS OF SN54LVC574A, SN74LVC574A :
Automotive: SN74LVC574A-Q1
Enhanced Product: SN74LVC574A-EP
•
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC574ADBR
SN74LVC574ADGVR
SN74LVC574ADWR
SN74LVC574AGQNR
SSOP
TVSOP
SOIC
DB
DGV
DW
20
20
20
20
2000
2000
2000
1000
330.0
330.0
330.0
330.0
16.4
12.4
24.4
12.4
8.2
6.9
7.5
5.6
2.5
1.6
2.7
1.6
12.0
8.0
16.0
12.0
24.0
12.0
Q1
Q1
Q1
Q1
10.8
3.3
13.0
4.3
12.0
8.0
BGA MI
CROSTA
R JUNI
OR
GQN
SN74LVC574AGQNR
BGA MI
CROSTA
R JUNI
OR
GQN
20
1000
330.0
12.4
3.3
4.3
1.5
8.0
12.0
Q1
SN74LVC574ANSR
SN74LVC574APWR
SN74LVC574APWT
SN74LVC574ARGYR
SN74LVC574AZQNR
SO
NS
PW
20
20
20
20
20
2000
2000
250
330.0
330.0
330.0
330.0
330.0
24.4
16.4
16.4
12.4
12.4
8.2
6.95
6.95
3.8
13.0
7.1
7.1
4.8
4.3
2.5
1.6
1.6
1.6
1.6
12.0
8.0
8.0
8.0
8.0
24.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
TSSOP
TSSOP
VQFN
PW
RGY
ZQN
3000
1000
BGA MI
CROSTA
R JUNI
OR
3.3
SN74LVC574AZQNR
BGA MI
ZQN
20
1000
330.0
12.4
3.3
4.3
1.5
8.0
12.0
Q1
CROSTA
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-Aug-2010
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
R JUNI
OR
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC574ADBR
SN74LVC574ADGVR
SN74LVC574ADWR
SN74LVC574AGQNR
SSOP
TVSOP
SOIC
DB
DGV
DW
20
20
20
20
2000
2000
2000
1000
346.0
346.0
346.0
340.5
346.0
346.0
346.0
338.1
33.0
29.0
41.0
20.6
BGA MICROSTAR
JUNIOR
GQN
SN74LVC574AGQNR
BGA MICROSTAR
JUNIOR
GQN
20
1000
346.0
346.0
29.0
SN74LVC574ANSR
SN74LVC574APWR
SN74LVC574APWT
SN74LVC574ARGYR
SN74LVC574AZQNR
SO
NS
PW
20
20
20
20
20
2000
2000
250
346.0
346.0
346.0
346.0
340.5
346.0
346.0
346.0
346.0
338.1
41.0
33.0
33.0
29.0
20.6
TSSOP
TSSOP
VQFN
PW
RGY
ZQN
3000
1000
BGA MICROSTAR
JUNIOR
SN74LVC574AZQNR
BGA MICROSTAR
JUNIOR
ZQN
20
1000
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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Applications
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amplifier.ti.com
dataconverter.ti.com
www.dlp.com
www.ti.com/audio
Data Converters
DLP® Products
Automotive
www.ti.com/automotive
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Telecom
DSP
dsp.ti.com
Computers and
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www.ti.com/computers
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Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
Consumer Electronics
Energy
www.ti.com/consumer-apps
www.ti.com/energy
Logic
Industrial
www.ti.com/industrial
Power Mgmt
Microcontrollers
RFID
power.ti.com
Medical
www.ti.com/medical
microcontroller.ti.com
www.ti-rfid.com
Security
www.ti.com/security
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
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