SN74LVC646ADBLE [TI]
Octal Bus Transceiver And Register With 3-State Outputs 24-SSOP -40 to 85;
| 型号： | SN74LVC646ADBLE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Octal Bus Transceiver And Register With 3-State Outputs 24-SSOP -40 to 85 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总23页 (文件大小：734K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J–JANUARY 1993–REVISED AUGUST 2005
FEATURES
•
•
•
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 7.4 ns at 3.3 V
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical VOLP (Output Ground Bounce)
<0.8 at VCC = 3.3 V, TA = 25°C
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
•
•
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
– 1000-V Charged-Device Model (C101)
xxxx
3.3-V VCC
)
SN54LVC646A . . . JT OR W PACKAGE
SN74LVC646A . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
SN54LVC646A . . . FK PACKAGE
(TOP VIEW)
CLKAB
SAB
DIR
A1
V
CC
1
2
3
4
5
6
7
8
9
24
23
CLKBA
22 SBA
4
3
2
1
28 27 26
25
A1
A2
A3
NC
A4
OE
B1
B2
NC
B3
B4
B5
5
6
7
8
9
OE
B1
B2
B3
21
20
19
18
24
23
22
21
20
19
A2
A3
A4
A5
A6
A7 10
17 B4
16 B5
15 B6
A5 10
11
A6
12 13 14 15 16 17 18
A8
GND
B7
B8
11
12
14
13
NC - No internal connection
DESCRIPTION/ORDERING INFORMATION
The SN54LVC646A octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation, and the
SN74LVC646A octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVC646ADW
SN74LVC646ADWR
SN74LVC646ANSR
SN74LVC646ADBR
SN74LVC646APW
TOP-SIDE MARKING
LVC646A
Tube of 25
SOIC – DW
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 60
Reel of 2000
Reel of 250
Tube of 15
Tube of 85
Tube of 42
SOP – NS
LVC646A
LC646A
–40°C to 85°C
SSOP – DB
TSSOP – PW
SN74LVC646APWR
SN74LVC646APWT
SNJ54LVC646AJT
LC646A
CDIP – JT
CFP – W
SNJ54LVC646AJT
SNJ54LVC646AW
SNJ54LVC646AFK
–55°C to 125°C
SNJ54LVC646AW
LCCC – FK
SNJ54LVC646AFK
(1) Package drawings, standard packing quantities, thermal data, symboliztion, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1993–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
On products compliant to MIL-PRF-38535, all parameters are
Instruments standard warranty. Production processing does not
tested unless otherwise noted. On all other products, production
necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J–JANUARY 1993–REVISED AUGUST 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked
into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1
illustrates the four fundamental bus-management functions that are performed with the 'LVC646A devices.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode,
data present at the high-impedance port is stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one
register and B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
DATA I/O
OPERATION OR
FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1–A8
Input
B1–B8
↑
X
Unspecified(1)
Store A, B unspecified(1)
Store B, A unspecified(1)
Store and B data
X
X
↑
X
X
Unspecified(1)
Input
X
↑
H or L
X
↑
H or L
X
X
X
Input
Input
X
X
X
Input disabled
Output
Input disabled
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
X
L
L
L
X
H or L
X
X
H
Output
Input
L
H
H
X
L
X
Input
Output
L
H or L
X
H
X
Input
Output
(1) The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e.,
data at the bus terminals is stored on every low-to-high transition of the clock inputs.
2
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J–JANUARY 1993–REVISED AUGUST 2005
21
3
1
23
2
22
21
3
1
23
CLKAB CLKBA SAB
L
2
22
DIR CLKAB CLKBA SAB
L
SBA
L
DIR
H
SBA
X
OE
L
OE
L
X
X
X
X
X
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
21
3
1
23
2
22
21
OE
L
3
DIR
L
1
23
2
22
SBA
H
DIR CLKAB CLKBA SAB
SBA
X
CLKAB CLKBA SAB
OE
X
X
X
X
X
↑
X
X
X
↑
X
↑
X
H or L
X
X
H
X
H
X
X
L
H
H or L
X
↑
TRANSFER STORED DATA
TO A AND/OR B
STORAGE FROM
A, B, OR A AND B
Figure 1. Bus-Management Functions
3
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J–JANUARY 1993–REVISED AUGUST 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
21
OE
3
DIR
23
CLKBA
22
1
SBA
CLKAB
2
SAB
One of Eight Channels
1D
C1
4
A1
20
B1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, NS, PW, and W packages.
4
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J–JANUARY 1993–REVISED AUGUST 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
6.5
6.5
6.5
V
V
VO
VO
IIK
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
63
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
DB package
DW package
NS package
PW package
46
θJA
Package thermal impedance(4)
°C/W
°C
65
88
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
SN54LVC646A
SN74LVC646A
UNIT
MIN
2
MAX
MIN
1.65
1.5
MAX
Operating
3.6
3.6
VCC
Supply voltage
V
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
V
2
0.35 × VCC
0.7
0.8
5.5
VCC
5.5
–4
VIL
Low-level input voltage
0.8
5.5
VI
Input voltage
0
0
0
V
V
High or low state
3-state
VCC
5.5
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–8
IOH
High-level output current
Low-level output current
mA
mA
–12
–24
–12
–24
4
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
12
24
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
10
ns/V
TA
–55
125
–40
85
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J–JANUARY 1993–REVISED AUGUST 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN54LVC646A
MIN TYP(1) MAX
SN74LVC646A
MIN TYP(1) MAX
VCC – 0.2
PARAMETER
TEST CONDITIONS
VCC
UNIT
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
IOH = –100 µA
VCC – 0.2
IOH = –4 mA
IOH = –8 mA
1.2
1.7
2.2
2.4
2.2
VOH
2.3 V
V
2.7 V
2.2
2.4
2.2
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
3 V
3 V
1.65 V to 3.6 V
2.7 V to 3.6 V
1.65 V
0.2
0.2
IOL = 4 mA
IOL = 8 mA
IOL = 12 mA
IOL = 24 mA
0.45
0.7
VOL
V
2.3 V
2.7 V
0.4
0.4
3 V
0.55
0.55
Control
inputs
II
VI = 0 to 5.5 V
3.6 V
±5
±5
µA
Ioff
VI or VO = 5.5 V
VO = 0 to 5.5 V
0
±10
±10
10
µA
µA
(2)
IOZ
3.6 V
±15
10
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V(3)
ICC
IO = 0
3.6 V
µA
10
10
One input at VCC – 0.6 V,
Other inputs at VCC or GND
∆ICC
Ci
2.7 V to 3.6 V
3.3 V
500
500
µA
pF
pF
Control
inputs
VI = VCC or GND
VO = VCC or GND
4.5
7.5
4.5
7.5
A or B
port
Cio
3.3 V
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) For I/O ports, the parameter IOZ includes the input leakage current.
(3) This applies in the disabled state only.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
SN54LVC646A
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
150
MIN
MAX
fclock
tw
Clock frequency
150 MHz
Pulse duration
3.3
1.6
1.7
3.3
1.5
1.7
ns
ns
ns
tsu
th
Setup time, data before CLK↑
Hold time, data after CLK↑
6
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J–JANUARY 1993–REVISED AUGUST 2005
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
SN74LVC646A
VCC = 1.8 V
± 0.18 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
150
MIN
MAX
(1)
(1)
fclock
tw
Clock frequency
150 MHz
(1)
(1)
(1)
(1)
(1)
(1)
Pulse duration
3.3
1.6
1.7
3.3
1.5
1.7
ns
ns
ns
tsu
th
Setup time, data before CLK↑
Hold time, data after CLK↑
(1) This information was not available at the time of publication.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
SN54LVC646A
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
fmax
150
150
1
MHz
ns
A or B
CLK
B or A
A or B
7.9
8.8
7.4
8.4
8.6
8.2
7.5
8.3
7.9
tpd
1
SBA or SAB
OE
9.9
1
ten
tdis
ten
tdis
A
A
B
B
10.2
8.9
1
ns
ns
ns
ns
OE
1
DIR
10.4
8.7
1
DIR
1
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
SN74LVC646A
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
PARAMETER
VCC = 2.7 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
150
1
MAX
(1)
(1)
fmax
150
MHz
ns
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
A or B
CLK
B or A
A or B
7.9
8.8
7.4
8.4
8.6
8.2
7.5
8.3
7.9
tpd
1
SBA or SAB
OE
9.9
1
ten
tdis
ten
tdis
A
A
B
B
10.2
8.9
1
ns
ns
ns
ns
OE
1
DIR
10.4
8.7
1
DIR
1
(1) This information was not available at the time of publication.
7
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J–JANUARY 1993–REVISED AUGUST 2005
Operating Characteristics
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
(1)
(1)
Outputs enabled
Outputs disabled
75
9
Power dissipation capacitance
per transceiver
Cpd
f = 10 MHz
pF
(1)
(1)
(1) This information was not available at the time of publication.
8
SN54LVC646A, SN74LVC646A
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
www.ti.com
SCAS302J–JANUARY 1993–REVISED AUGUST 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
− V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-9762601Q3A
ACTIVE
LCCC
FK
28
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
9762601Q3A
SNJ54LVC
646AFK
5962-9762601QKA
5962-9762601QLA
ACTIVE
ACTIVE
CFP
W
24
24
1
1
TBD
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9762601QK
A
SNJ54LVC646AW
CDIP
JT
5962-9762601QL
A
SNJ54LVC646AJT
SN74LVC646ADBLE
SN74LVC646ADBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
24
24
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LC646A
LC646A
LC646A
LVC646A
LVC646A
LVC646A
LC646A
LC646A
LC646A
SN74LVC646ADBRE4
SN74LVC646ADBRG4
SN74LVC646ADW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
DB
DB
24
24
24
24
24
24
24
24
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
DW
DW
DW
PW
PW
PW
Green (RoHS
& no Sb/Br)
SN74LVC646ADWE4
SN74LVC646ADWG4
SN74LVC646APW
SOIC
25
Green (RoHS
& no Sb/Br)
SOIC
25
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
60
Green (RoHS
& no Sb/Br)
SN74LVC646APWE4
SN74LVC646APWG4
60
Green (RoHS
& no Sb/Br)
60
Green (RoHS
& no Sb/Br)
SN74LVC646APWLE
SN74LVC646APWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
24
24
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LC646A
LC646A
SN74LVC646APWRE4
ACTIVE
TSSOP
PW
24
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74LVC646APWRG4
SN74LVC646APWT
SN74LVC646APWTE4
SN74LVC646APWTG4
SNJ54LVC646AFK
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
LCCC
PW
24
24
24
24
28
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
LC646A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PW
PW
PW
FK
250
250
250
1
Green (RoHS
& no Sb/Br)
-40 to 85
LC646A
LC646A
LC646A
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
TBD
-55 to 125
5962-
9762601Q3A
SNJ54LVC
646AFK
SNJ54LVC646AJT
SNJ54LVC646AW
ACTIVE
ACTIVE
CDIP
CFP
JT
W
24
24
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9762601QL
A
SNJ54LVC646AJT
5962-9762601QK
A
SNJ54LVC646AW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVC646A, SN74LVC646A :
Catalog: SN74LVC646A
•
Military: SN54LVC646A
•
Space: SN54LVC646A-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC646ADBR
SN74LVC646APWR
SN74LVC646APWT
SSOP
TSSOP
TSSOP
DB
PW
PW
24
24
24
2000
2000
250
330.0
330.0
330.0
16.4
16.4
16.4
8.2
8.8
8.3
8.3
2.5
1.6
1.6
12.0
8.0
16.0
16.0
16.0
Q1
Q1
Q1
6.95
6.95
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC646ADBR
SN74LVC646APWR
SN74LVC646APWT
SSOP
TSSOP
TSSOP
DB
PW
PW
24
24
24
2000
2000
250
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MCER004A – JANUARY 1995 – REVISED JANUARY 1997
JT (R-GDIP-T**)
CERAMIC DUAL-IN-LINE
24 LEADS SHOWN
PINS **
A
24
28
DIM
13
24
1.280
(32,51) (37,08)
1.460
A MAX
1.240
(31,50) (36,58)
1.440
B
A MIN
B MAX
B MIN
0.300
(7,62)
0.291
(7,39)
1
12
0.070 (1,78)
0.030 (0,76)
0.245
(6,22)
0.285
(7,24)
0.320 (8,13)
0.290 (7,37)
0.015 (0,38) MIN
0.100 (2,54) MAX
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0.023 (0,58)
0.015 (0,38)
0°–15°
0.014 (0,36)
0.008 (0,20)
0.100 (2,54)
4040110/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP007 – OCTOBER 1994
W (R-GDFP-F24)
CERAMIC DUAL FLATPACK
0.375 (9,53)
0.340 (8,64)
Base and Seating Plane
0.006 (0,15)
0.004 (0,10)
0.045 (1,14)
0.026 (0,66)
0.090 (2,29)
0.045 (1,14)
0.395 (10,03)
0.360 (9,14)
0.360 (9,14)
0.240 (6,10)
0.360 (9,14)
0.240 (6,10)
0.019 (0,48)
0.015 (0,38)
1
24
0.050 (1,27)
0.640 (16,26)
0.490 (12,45)
0.030 (0,76)
0.015 (0,38)
12
13
30° TYP
1.115 (28,32)
0.840 (21,34)
4040180-5/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD
E. Index point is provided on cap for terminal identification only.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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