SN74LVCC3245APWRE4 [TI]
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS; 具有可调输出电压和三态输出的八路总线收发器
| 型号： | SN74LVCC3245APWRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS |
| 文件： | 总18页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O–NOVEMBER 1996–REVISED MARCH 2005
FEATURES
DB, DBQ, DW, NS, OR PW PACKAGE
(TOP VIEW)
•
Bidirectional Voltage Translator
•
2.3 V to 3.6 V on A Port and 3 V to 5.5 V on B
Port
1
24
23
22
21
20
19
18
17
16
15
14
13
V
DIR
V
CCB
CCA
2
NC
OE
B1
B2
B3
•
•
•
Control Inputs VIH/VIL Levels Are Referenced
to VCCA Voltage
3
A1
A2
A3
A4
A5
A6
A7
A8
4
Latch-Up Performance Exceeds 250 mA Per
JESD 17
5
6
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
7
B4
8
B5
B6
B7
B8
9
10
11
12
– 1000-V Charged-Device Model (C101)
GND
GND
GND
NC - No internal connection
DESCRIPTION/ORDERING INFORMATION
This 8-bit (octal) noninverting bus transceiver contains two separate supply rails. The B port is designed to track
VCCB, which accepts voltages from 3 V to 5.5 V, and the A port is designed to track VCCA, which operates at 2.3
V to 3.6 V. This allows for translation from a 3.3-V to a 5-V system environment and vice versa, from a 2.5-V to a
3.3-V system environment and vice versa.
The SN74LVCC3245A is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated. The control circuitry (DIR, OE) is powered by VCCA
.
ORDERING INFORMATION
TA
PACKAGE(1)
Tube of 25
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SN74LVCC3245ADW
SN74LVCC3245ADWR
SN74LVCC3245ANSR
SN74LVCC3245ADBR
SN74LVCC3245ADBQR
SN74LVCC3245APW
SN74LVCC3245APWR
SN74LVCC3245APWT
SOIC – DW
LVCC3245A
Reel of 2000
Reel of 2000
Reel of 2000
SOP – NS
LVCC3245A
LH245A
SSOP – DB
–40°C to 85°C
SSOP (QSOP) – DBQ Reel of 2500
Tube of 60
LVCC3245A
TSSOP – PW
Reel of 2000
Reel of 250
LH245A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(EACH TRANSCEIVER)
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 1996–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O–NOVEMBER 1996–REVISED MARCH 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
2
DIR
22
OE
B1
3
A1
21
To Seven Other Channels
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCA
Supply voltage range
VCCB
–0.5
6 V
All A ports(2)
–0.5 VCCA + 0.5
VI
Input voltage range
All B ports(3)
Except I/O ports(2)
All A ports
All B ports
VI < 0
–0.5 VCCB + 0.5
V
V
–0.5 VCCA + 0.5
–0.5 VCCA + 0.5
VO
Output voltage range(3)
–0.5 VCCB + 0.5
IIK
IOK
IO
Input clamp current
–50
–50
±50
±100
63
mA
mA
mA
mA
Output clamp current
VO < 0
Continuous output current
Continuous current through VCCA, VCCB, or GND
DB package
DBQ package
DW package
NS package
PW package
61
θJA
Package thermal impedance(4)
46
°C/W
65
88
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) This value is limited to 4.6 V maximum.
(3) This value is limited to 6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O–NOVEMBER 1996–REVISED MARCH 2005
Recommended Operating Conditions(1)
VCCA
VCCB
MIN NOM
MAX UNIT
VCCA
VCCB
Supply voltage
Supply voltage
2.3
3
3.3
5
3.6
5.5
V
V
2.3 V
2.7 V
3 V
3 V
3 V
1.7
2
VIHA
VIHB
VILA
VILB
VIH
High-level input voltage
High-level input voltage
Low-level input voltage
V
V
V
V
V
V
3.6 V
5.5 V
3 V
2
3.6 V
2.3 V
2.7 V
3 V
2
2
3 V
2
3.6 V
5.5 V
3 V
2
3.6 V
2.3 V
2.7 V
3 V
3.85
0.7
0.8
3 V
3.6 V
5.5 V
3 V
0.8
3.6 V
2.3 V
2.7 V
3 V
0.8
0.8
3 V
0.8
Low-level input voltage
3.6 V
5.5 V
3 V
0.8
3.6 V
2.3 V
2.7 V
3 V
1.65
1.7
2
3 V
High-level input voltage (control pins)
(referenced to VCCA
)
3.6 V
5.5 V
3 V
2
3.6 V
2.3 V
2.7 V
3 V
2
0.7
0.8
3 V
Low-level input voltage (control pins)
VIL
(referenced to VCCA
)
3.6 V
5.5 V
0.8
3.6 V
0.8
VIA
Input voltage
Input voltage
Output voltage
Output voltage
0
0
0
0
VCCA
VCCB
VCCA
VCCB
–8
V
V
V
V
VIB
VOA
VOB
2.3 V
2.7 V
3 V
3 V
3 V
–12
–24
–24
–12
–12
–24
–24
8
IOHA
IOHB
IOLA
High-level output current
High-level output current
Low-level output current
mA
mA
mA
3 V
2.7 V
2.3 V
2.7 V
3 V
4.5 V
3 V
3 V
3 V
2.7 V
2.3 V
2.7 V
3 V
4.5 V
3 V
3 V
12
3 V
24
2.7 V
4.5 V
24
(1) All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O–NOVEMBER 1996–REVISED MARCH 2005
Recommended Operating Conditions (continued)
VCCA
2.3 V
2.7 V
VCCB
3 V
MIN NOM
MAX UNIT
12
3 V
12
IOLB
Low-level output current
mA
24
3 V
3 V
2.7 V
4.5 V
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
10
85
ns/V
TA
–40
°C
4
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O–NOVEMBER 1996–REVISED MARCH 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCCA
3 V
VCCB
3 V
MIN
2.9
2
TYP
MAX UNIT
IOH = –100 µA
3
IOH = –8 mA
2.3 V
2.7 V
3 V
3 V
3 V
2.2
2.4
2.2
2
2.5
2.8
2.6
2.3
3
VOHA
IOH = –12 mA
V
3 V
3 V
3 V
IOH = –24 mA
IOH = –100 µA
IOH = –12 mA
2.7 V
3 V
4.5 V
3 V
2.9
2.4
2.4
2.2
3.2
2.3 V
2.7 V
3 V
3 V
VOHB
3 V
2.8
2.6
4.2
V
3 V
IOH = –24 mA
2.7 V
3 V
4.5 V
3 V
IOL = 100 µA
IOL = 8 mA
IOL = 12 mA
0.1
0.6
2.3 V
2.7 V
3 V
3 V
VOLA
3 V
0.1
0.2
0.2
0.5
0.5
0.5
0.1
0.4
0.5
0.5
±1
V
V
3 V
IOL = 24 mA
2.7 V
3 V
4.5 V
3 V
IOL = 100 µA
IOL = 12 mA
2.3 V
3 V
3 V
VOLB
3 V
0.2
0.2
±0.1
±0.1
±0.5
5
IOL = 24 mA
2.7 V
4.5 V
3.6 V
5.5 V
3.6 V
Open
3.6 V
5.5 V
3.6 V
5.5 V
II
Control inputs VI = VCCA or GND
3.6 V
µA
µA
±1
(1)
IOZ
A or B ports
B to A
VO = VCCA/B or GND,
VI = VIL or VIH
3.6 V
3.6 V
±5
A port = VCCA or GND,
IO = 0
50
ICCA
5
50
µA
µA
B port = VCCB or GND,
IO = 0
3.6 V
3.6 V
5
50
5
50
ICCB
A to B
A port = VCCA or GND,
IO = 0
8
80
VI = VCCA – 0.6 V, Other inputs at VCCA or GND,
OE at GND and DIR at VCCA
A port
OE
3.6 V
3.6 V
3.6 V
3.6 V
3.6 V
3.6 V
3.6 V
5.5 V
0.35
0.35
0.35
1
0.5
0.5
0.5
1.5
VI = VCCA – 0.6 V, Other inputs at VCCA or GND,
DIR at VCCA
(2)
(2)
∆ICCA
mA
mA
VI = VCCA – 0.6 V, Other inputs at VCCA or GND,
OE at GND
DIR
VI = VCCB – 2.1 V, Other inputs at VCCB or GND,
OE at GND and DIR at GND
∆ICCB
B port
Ci
Control inputs VI = VCCA or GND
A or B ports VO = VCCA/B or GND
Open
3.3 V
Open
5 V
4
pF
pF
Cio
18.5
(1) For I/O ports, the parameter IOZ includes the input leakage current.
(2) This is the increase in supply current for each input that is at one of the specified voltage levels, rather than 0 V or the associated VCC
.
5
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O–NOVEMBER 1996–REVISED MARCH 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 4)
VCCA = 2.5 V
± 0.2 V,
VCCB = 3.3 V
± 0.3 V
VCCA = 2.7 V TO VCCA = 2.7 V TO
3.6 V,
VCCB = 5 V
± 0.5 V
3.6 V,
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1
MAX
MIN
1
MAX
MIN
1
MAX
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
tPZL
tPZH
tPLZ
tPHZ
tPLZ
tPHZ
9.4
9.1
6
5.3
5.8
7
7.1
7.2
6.4
7.6
9.7
9.5
9.2
9.9
6.6
6.9
7.5
7.9
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
1
1
1
1
11.2
9.9
1
1
B
1
1
1
1
14.5
12.9
13
1
9.2
9.5
8.1
8.4
7
1
OE
OE
OE
OE
1
1
1
1
1
1
1
12.8
7.1
1
1
1
1
1
1
6.9
1
7.8
7.3
7
1
1
8.8
1
1
1
8.9
1
1
Operating Characteristics
VCCA = 3.3 V, VCCB = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Outputs enabled
Outputs disabled
38
Cpd
Power dissipation capacitance per transceiver
CL = 50, f = 10 MHz
pF
4.5
(1)
Power-Up Considerations
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device pins. To guard against such power-up problems, take these
precautions:
1. Connect ground before any supply voltage is applied.
2. Power up the control side of the device (VCCA for all four of these devices).
3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA
.
4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
ramp it with VCCA. Otherwise, keep DIR low.
(1) Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.
6
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O–NOVEMBER 1996–REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION FOR A PORT
VCCA = 2.5 V ± 0.2 V AND VCCB = 3.3 V ± 0.3 V
2 × V
CC
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
500 Ω
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
- 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O–NOVEMBER 1996–REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION FOR B PORT
VCCA = 2.5 V ± 0.2 V AND VCCB = 3.3 V ± 0.3 V
2 × V
CC
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
t
pd
Open
C = 50 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
500 Ω
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
- 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
8
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O–NOVEMBER 1996–REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION FOR B PORT
VCCA = 3.6 V and vCCB = 5.5 V
2 × V
CC
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
C = 50 pF
(see Note A)
t
/t
Open
L
PLH PHL
500 Ω
t
/t
2 × V
CC
PLZ PZL
t
/t
Open
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
B-Port
Input
50% V
50% V
CC
CC
2.7 V
0 V
Output
Control
0 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
PLZ
PZL
Output
Waveform 1
V
V
CC
V
CC
50% V
CC
S1 at 2 × V
CC
V
V
+ 0.3 V
t
PHZ
OL
1.5 V
1.5 V
Input
OL
(see Note B)
0 V
t
PZH
t
PHL
t
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
- 0.3 V
OH
B-Port
Output
50% V
CC
50% V
50% V
CC
CC
≈0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
9
SN74LVCC3245A
OCTAL BUS TRANSCEIVER
WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS585O–NOVEMBER 1996–REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION FOR A AND B PORT
VCCA AND VCCB = 3.6 V
7 V
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
C = 50 pF
(see Note A)
L
t
/t
Open
7 V
500 Ω
PLH PHL
t
/t
PLZ PZL
t
/t
Open
PHZ PZH
LOAD CIRCUIT
t
w
2.7 V
1.5 V
1.5 V
Input
2.7 V
Output
Control
1.5 V
1.5 V
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
PZL
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
2.7 V
0 V
1.5 V
V
V
+ 0.3 V
PHZ
OL
1.5 V
1.5 V
V
OL
Input
(see Note B)
t
t
PZH
t
PHL
t
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
- 0.3 V
OH
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
1.5 V
Output
≈0 V
OL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
10
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
74LVCC3245ADBQRE4
74LVCC3245ADBQRG4
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP/
QSOP
DBQ
24
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SSOP/
QSOP
DBQ
24
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SN74LVCC3245ADBLE
SN74LVCC3245ADBQR
OBSOLETE
ACTIVE
SSOP
DB
24
24
TBD
Call TI
Call TI
SSOP/
QSOP
DBQ
2500 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
SN74LVCC3245ADBR
SN74LVCC3245ADBRE4
SN74LVCC3245ADW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SO
DB
DB
24
24
24
24
24
24
24
24
24
24
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
DW
DW
DW
NS
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCC3245ADWE4
SN74LVCC3245ADWR
SN74LVCC3245ADWRE4
SN74LVCC3245ANSR
SN74LVCC3245ANSRE4
SN74LVCC3245APW
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
PW
PW
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCC3245APWE4
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCC3245APWLE
SN74LVCC3245APWR
OBSOLETE TSSOP
PW
PW
24
24
TBD
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVCC3245APWRE4
SN74LVCC3245APWT
SN74LVCC3245APWTE4
PW
PW
PW
24
24
24
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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