SN74LVCC4245A-EP_15 [TI]

OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS;


型号：	SN74LVCC4245A-EP_15
厂家：	TEXAS INSTRUMENTS
描述：	OCTAL DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS 输出元件
文件：	总19页 (文件大小：654K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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ꢎ ꢆꢏꢊꢄ ꢐꢑ ꢀ ꢏ ꢒꢊꢁꢀ ꢆꢌꢓ ꢅꢌꢒ ꢔ ꢓꢏ ꢕ ꢊꢖꢗ ꢑꢀ ꢏꢊꢐꢄ ꢌ ꢎ ꢑꢏ ꢍꢑꢏ ꢅ ꢎ ꢄꢏꢊ ꢘ

ꢊꢁꢖ ꢇ ꢋꢀꢏꢊꢏ ꢌ ꢎ ꢑꢏ ꢍ ꢑꢏ

SCAS773A − JUNE 2004 − REVISED MARCH 2005

Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

Enhanced Diminishing Manufacturing

Sources (DMS) Support

DB, DW, OR PW PACKAGE

(TOP VIEW)

Enhanced Product-Change Notification

†

Qualification Pedigree

Bidirectional Voltage Translator

CCB

CCA

DIR

2.3 V to 3.6 V on A Port and 3 V to 5.5 V on

B Port

Control Inputs V /V Levels Are

IH IL

Referenced to V

Voltage

CCA

Latch-Up Performance Exceeds 250 mA Per

JESD 17

†

Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

GND

NC − No internal connection

description/ordering information

This 8-bit (octal) noninverting bus transceiver contains two separate supply rails. The B port is designed to track

, which accepts voltages from 3 V to 5.5 V, and the A port is designed to track V , which operates at

CCB

CCA

2.3 V to 3.6 V. This allows for translation from a 3.3-V to a 5-V system environment and vice versa, from a 2.5-V

to a 3.3-V system environment and vice versa.

The SN74LVCC3245A is designed for asynchronous communication between data buses. The device

transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the

direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are

isolated. The control circuitry (DIR, OE) is powered by V

CCA

ORDERING INFORMATION

ORDERABLE

TOP-SIDE

MARKING

†

PACKAGE

PART NUMBER

CLVCC3245AIDWREP

CLVCC3245AIDBREP

CLVCC3245AIPWREP

SOIC − DW

SSOP − DB

TSSOP − PW

Reel of 2000

LVCC3245A

LH245AEP

−40°C to 85°C

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢆ ꢇ ꢈꢃ ꢉꢊ ꢋꢌ ꢍ

ꢎꢆ ꢏꢊ ꢄ ꢐ ꢑꢀ ꢏ ꢒ ꢊꢁ ꢀꢆ ꢌꢓ ꢅ ꢌ ꢒ ꢔ ꢓ ꢏꢕ ꢊꢖ ꢗ ꢑꢀ ꢏꢊꢐꢄ ꢌ ꢎ ꢑꢏ ꢍꢑꢏ ꢅꢎ ꢄꢏꢊꢘ ꢌ

ꢊ ꢁꢖ ꢇ ꢋꢀꢏꢊꢏ ꢌ ꢎꢑꢏ ꢍꢑ ꢏꢀ

SCAS773A − JUNE 2004 − REVISED MARCH 2005

FUNCTION TABLE

(each transceiver)

INPUTS

OPERATION

DIR

B data to A bus

A data to B bus

Isolation

logic diagram (positive logic)

DIR

To Seven Other Channels

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

and V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V

CCA

CCB

Input voltage range, V : All A ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

CCA

CCB

CCA

CCB

All B ports (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

Output voltage range, V (see Note 2): All A ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

All B ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Continuous current through V

, V

, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

CCA CCB

Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W

DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Storage temperature range, T

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. This value is limited to 4.6 V maximum.

2. This value is limited to 6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢎ ꢆꢏꢊꢄ ꢐꢑ ꢀ ꢏ ꢒꢊꢁꢀ ꢆꢌꢓ ꢅꢌꢒ ꢔ ꢓꢏ ꢕ ꢊꢖꢗ ꢑꢀ ꢏꢊꢐꢄ ꢌ ꢎ ꢑꢏ ꢍꢑꢏ ꢅ ꢎ ꢄꢏꢊ ꢘ

ꢊꢁꢖ ꢇ ꢋꢀꢏꢊꢏ ꢌ ꢎ ꢑꢏ ꢍꢑ ꢏ

SCAS773A − JUNE 2004 − REVISED MARCH 2005

recommended operating conditions (see Note 4)

CCA

CCB

MIN NOM

MAX

3.6

UNIT

Supply voltage

2.3

3.3

CCA

5.5

CCB

2.3 V

2.7 V

3 V

1.7

High-level input voltage

Low-level input voltage

IHA

IHB

ILA

ILB

3.6 V

5.5 V

3 V

3.6 V

2.3 V

2.7 V

3 V

3.6 V

5.5 V

3 V

3.6 V

2.3 V

2.7 V

3 V

3.85

0.7

0.8

1.65

3 V

3.6 V

5.5 V

3 V

3.6 V

2.3 V

2.7 V

3 V

Low-level input voltage

3.6 V

5.5 V

3 V

3.6 V

2.3 V

2.7 V

3 V

1.7

3 V

High-level input voltage (control pins)

(Referenced to V

)

3.6 V

5.5 V

3 V

CCA

3.6 V

2.3 V

2.7 V

3 V

0.7

0.8

3 V

Low-level input voltage (control pins)

(Referenced to V

)

3.6 V

5.5 V

CCA

3.6 V

Input voltage

Output voltage

CCA

CCB

CCA

CCB

NOTE 4: All unused inputs of the device must be held at the associated V

or GND to ensure proper device operation. Refer to the TI application

report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊ ꢁꢖ ꢇ ꢋꢀꢏꢊꢏ ꢌ ꢎꢑꢏ ꢍꢑ ꢏꢀ

SCAS773A − JUNE 2004 − REVISED MARCH 2005

recommended operating conditions (see Note 4) (continued)

MIN NOM

MAX

−8

UNIT

CCA

CCB

2.3 V

3 V

2.7 V

3.3 V

2.3 V

2.7 V

3.3 V

2.3 V

2.7 V

3.3 V

2.3 V

2.7 V

3.3 V

3 V

−12

−24

−12

−24

High-level output current

Low-level output current

OHA

OHB

OLA

OLB

3.3 V

3 V

3.3 V

3 V

∆t/∆v

Input transition rise or fall rate

Operating free-air temperature

ns/V

−40

°C

NOTE 4: All unused inputs of the device must be held at the associated V

or GND to ensure proper device operation. Refer to the TI application

report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊꢁꢖ ꢇ ꢋꢀꢏꢊꢏ ꢌ ꢎ ꢑꢏ ꢍꢑ ꢏ

SCAS773A − JUNE 2004 − REVISED MARCH 2005

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2.9

TYP

MAX

UNIT

CCA

3 V

CCB

3 V

= −100 µA

= −8 mA

2.3 V

2.7 V

3 V

2.2

2.4

2.2

2.5

2.8

2.6

2.3

= −12 mA

OHA

3 V

= −24 mA

2.7 V

3 V

4.5 V

3 V

= −100 µA

2.9

2.4

2.2

3.2

2.3 V

2.7 V

3 V

= −12 mA

= −24 mA

3 V

2.8

2.6

4.2

OHB

OLA

3 V

2.7 V

3 V

4.5 V

3 V

= 100 µA

= 8 mA

0.1

0.6

0.5

0.1

0.4

0.5

2.3 V

2.7 V

3 V

= 12 mA

3 V

0.1

0.2

3 V

= 24 mA

2.7 V

3 V

4.5 V

3 V

= 100 µA

= 12 mA

2.3 V

3 V

OLB

3 V

0.2

0.1

0.5

= 24 mA

3 V

4.5 V

3.6 V

5.5 V

3.6 V

Control inputs V = V

CCA

or GND

3.6 V

µA

†

= V

CCA/B

or GND,

V = V or V

3.6 V

A or B ports

A port = V

= 0

Open

3.6 V

5.5 V

3.6 V

5.5 V

CCA

B to A

µA

CCA

B port = V

or GND,

= 0

3.6 V

CCB

A to B

A port

A port = V

= 0

3.6 V

CCB

CCA

V = V

CCA

− 0.6 V, Other inputs at V

or GND,

CCA

CCB

3.6 V

5.5 V

0.35

0.5

1.5

OE at GND and DIR at V

CCA

V = V

DIR at V

CCA

− 0.6 V, Other inputs at V

or GND,

CCA

‡

∆I

CCA

V = V

OE at GND

− 0.6 V, Other inputs at V

− 2.1 V, Other inputs at V

CCB

CCA

DIR

V = V

B port

CCB

OE at GND and DIR at GND

Control inputs V = V

CCA

or GND

Open

3.3 V

Open

5 V

A or B ports

= V

or GND

18.5

CCA/B

†

‡

For I/O ports, the parameter I

includes the input leakage current.

This is the increase in supply current for each input that is at one of the specified voltage levels, rather than 0 V or the associated V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢆ ꢇ ꢈꢃ ꢉꢊ ꢋꢌ ꢍ

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SCAS773A − JUNE 2004 − REVISED MARCH 2005

switching characteristics over recommended operating free-air temperature range (unless

otherwise noted) (see Figures 1 through 4)

= 2.5 V

0.2 V,

= 3.3 V

0.3 V

= 2.7 V

CCA

TO 3.6 V,

V = 5 V

TO 3.6 V,

= 3.3 V

FROM

(INPUT)

(OUTPUT)

CCB

0.5 V

CCB

0.3 V

PARAMETER

UNIT

MIN

MAX

9.4

MIN

MAX

MIN

MAX

7.1

7.2

6.4

7.6

9.7

9.5

9.2

9.9

6.6

6.9

7.5

7.9

PHL

PLH

PHL

PLH

PZL

PZH

PZL

PZH

PLZ

PHZ

PLZ

PHZ

9.1

5.3

5.8

11.2

9.9

14.5

12.9

9.2

9.5

8.1

8.4

12.8

7.1

6.9

7.8

7.3

8.8

8.9

operating characteristics, V

= 3.3 V, V

= 5 V, T = 25°C

CCA

CCB

PARAMETER

TEST CONDITIONS

= 50, f = 10 MHz

TYP

UNIT

Outputs enabled

Outputs disabled

Power dissipation capacitance per transceiver

4.5

†

power-up considerations

TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up

sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other

anomalies caused by improperly biased device pins. To guard against such power-up problems, take these

precautions:

1. Connect ground before any supply voltage is applied.

2. Power up the control side of the device (V

for all four of these devices).

CCA

3. Tie OE to V

with a pullup resistor so that it ramps with V

CCA

4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),

ramp it with V . Otherwise, keep DIR low.

CCA

†

Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢎ ꢆꢏꢊꢄ ꢐꢑ ꢀ ꢏ ꢒꢊꢁꢀ ꢆꢌꢓ ꢅꢌꢒ ꢔ ꢓꢏ ꢕ ꢊꢖꢗ ꢑꢀ ꢏꢊꢐꢄ ꢌ ꢎ ꢑꢏ ꢍꢑꢏ ꢅ ꢎ ꢄꢏꢊ ꢘ

ꢊꢁꢖ ꢇ ꢋꢀꢏꢊꢏ ꢌ ꢎ ꢑꢏ ꢍꢑ ꢏ

SCAS773A − JUNE 2004 − REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION FOR A PORT

= 2.5 V 0.2 V AND V

= 3.3 V 0.3 V

CCA

CCB

2 × V

Open

500 Ω

From Output

Under Test

TEST

GND

Open

= 30 pF

2 × V

GND

PLZ PZL

500 Ω

(see Note A)

PHZ PZH

LOAD CIRCUIT

Input

Timing

Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Output

Control

(low-level

enabling)

Data

Input

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

PZL

PLZ

Output

Waveform 1

Input

S1 at 2 × V

(see Note B)

+ 0.15 V

0 V

PZH

PHZ

PLH

PHL

Output

Waveform 2

S1 at GND

− 0.15 V

Output

0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A.

includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.

D. The outputs are measured one at a time, with one transition per measurement.

and t

PHL

are the same as t

dis

PLZ

PZL

PLH

PHZ

PZH

are the same as t

are the same as t .

H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊ ꢁꢖ ꢇ ꢋꢀꢏꢊꢏ ꢌ ꢎꢑꢏ ꢍꢑ ꢏꢀ

SCAS773A − JUNE 2004 − REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION FOR B PORT

= 2.5 V 0.2 V AND V

= 3.3 V 0.3 V

CCA

CCB

2 × V

Open

500 Ω

From Output

Under Test

TEST

GND

Open

= 50 pF

2 × V

GND

PLZ PZL

500 Ω

(see Note A)

PHZ PZH

LOAD CIRCUIT

Input

Timing

Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

Output

Control

(low-level

enabling)

Data

Input

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

PZL

PLZ

Output

Waveform 1

Input

S1 at 2 × V

(see Note B)

+ 0.15 V

0 V

PZH

PHZ

PLH

PHL

Output

Waveform 2

S1 at GND

− 0.15 V

Output

0 V

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

NOTES: A.

includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.

D. The outputs are measured one at a time, with one transition per measurement.

and t

PHL

are the same as t

dis

PLZ

PZL

PLH

PHZ

PZH

are the same as t

are the same as t .

H. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢃ

ꢉ

ꢊ

ꢋ

ꢌ

ꢍ

ꢌ

ꢀ

ꢎ ꢆꢏꢊꢄ ꢐꢑ ꢀ ꢏ ꢒꢊꢁꢀ ꢆꢌꢓ ꢅꢌꢒ ꢔ ꢓꢏ ꢕ ꢊꢖꢗ ꢑꢀ ꢏꢊꢐꢄ ꢌ ꢎ ꢑꢏ ꢍꢑꢏ ꢅ ꢎ ꢄꢏꢊ ꢘ

ꢊꢁꢖ ꢇ ꢋꢀꢏꢊꢏ ꢌ ꢎ ꢑꢏ ꢍꢑ ꢏ

SCAS773A − JUNE 2004 − REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION FOR B PORT

= 3.6 V AND V = 5.5 V

CCA

CCB

2 × V

Open

500 Ω

From Output

Under Test

GND

TEST

= 50 pF

Open

PLH PHL

500 Ω

(see Note A)

2 × V

PLZ PZL

Open

PHZ PZH

LOAD CIRCUIT

B-Port

Input

50% V

2.7 V

0 V

Output

Control

0 V

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

PLZ

PZL

Output

Waveform 1

50% V

S1 at 2 × V

(see Note B)

+ 0.3 V

1.5 V

Input

0 V

PZH

PHZ

PHL

PLH

Output

Waveform 2

S1 at Open

(see Note B)

− 0.3 V

B-Port

Output

50% V

≈0 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A.

C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 3. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢆ ꢇ ꢈꢃ ꢉꢊ ꢋꢌ ꢍ

ꢎꢆ ꢏꢊ ꢄ ꢐ ꢑꢀ ꢏ ꢒ ꢊꢁ ꢀꢆ ꢌꢓ ꢅ ꢌ ꢒ ꢔ ꢓ ꢏꢕ ꢊꢖ ꢗ ꢑꢀ ꢏꢊꢐꢄ ꢌ ꢎ ꢑꢏ ꢍꢑꢏ ꢅꢎ ꢄꢏꢊꢘ ꢌ

ꢊ ꢁꢖ ꢇ ꢋꢀꢏꢊꢏ ꢌ ꢎꢑꢏ ꢍꢑ ꢏꢀ

SCAS773A − JUNE 2004 − REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION FOR A AND B PORT

AND V

= 3.6 V

CCA

CCB

7 V

Open

GND

500 Ω

From Output

Under Test

TEST

= 50 pF

Open

7 V

500 Ω

PLH PHL

(see Note A)

PLZ PZL

PHZ PZH

Open

LOAD CIRCUIT

2.7 V

1.5 V

Input

2.7 V

0 V

Output

Control

1.5 V

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

PLZ

PZL

Output

Waveform 1

S1 at 7 V

3.5 V

2.7 V

0 V

1.5 V

+ 0.3 V

1.5 V

Input

(see Note B)

PZH

PHZ

PHL

PLH

Output

Waveform 2

S1 at Open

(see Note B)

− 0.3 V

1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

NONINVERTING OUTPUTS

1.5 V

Output

≈0 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A.

C includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

Figure 4. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jan-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

CLVCC3245AIDBREP

CLVCC3245AIDWREP

CLVCC3245AIPWREP

V62/05602-01XE

ACTIVE

SSOP

SOIC

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

TSSOP

SSOP

SOIC

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

V62/05602-01YE

Green (RoHS

& no Sb/Br)

V62/05602-01ZE

Green (RoHS

& no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

30-Jan-2012

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN74LVCC3245A-EP :

Catalog: SN74LVCC3245A

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CLVCC3245AIDBREP

CLVCC3245AIDWREP

CLVCC3245AIPWREP

SSOP

SOIC

2000

330.0

16.4

24.4

16.4

8.2

10.85 15.8

6.95 8.3

8.8

2.5

2.7

1.6

12.0

8.0

16.0

24.0

16.0

TSSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CLVCC3245AIDBREP

CLVCC3245AIDWREP

CLVCC3245AIPWREP

SSOP

SOIC

2000

367.0

38.0

45.0

38.0

TSSOP

Pack Materials-Page 2

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

0,15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

0,25

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SN74LVCC4245A-EP_15 [TI]

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