SN74LVCC3245APW [TI]
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS; 具有可调输出电压和三态输出的八路总线收发器
| 型号： | SN74LVCC3245APW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS |
| 文件： | 总10页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCC3245A
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE
AND 3-STATE OUTPUTS
SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998
DB, DW, OR PW PACKAGE
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
(TOP VIEW)
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
V
1
2
3
4
5
6
7
8
9
24
V
CCB
CCA
DIR
23 NC
22 OE
21 B1
20 B2
19 B3
18 B4
17 B5
16 B6
15 B7
14 B8
13 GND
A1
A2
A3
A4
A5
A6
A7
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
A8 10
description
GND 11
GND 12
This 8-bit (octal) noninverting bus transceiver
contains two separate supply rails. The B port is
NC – No internal connection
designed to track V
, which accepts voltages
CCB
from 3 V to 5.5 V, and the A port is designed to
track V , which operates at 2.3 V to 3.6 V. This
CCA
allows for translation from a 3.3-V to a 5-V system
environment and vice versa, or from a 2.5-V to a
3.3-V system environment and vice versa.
The SN74LVCC3245A is designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated.
The SN74LVCC3245A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC3245A
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE
AND 3-STATE OUTPUTS
SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998
logic diagram (positive logic)
2
DIR
22
OE
3
A1
21
B1
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CCB
CCA
Input voltage range, V : All A port (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
+ 0.5 V
I
CCA
CCB
CCA
CCA
CCB
All B port (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Except I/O ports (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Output voltage range, V (see Note 1): All A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
All B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
O
, V
, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CCA CCB
JA
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. This value is limited to 6 V maximum.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC3245A
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE
AND 3-STATE OUTPUTS
SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998
recommended operating conditions (see Note 4)
V
CCA
V
CCB
MIN NOM
MAX
3.6
UNIT
V
V
V
Supply voltage
Supply voltage
2.3
3
3.3
5
CCA
5.5
V
CCB
2.3 V
2.7 V
3 V
3 V
3 V
1.7
2
V
IHA
V
IHB
V
ILA
V
ILB
High-level input voltage
High-level input voltage
Low-level input voltage
Low-level input voltage
V
OB
V
OA
V
OB
V
OA
≤ 0.1 V,
≤ 0.1 V,
≤ 0.1 V,
≤ 0.1 V,
V
OB
V
OA
V
OB
V
OA
≥ V
≥ V
≥ V
≥ V
– 0.1 V
– 0.1 V
– 0.1 V
– 0.1 V
V
V
V
V
CCB
CCA
CCB
CCA
3.6 V
5.5 V
3 V
2
3.6 V
2.3 V
2.7 V
3 V
2
2
3 V
2
3.6 V
5.5 V
3 V
2
3.6 V
2.3 V
2.7 V
3 V
3.85
0.7
0.8
0.8
0.8
0.8
0.8
0.8
1.65
3 V
3.6 V
5.5 V
3 V
3.6 V
2.3 V
2.7 V
3 V
3 V
3.6 V
5.5 V
3.6 V
V
V
V
V
Input voltage
Input voltage
Output voltage
Output voltage
0
0
0
0
V
V
V
V
V
IA
CCA
CCB
CCA
V
V
V
IB
OA
OB
CCB
–8
2.3 V
2.7 V
3.3 V
2.3 V
2.7 V
3.3 V
2.3 V
2.7 V
3.3 V
2.3 V
2.7 V
3.3 V
3 V
3 V
I
I
I
I
High-level output current
High-level output current
Low-level output current
Low-level output current
–12
–24
–12
–12
–24
8
mA
mA
mA
mA
OHA
OHB
OLA
OLB
3 V
3.3 V
3.3 V
3 V
3 V
3 V
12
3 V
24
3.3 V
3.3 V
3 V
12
12
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
–40
85
°C
NOTE 4: AllunusedinputsofthedevicemustbeheldattheassociatedV
orGNDtoensureproperdeviceoperation. RefertotheTIapplication
CC
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC3245A
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE
AND 3-STATE OUTPUTS
SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.9
2
TYP
MAX
UNIT
V
V
CCB
CCA
I
I
= –100 µA
3 V
3 V
3
OH
= –8 mA
2.3 V
2.7 V
3 V
3 V
3 V
3 V
3 V
OH
2.2
2.4
2.2
2
2.5
2.8
2.6
2.3
3
V
I
= –12 mA
V
OHA
OH
3 V
I
I
I
= –24 mA
= –100 µA
= –12 mA
OH
OH
OH
2.7 V
3 V
4.5 V
3 V
2.9
2.4
2.4
2.2
3.2
2.3 V
2.7 V
3 V
3 V
V
3 V
2.8
2.6
4.2
V
OHB
OLA
3 V
I
= –24 mA
OH
2.7 V
3 V
4.5 V
3 V
I
I
I
= 100 µA
= 8 mA
0.1
0.6
0.5
0.5
0.5
0.1
0.4
0.5
0.5
±1
OL
OL
OL
2.3 V
2.7 V
3 V
3 V
V
= 12 mA
3 V
0.1
0.2
0.2
V
V
3 V
I
= 24 mA
OL
2.7 V
3 V
4.5 V
3 V
I
I
= 100 µA
OL
= 12 mA
2.3 V
3 V
OL
V
OLB
3 V
0.2
0.2
±0.1
±0.1
±0.5
5
I
= 24 mA
3 V
OL
4.5 V
3.6 V
5.5 V
3.6 V
Open
3.6 V
5.5 V
3.6 V
5.5 V
I
I
Control inputs V = V
or GND
3.6 V
µA
µA
I
I
CCA
±1
†
V
= V
or GND,
or GND,
V = V or V
3.6 V
3.6 V
±5
A or B ports
B to A
O
CCA/B
I
IL
IH
OZ
A port = V
I
O
= 0
50
CCA
I
5
50
µA
µA
CCA
B port = V
or GND,
or GND,
I
= 0
3.6 V
3.6 V
CCB
O
O
5
50
5
50
I
A to B
A port
A port = V
I
= 0
CCB
CCA
8
80
V = V
– 0.6 V, Other inputs at V
or GND,
I
CCA
CCA
CCA
CCA
CCB
3.6 V
3.6 V
3.6 V
3.6 V
3.6 V
3.6 V
3.6 V
5.5 V
0.35
0.35
0.35
1
0.5
0.5
0.5
1.5
OE at GND and DIR at V
CCA
– 0.6 V, Other inputs at V
V = V
DIR at V
or GND,
or GND,
or GND,
I
CCA
CCA
‡
‡
mA
mA
∆I
∆I
OE
CCA
V = V
OE at GND
– 0.6 V, Other inputs at V
– 2.1 V, Other inputs at V
CCB
I
CCA
DIR
V = V
I
B port
CCB
OE at GND and DIR at GND
C
C
Control inputs V = V
or GND
Open
3.3 V
3.3 V
3.3 V
Open
5 V
4
18.5
38
pF
pF
i
I
CCA
= V
A or B ports
A to B
V
or GND
CCA/B
io
O
Outputs enabled
Outputs enabled
5 V
C
pF
pd
B to A
5 V
36.5
†
‡
For I/O ports, the parameter I
OZ
includes the input leakage current.
This is the increase in supply current for each input that is at one of the specified voltage levels rather than 0 V or the associated V
.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC3245A
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE
AND 3-STATE OUTPUTS
SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 4)
V
V
= 2.5 V ± 0.2 V,
= 3.3 V ± 0.3 V
V
CCA
V
= 2.7 V TO 3.6 V,
V
V
= 2.7 V TO 3.6 V,
CCA
CCB
CCA
FROM
(INPUT)
TO
(OUTPUT)
= 5 V ± 0.5 V
= 3.3 V ± 0.3 V
CCB
MIN
CCB
MIN
PARAMETER
UNIT
MIN
MAX
9.4
MAX
MAX
t
t
t
t
t
t
t
t
t
t
t
t
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
6
5.3
5.8
7
1
1
1
1
1
1
1
1
1
1
1
1
7.1
7.2
6.4
7.6
9.7
9.5
9.2
9.9
6.6
6.9
7.5
7.9
PHL
PLH
PHL
PLH
PZL
PZH
PZL
PZH
PLZ
PHZ
PLZ
PHZ
A
B
A
A
B
A
B
ns
ns
ns
ns
ns
ns
9.1
11.2
9.9
B
14.5
12.9
13
9.2
9.5
8.1
8.4
5.5
7.8
7.3
7
OE
OE
OE
OE
12.8
7.1
6.9
8.8
8.9
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC3245A
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE
AND 3-STATE OUTPUTS
SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION FOR A PORT
V
= 2.5 V ± 0.2 V AND V
= 3.3 V ± 0.3 V
CCA
CCB
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC3245A
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE
AND 3-STATE OUTPUTS
SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION FOR B PORT
V
= 2.5 V ± 0.2 V AND V
= 3.3 V ± 0.3 V
CCA
CCB
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 50 pF
t
2 × V
CC
GND
L
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 2. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC3245A
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE
AND 3-STATE OUTPUTS
SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION FOR B PORT
V
= 3.6 V AND V
= 5.5 V
CCA
CCB
2 × V
CC
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
/t
Open
PLH PHL
/t
C
= 50 pF
L
t
2 × V
CC
Open
PLZ PZL
500 Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
B-Port
Input
50% V
50% V
CC
CC
2.7 V
0 V
0 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PLZ
Output
Waveform 1
V
V
CC
V
CC
50% V
CC
CC
V
V
+ 0.3 V
– 0.3 V
S1 at 2 × V
(see Note B)
OL
1.5 V
1.5 V
CC
Input
OL
0 V
V
t
PHZ
t
t
PZH
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
OH
OH
B-Port
Output
50% V
50% V
50% V
CC
CC
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 3. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCC3245A
OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE
AND 3-STATE OUTPUTS
SCAS585F – NOVEMBER 1996 – REVISED AUGUST 1998
PARAMETER MEASUREMENT INFORMATION FOR A AND B PORT
V
AND V
= 3.6 V
CCA
CCB
7 V
S1
Open
500 Ω
From Output
Under Test
TEST
S1
GND
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
PLZ PZL
/t
500 Ω
(see Note A)
t
Open
PHZ PZH
LOAD CIRCUIT
t
w
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
0 V
Output
Control
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PLZ
Output
3.5 V
2.7 V
0 V
Waveform 1
S1 at 7 V
(see Note B)
1.5 V
V
V
+ 0.3 V
– 0.3 V
OL
1.5 V
1.5 V
Input
V
OL
t
PHZ
t
t
PHL
PZH
t
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
OH
OH
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 4. Load Circuit and Voltage Waveforms
9
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