SN74LVTH126PWRG4_技术文档

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢊ

ꢋ

ꢀ

ꢁ

ꢌ

ꢃ

ꢍ ꢎꢍ ꢏꢅ ꢐꢑꢆ ꢒ ꢓꢐꢔꢕ ꢓꢖꢄ ꢗ ꢑꢓꢀ ꢑ ꢓꢘ ꢘꢗ ꢕ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢊ

ꢀ

ꢙ

ꢚ

ꢆ

ꢇ

ꢍ

ꢏ

ꢀ

ꢆ

ꢐ

ꢆ

ꢗ

ꢛ

ꢓ

ꢆ

ꢖ

ꢓ

ꢆ

SCBS746B − JULY 2000 - REVISED OCTOBER 2003

SN54LVTH126 . . . J OR W PACKAGE

SN74LVTH126 . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

D

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

)

CC

Support Unregulated Battery Operation

Down to 2.7 V

1OE

1A

1Y

2OE

2A

2Y

V

CC

4OE

1

2

3

4

5

6

7

14

13

12

11

Typical V

<0.8 V at V

(Output Ground Bounce)

OLP

CC

= 3.3 V, T = 25°C

4A

4Y

A

I

and Power-Up 3-State Support Hot

off

Insertion

10 3OE

3A

3Y

9

8

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

GND

D

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

SN54LVTH126 . . . FK PACKAGE

(TOP VIEW)

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

3

2

1

20 19

18 4A

− 1000-V Charged-Device Model (C101)

1Y

NC

4

5

6

7

8

17

16

15

14

NC

4Y

description/ordering information

2OE

NC

3OE

These bus buffers are designed specifically for

2A

low-voltage (3.3-V) V

operation, but with the

CC

9 10 11 12 13

capability to provide a TTL interface to a 5-V

system environment.

The ’LVTH126 devices feature independent line

drivers with 3-state outputs. Each output is in the

high-impedance state when the associated

output-enable (OE) input is low.

NC − No internal connection

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

Tube

SN74LVTH126D

SOIC − D

LVTH126

Tape and reel

Tube

SN74LVTH126DR

SN74LVTH126NSR

SN74LVTH126DBR

SN74LVTH126PW

SN74LVTH126PWR

SN74LVTH126DGVR

SNJ54LVTH126J

SNJ54LVTH126W

SNJ54LVTH126FK

SOP − NS

LVTH126

LXH126

SSOP − DB

−40°C to 85°C

−55°C to 125°C

TSSOP − PW

LXH126

Tape and reel

Tube

TVSOP − DGV

CDIP − J

LXH126

SNJ54LVTH126J

SNJ54LVTH126W

SNJ54LVTH126FK

CFP − W

Tube

LCCC − FK

Tube

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  2003, Texas Instruments Incorporated

ꢓ ꢁ ꢄꢗꢀꢀ ꢛ ꢆꢇ ꢗꢕꢙ ꢚꢀ ꢗ ꢁ ꢛꢆꢗꢔ ꢜꢝ ꢞꢟ ꢠꢡꢢ ꢣꢤꢥ ꢦꢜ ꢢꢡ ꢦꢜꢧ ꢞꢦꢟ ꢖꢕ ꢛ ꢔ ꢓ ꢨꢆ ꢚꢛ ꢁ

ꢜ

ꢔ

ꢐ

ꢆ

ꢐ

ꢞ

ꢦ

ꢩ

ꢡ

ꢪ

ꢤ

ꢧ

ꢜ

ꢞ

ꢡ

ꢦ

ꢢ

ꢣ

ꢪ

ꢥ

ꢦ

ꢜ

ꢧ

ꢟ

ꢡ

ꢩ

ꢫ

ꢣ

ꢬ

ꢭ

ꢞ

ꢢ

ꢧ

ꢜ

ꢞ

ꢡ

ꢦ

ꢠ

ꢧ

ꢥ

ꢎ

ꢖ

ꢪ

ꢡ

ꢠ

ꢣ

ꢢ

ꢜ

ꢟ

ꢢ

ꢡ

ꢦ

ꢩ

ꢡ

ꢪ

ꢤ

ꢜ

ꢡ

ꢟ

ꢫ

ꢥ

ꢢ

ꢞ

ꢩ

ꢞ

ꢢ

ꢧ

ꢜ

ꢞ

ꢡ

ꢦ

ꢟ

ꢫ

ꢥ

ꢪ

ꢜ

ꢝ

ꢥ

ꢜ

ꢥ

ꢪ

ꢤ

ꢟ

ꢡ

ꢩ

ꢆ

ꢥ

ꢮ

ꢧ

ꢟ

ꢚ

ꢦ

ꢟ

ꢜ

ꢪ

ꢣ

ꢤ

ꢥ

ꢦ

ꢜ

ꢟ

ꢜ

ꢧ

ꢦ

ꢠ

ꢧ

ꢪ

ꢠ

ꢯ

ꢧ

ꢪ

ꢧ

ꢦ

ꢜ

ꢰ

ꢎ

ꢖ

ꢪ

ꢡ

ꢠ

ꢣ

ꢢ

ꢜ

ꢞ

ꢡ

ꢦ

ꢫꢧ ꢪ ꢧ ꢤ ꢥ ꢜ ꢥ ꢪ ꢟ ꢎ

ꢫ

ꢪ

ꢡ

ꢢ

ꢥ

ꢟ

ꢞ

ꢦ

ꢱ

ꢠ

ꢡ

ꢥ

ꢟ

ꢦ

ꢡ

ꢜ

ꢦ

ꢥ

ꢢ

ꢥ

ꢟ

ꢧ

ꢪ

ꢞ

ꢭ

ꢰ

ꢞ

ꢦ

ꢢ

ꢭ

ꢣ

ꢠ

ꢥ

ꢜ

ꢥ

ꢟ

ꢜ

ꢞ

ꢦ

ꢱ

ꢡ

ꢩ

ꢧ

ꢭ

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢍ

ꢂ

ꢃ

ꢄ

ꢐ

ꢍ

ꢅ

ꢑ

ꢏ

ꢆ

ꢀ

ꢇ

ꢒ

ꢆꢐ

ꢈ

ꢉ

ꢓ

ꢊ

ꢐ

ꢗ

ꢋ

ꢀ

ꢔ

ꢛ

ꢁ

ꢕ

ꢓ

ꢌ

ꢓ

ꢆ

ꢃ

ꢖ

ꢄ

ꢓ

ꢅ

ꢗ

ꢆ

ꢇ

ꢑ

ꢈ

ꢓ

ꢉ

ꢀ

ꢊ

ꢍ

ꢎ

ꢏ

ꢅ

ꢑ

ꢓ

ꢘ

ꢗꢕ

ꢀ

ꢙ

ꢚ

ꢆ

ꢇ

ꢆ

ꢀ

SCBS746B − JULY 2000 - REVISED OCTOBER 2003

description/ordering information (continued)

When V

is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.

CC

However, to ensure the high-impedance state above 1.5 V, OE should be tied to GND through a pulldown

resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry

off

disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

FUNCTION TABLE

(each buffer)

INPUTS

OUTPUT

Y

OE

A

H

L

H

L

H

L

X

Z

logic diagram (positive logic)

1

10

1OE

3OE

3A

2

3

9

8

1A

1Y

2Y

3Y

4Y

4

13

12

2OE

4OE

4A

5

6

11

2A

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢊ

ꢋ

ꢀ

ꢁ

ꢌ

ꢃ

ꢍ ꢎꢍ ꢏꢅ ꢐꢑꢆ ꢒ ꢓꢐꢔꢕ ꢓꢖꢄ ꢗ ꢑꢓꢀ ꢑ ꢓꢘ ꢘꢗ ꢕ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢊ

ꢀ

ꢙ ꢚꢆ ꢇ ꢍ ꢏꢀꢆꢐꢆ ꢗ ꢛ ꢓꢆ ꢖ ꢓꢆ

SCBS746B − JULY 2000 - REVISED OCTOBER 2003

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V

CC

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

Voltage range applied to any output in the high-impedance

or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

O

Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

O

CC

Current into any output in the low state, I : SN54LVTH126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA

O

SN74LVTH126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA

Current into any output in the high state, I (see Note 2): SN54LVTH126 . . . . . . . . . . . . . . . . . . . . . . . . 48 mA

O

SN74LVTH126 . . . . . . . . . . . . . . . . . . . . . . . . 64 mA

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

IK

OK

I

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

O

Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W

JA

DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W

DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. This current flows only when the output is in the high state and V > V

.

CC

O

3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 4)

SN54LVTH126 SN74LVTH126

UNIT

MIN

2.7

2

MAX

MIN

2.7

2

MAX

V

Supply voltage

3.6

V

CC

High-level input voltage

Low-level input voltage

Input voltage

IH

0.8

5.5

−24

48

0.8

5.5

−32

64

V

IL

V

I

High-level output current

Low-level output current

Input transition rise or fall rate

Power-up ramp rate

mA

ns/V

µs/V

°C

OH

OL

I

∆t/∆v

∆t/∆V

Outputs enabled

10

200

−55

200

−40

CC

T

A

Operating free-air temperature

125

85

NOTE 4: All unused control inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

CC

ꢖ

ꢕ

ꢛ

ꢔ

ꢓ

ꢨ

ꢆ

ꢖ

ꢕ

ꢗ

ꢅ

ꢚ

ꢗ

ꢙ

ꢞ

ꢦ

ꢩ

ꢡ

ꢪ

ꢤ

ꢧ

ꢜ

ꢞ

ꢡ

ꢦ

ꢢ

ꢡ

ꢦ

ꢢ

ꢥ

ꢪ

ꢦ

ꢟ

ꢫ

ꢪ

ꢡ

ꢠ

ꢣ

ꢠꢥ ꢟ ꢞ ꢱꢦ ꢫꢝ ꢧ ꢟ ꢥ ꢡꢩ ꢠꢥ ꢲ ꢥ ꢭꢡ ꢫꢤꢥ ꢦꢜꢎ ꢨ ꢝꢧ ꢪꢧ ꢢꢜ ꢥꢪ ꢞꢟ ꢜꢞ ꢢ ꢠꢧ ꢜꢧ ꢧꢦ ꢠ ꢡꢜ ꢝꢥꢪ

ꢢ

ꢜ

ꢟ

ꢞ

ꢦ

ꢜ

ꢝ

ꢥ

ꢩ

ꢡ

ꢪ

ꢤ

ꢧ

ꢜ

ꢞ

ꢲ

ꢥ

ꢡ

ꢪ

ꢟ

ꢫ

ꢥ

ꢢ

ꢞ

ꢩ

ꢞ

ꢢ

ꢧ

ꢜ

ꢞ

ꢡ

ꢦ

ꢟ

ꢧ

ꢪ

ꢥ

ꢠ

ꢥ

ꢟ

ꢞ

ꢱ

ꢦ

ꢱ

ꢡ

ꢧ

ꢭ

ꢟ

ꢎ

ꢆ

ꢥ

ꢮ

ꢧ

ꢟ

ꢚ

ꢦ

ꢟ

ꢜ

ꢪ

ꢣ

ꢤ

ꢥ

ꢦ

ꢢ ꢝꢧ ꢦ ꢱꢥ ꢡꢪ ꢠꢞ ꢟ ꢢ ꢡꢦ ꢜꢞ ꢦꢣꢥ ꢜ ꢝꢥ ꢟ ꢥ ꢫꢪ ꢡꢠ ꢣꢢꢜ ꢟ ꢯ ꢞꢜꢝ ꢡꢣꢜ ꢦꢡꢜ ꢞꢢꢥ ꢎ

ꢜ

ꢟ

ꢪ

ꢥ

ꢟ

ꢥ

ꢪ

ꢲ

ꢥ

ꢟ

ꢜ

ꢝ

ꢥ

ꢪ

ꢞ

ꢱ

ꢝ

ꢜ

ꢡ

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢍ

ꢂ

ꢃ

ꢄ

ꢐ

ꢍ

ꢅ

ꢑ

ꢏ

ꢆ

ꢀ

ꢇ

ꢒ

ꢆꢐ

ꢈ

ꢉ

ꢓ

ꢊ

ꢐ

ꢗ

ꢋ

ꢀ

ꢔ

ꢛ

ꢁ

ꢕ

ꢓ

ꢌ

ꢓ

ꢆ

ꢃ

ꢖ

ꢄ

ꢓ

ꢅ

ꢗ

ꢆ

ꢇ

ꢑ

ꢈ

ꢓ

ꢉ

ꢀ

ꢊ

ꢍ

ꢎ

ꢏ

ꢅ

ꢑ

ꢓ

ꢘꢘ

ꢗꢕ

ꢀ

ꢙ

ꢚ

ꢆ

ꢇ

ꢆ

ꢀ

SCBS746B − JULY 2000 - REVISED OCTOBER 2003

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LVTH126

SN74LVTH126

PARAMETER

TEST CONDITIONS

I = −18 mA

UNIT

†

MIN TYP

MAX

MIN TYP

MAX

V

= 2.7 V,

−1.2

V

IK

CC

I

= 2.7 V to 3.6 V,

= 2.7 V,

I

= −100 µA

= −8 mA

= −24 mA

= −32 mA

= 100 µA

= 24 mA

= 16 mA

= 32 mA

= 48 mA

= 64 mA

V

−0.2

CC

2.4

V

−0.2

CC

2.4

OH

OL

V

OH

2

V

= 3 V

CC

2

0.2

0.5

0.2

0.5

0.4

0.5

V

= 2.7 V

0.4

V

OL

0.5

V

CC

= 3 V

0.55

10

1

V

= 0 or 3.6 V,

= 3.6 V,

V = 5.5 V

10

1

CC

I

Control inputs

Data inputs

V = V

or GND

CC

I

CC

I

µA

V = V

1

I

CC

V

= 3.6 V

= 0,

CC

V = 0

I

−5

100

I

V or V = 0 to 4.5 V

µA

off

CC

I

O

V = 0.8 V

I

75

V

CC

= 3 V

V = 2 V

I

−75

Data inputs

I(hold)

‡

V

= 3.6 V ,

V = 0 to 3.6 V

500

5

CC

I

= 3.6 V,

V

O

V

O

= 3 V

5

µA

OZH

= 0.5 V

−5

OZL

= 0 to 1.5 V, V = 0.5 V to 3 V,

OE = don’t care

O

∗

50

µA

I

OZPU

OZPD

V

= 1.5 V to 0, V = 0.5 V to 3 V,

CC

OE = don’t care

O

∗

I

Outputs high

Outputs low

0.12

4.5

0.19

7

0.12

4.5

0.19

7

V

I

= 3.6 V,

CC

= 0,

I

mA

O

CC

V = V

I

or GND

CC

Outputs disabled

0.12

0.19

0.12

0.19

V

= 3 V to 3.6 V, One input at V − 0.6 V,

CC

Other inputs at V

§

0.3

0.2

∆I

CC

or GND

CC

C

V = 3 V or 0

4

pF

i

I

V

O

= 3 V or 0

6.5

o

∗

†

‡

§

On products compliant to MIL-PRF-38535, this parameter is not production tested.

All typical values are at V = 3.3 V, T = 25°C.

CC

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V or GND.

A

CC

ꢖ

ꢕ

ꢛ

ꢔ

ꢓ

ꢨ

ꢆ

ꢖ

ꢕ

ꢗ

ꢅ

ꢚ

ꢗ

ꢙ

ꢞ

ꢦ

ꢩ

ꢡ

ꢪ

ꢤ

ꢧ

ꢜ

ꢞ

ꢡ

ꢦ

ꢢ

ꢡ

ꢦ

ꢢ

ꢥ

ꢪ

ꢦ

ꢟ

ꢫ

ꢪ

ꢡ

ꢠ

ꢣ

ꢢ

ꢠ ꢥ ꢟ ꢞ ꢱ ꢦ ꢫꢝ ꢧ ꢟ ꢥ ꢡꢩ ꢠꢥ ꢲ ꢥ ꢭ ꢡꢫ ꢤꢥ ꢦ ꢜꢎ ꢨ ꢝꢧ ꢪꢧ ꢢꢜ ꢥꢪ ꢞꢟ ꢜꢞ ꢢ ꢠꢧ ꢜꢧ ꢧꢦ ꢠ ꢡꢜ ꢝꢥꢪ

ꢜ

ꢟ

ꢞ

ꢦ

ꢜ

ꢝ

ꢥ

ꢩ

ꢡ

ꢪ

ꢤ

ꢧ

ꢜ

ꢞ

ꢲ

ꢥ

ꢡ

ꢪ

ꢟ

ꢫ

ꢥ

ꢢ

ꢞ

ꢩ

ꢞ

ꢢ

ꢧ

ꢜ

ꢞ

ꢡ

ꢦ

ꢟ

ꢧ

ꢪ

ꢥ

ꢠ

ꢥ

ꢟ

ꢞ

ꢱ

ꢦ

ꢱ

ꢡ

ꢧ

ꢭ

ꢟ

ꢎ

ꢆ

ꢥ

ꢮ

ꢧ

ꢟ

ꢚ

ꢦ

ꢟ

ꢜ

ꢪ

ꢣ

ꢤ

ꢥ

ꢦ

ꢢ ꢝ ꢧ ꢦ ꢱꢥ ꢡꢪ ꢠꢞ ꢟ ꢢ ꢡꢦ ꢜꢞ ꢦꢣ ꢥ ꢜ ꢝꢥ ꢟ ꢥ ꢫꢪ ꢡ ꢠꢣꢢ ꢜꢟ ꢯ ꢞꢜꢝ ꢡꢣꢜ ꢦꢡꢜ ꢞꢢꢥ ꢎ

ꢜ

ꢟ

ꢪ

ꢥ

ꢟ

ꢥ

ꢪ

ꢲ

ꢥ

ꢟ

ꢜ

ꢝ

ꢥ

ꢪ

ꢞ

ꢱ

ꢝ

ꢜ

ꢡ

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢊ

ꢋ

ꢀ

ꢁ

ꢌ

ꢃ

ꢍ ꢎꢍ ꢏꢅ ꢐꢑꢆ ꢒ ꢓꢐꢔꢕ ꢓꢖꢄ ꢗ ꢑꢓꢀ ꢑ ꢓꢘ ꢘꢗ ꢕ

ꢄ

ꢅ

ꢆ

ꢇ

ꢈ

ꢉ

ꢊ

ꢀ

ꢙ ꢚꢆ ꢇ ꢍ ꢏꢀꢆꢐꢆ ꢗ ꢛ ꢓꢆ ꢖ ꢓꢆ

SCBS746B − JULY 2000 - REVISED OCTOBER 2003

switching characteristics over recommended operating free-air temperature range, C = 50 pF

L

(unless otherwise noted) (see Figure 1)

SN54LVTH126

= 3.3 V

SN74LVTH126

V

CC

V

CC

= 3.3 V

V

FROM

(INPUT)

TO

(OUTPUT)

V

= 2.7 V

PARAMETER

UNIT

CC

0.3 V

†

MIN

MAX

4.8

4.9

6.4

6.2

4.8

6.5

MIN

MAX

5.5

5.4

7.1

6.8

5.3

7.1

MIN TYP

MAX

3.8

3.9

5.4

5.2

3.8

5.5

MIN

MAX

4.5

4.4

6.1

5.8

4.3

6.1

t

1

2.3

2.4

3.6

2.2

3.6

PLH

PHL

PZH

PZL

PHZ

PLZ

A

Y

ns

1

OE

1.1

1

1.1

1

1.3

†

All typical values are at V

CC

= 3.3 V, T = 25°C.

A

ꢖ

ꢕ

ꢛ

ꢔ

ꢓ

ꢨ

ꢆ

ꢖ

ꢕ

ꢗ

ꢅ

ꢚ

ꢗ

ꢙ

ꢞ

ꢦ

ꢩ

ꢡ

ꢪ

ꢤ

ꢧ

ꢜ

ꢞ

ꢡ

ꢦ

ꢢ

ꢡ

ꢦ

ꢢ

ꢥ

ꢪ

ꢦ

ꢟ

ꢫ

ꢪ

ꢡ

ꢠ

ꢣ

ꢠꢥ ꢟ ꢞ ꢱꢦ ꢫꢝ ꢧ ꢟ ꢥ ꢡꢩ ꢠꢥ ꢲ ꢥ ꢭꢡ ꢫꢤꢥ ꢦꢜꢎ ꢨ ꢝꢧ ꢪꢧ ꢢꢜ ꢥꢪ ꢞꢟ ꢜꢞ ꢢ ꢠꢧ ꢜꢧ ꢧꢦ ꢠ ꢡꢜ ꢝꢥꢪ

ꢢ

ꢜ

ꢟ

ꢞ

ꢦ

ꢜ

ꢝ

ꢥ

ꢩ

ꢡ

ꢪ

ꢤ

ꢧ

ꢜ

ꢞ

ꢲ

ꢥ

ꢡ

ꢪ

ꢟ

ꢫ

ꢥ

ꢢ

ꢞ

ꢩ

ꢞ

ꢢ

ꢧ

ꢜ

ꢞ

ꢡ

ꢦ

ꢟ

ꢧ

ꢪ

ꢥ

ꢠ

ꢥ

ꢟ

ꢞ

ꢱ

ꢦ

ꢱ

ꢡ

ꢧ

ꢭ

ꢟ

ꢎ

ꢆ

ꢥ

ꢮ

ꢧ

ꢟ

ꢚ

ꢦ

ꢟ

ꢜ

ꢪ

ꢣ

ꢤ

ꢥ

ꢦ

ꢢ ꢝꢧ ꢦ ꢱꢥ ꢡꢪ ꢠꢞ ꢟ ꢢ ꢡꢦ ꢜꢞ ꢦꢣꢥ ꢜ ꢝꢥ ꢟ ꢥ ꢫꢪ ꢡꢠ ꢣꢢꢜ ꢟ ꢯ ꢞꢜꢝ ꢡꢣꢜ ꢦꢡꢜ ꢞꢢꢥ ꢎ

ꢜ

ꢟ

ꢪ

ꢥ

ꢟ

ꢥ

ꢪ

ꢲ

ꢥ

ꢟ

ꢜ

ꢝ

ꢥ

ꢪ

ꢞ

ꢱ

ꢝ

ꢜ

ꢡ

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ

ꢁ

ꢍ

ꢂ

ꢃ

ꢄ

ꢐ

ꢍ

ꢅ

ꢑ

ꢏ

ꢆ

ꢀ

ꢇ

ꢒ

ꢆꢐ

ꢈ

ꢉ

ꢓ

ꢊ

ꢐ

ꢗ

ꢋ

ꢀ

ꢔ

ꢛ

ꢁ

ꢕ

ꢓ

ꢌ

ꢓ

ꢆ

ꢃ

ꢖ

ꢄ

ꢓ

ꢅ

ꢗ

ꢆ

ꢇ

ꢑ

ꢈ

ꢓ

ꢉ

ꢀ

ꢊ

ꢍ

ꢎ

ꢏ

ꢅ

ꢑ

ꢓ

ꢘꢘ

ꢗꢕ

ꢀ

ꢙ

ꢚ

ꢆ

ꢇ

ꢆ

ꢀ

SCBS746B − JULY 2000 - REVISED OCTOBER 2003

PARAMETER MEASUREMENT INFORMATION

6 V

TEST

S1

Open

GND

500 Ω

From Output

Under Test

t

/t

PLH PHL

Open

6 V

t

/t

PLZ PZL

C

= 50 pF

t

/t

GND

L

PHZ PZH

500 Ω

(see Note A)

2.7 V

0 V

LOAD CIRCUIT

Timing Input

Data Input

1.5 V

t

w

t

h

su

2.7 V

0 V

2.7 V

0 V

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

2.7 V

0 V

2.7 V

0 V

Output

Control

1.5 V

Input

t

PLZ

PZL

t

PHL

PLH

PHL

Output

Waveform 1

S1 at 6 V

3 V

V

OH

1.5 V

t

Output

V

+ 0.3 V

OL

V

OL

(see Note B)

t

PZH

PHZ

PLH

Output

Waveform 2

S1 at GND

V

OH

V

OH

− 0.3 V

OH

1.5 V

Output

≈0 V

OL

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A. includes probe and jig capacitance.

C

L

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.

O

r

f

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2008

PACKAGING INFORMATION

Orderable Device

SN74LVTH126D

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

14

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVTH126DBR

SN74LVTH126DBRE4

SN74LVTH126DBRG4

SN74LVTH126DE4

SN74LVTH126DG4

SN74LVTH126DGVR

SN74LVTH126DGVRE4

SN74LVTH126DGVRG4

SN74LVTH126DR

SSOP

SOIC

DB

D

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TVSOP

SOIC

DGV

D

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVTH126DRE4

SN74LVTH126DRG4

SN74LVTH126NSR

SN74LVTH126NSRE4

SN74LVTH126NSRG4

SN74LVTH126PW

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

NS

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LVTH126PWE4

SN74LVTH126PWG4

SN74LVTH126PWR

SN74LVTH126PWRE4

SN74LVTH126PWRG4

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2008

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74LVTH126DBR

SN74LVTH126DGVR

SN74LVTH126DR

SN74LVTH126NSR

SN74LVTH126PWR

SSOP

TVSOP

SOIC

DB

DGV

D

14

2000

2500

2000

330.0

16.4

12.4

16.4

12.4

8.2

6.8

6.5

8.2

6.9

6.6

4.0

2.5

1.6

2.1

2.5

1.6

12.0

8.0

16.0

12.0

16.0

12.0

Q1

9.0

8.0

SO

NS

10.5

5.6

12.0

8.0

TSSOP

PW

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74LVTH126DBR

SN74LVTH126DGVR

SN74LVTH126DR

SN74LVTH126NSR

SN74LVTH126PWR

SSOP

TVSOP

SOIC

DB

DGV

D

14

2000

2500

2000

367.0

38.0

35.0

38.0

35.0

SO

NS

TSSOP

PW

Pack Materials-Page 2

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

M

0,07

0,40

24

13

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

1

12

0,50

A

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

14

16

20

24

38

48

56

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All

semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time

of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which

have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such

components to meet such requirements.

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Medical

Logic

Security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense www.ti.com/space-avionics-defense

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SN74LVTH126PWRG4
厂家：	TEXAS INSTRUMENTS
描述：	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUT PC 驱动信息通信管理光电二极管输出元件逻辑集成电路
文件：	总18页 (文件大小：707K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74LVTH126PWRG4 [TI]

相关型号：

SN74LVTH162240

SN74LVTH162240-EP

SN74LVTH162240DGG

SN74LVTH162240DGGR

SN74LVTH162240DL

SN74LVTH162240DLR

SN74LVTH162241

SN74LVTH162241DGG

SN74LVTH162241DGGR

SN74LVTH162241DGVR

SN74LVTH162241DL

SN74LVTH162241DLG4