SN74SSTL16857DGG [TI]
14-BIT SSTL_2 REGISTERED BUFFER; 14位SSTL_2寄存缓冲器
| 型号： | SN74SSTL16857DGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14-BIT SSTL_2 REGISTERED BUFFER |
| 文件： | 总7页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74SSTL16857
14-BIT SSTL_2 REGISTERED BUFFER
SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999
DGG PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
Supports SSTL_2 Signal Data Inputs and
Outputs
Q1
Q2
GND
D1
D2
GND
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
Supports LVTTL Switching Levels on the
RESET Pin
V
V
DDQ
Q3
CC
Differential CLK Signal
D3
D4
D5
D6
D7
Q4
Q5
GND
Flow-Through Architecture Optimizes PCB
Layout
Meets SSTL_2 Class II Specifications
V
DDQ
Q6 10
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
39 CLK
Q7
CLK
11
12
38
37
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
V
V
DDQ
CC
GND 13
Q8 14
Q9 15
36 GND
35
V
REF
– 1000-V Charged-Device Model (C101)
34 RESET
Packaged in Plastic Thin Shrink
Small-Outline Package
V
16
33 D8
DDQ
GND 17
Q10 18
Q11 19
Q12 20
32 D9
31 D10
30 D11
29 D12
description
This 14-bit registered buffer is designed for 2.3-V
to 3.6-V V operation and SSTL_2 data input
V
21
28
V
DDQ
CC
CC
GND 22
Q13 23
Q14 24
27 GND
26 D13
25 D14
and output levels.
All inputs are compatible with the JEDEC
Standard for SSTL_2, except the LVCMOS reset
(RESET) input. All outputs are SSTL_2, Class II
compatible.
When RESET is low, the differential input receivers are disabled, and undriven (floating) data and clock inputs
are allowed. In addition, when RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS
RESET input must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
The SN74SSTL16857 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
RESET
CLK
CLK
D
X
H
L
L
H
H
H
X
X
L
H
L
↓
↓
↑
↑
L or H
L or H
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL16857
14-BIT SSTL_2 REGISTERED BUFFER
SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999
logic diagram (positive logic)
34
RESET
38
CLK
39
CLK
35
V
REF
48
D1
1D
C1
1
Q1
R
To 13 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
or V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
DDQ
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
DDQ
DDQ
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V , V
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
Storage temperature range, T
O
DDQ
CC DDQ
, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. Current flows only when the output is in the high state and V > V
.
DDQ
O
3. The package thermal impedance is calculated in accordance with JESD 51.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL16857
14-BIT SSTL_2 REGISTERED BUFFER
SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999
recommended operating conditions (see Note 4)
MIN
NOM
MAX
3.6
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Supply voltage
V
CC
DDQ
REF
TT
I
DDQ
2.3
Output supply voltage
2.7
V
Reference voltage (V
Termination voltage
Input voltage
= V
/2)
DDQ
1.15
1.25
1.35
V
REF
V
–40 mV
0
V
V
+40 mV
REF
V
REF
REF
V
CC
V
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Data inputs
Data inputs
Data inputs
Data inputs
RESET
V
+350 mV
+180 mV
2
V
IH
REF
V
REF
–350 mV
V
IL
V
V
IH
REF
V
REF
–180 mV
V
IL
V
IH
RESET
0.8
V
IL
Common-mode input voltage range
Peak-to-peak input voltage
High-level output current
CLK, CLK
CLK, CLK
0.97
360
1.53
V
ICR
I(PP)
mV
mA
mA
C
I
I
–20
20
OH
Low-level output current
OL
T
A
Operating free-air temperature
0
70
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL16857
14-BIT SSTL_2 REGISTERED BUFFER
SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
V
IK
I = –18 mA
I
2.3 V
–1.2
V
I
I
I
I
I
I
= –100 µA
= –8 mA
= –16 mA
= 100 µA
= 8 mA
2.3 V to 2.7 V
V
CC
–0.2
1.95
1.95
OH
OH
OH
OL
OL
OL
V
V
V
OH
2.3 V
2.3 V to 2.7 V
2.3 V
0.2
0.35
0.35
±5
V
OL
= 16 mA
V = 1.7 V or 0.8V
I
V
V
V
V
= 1.15 V or 1.35 V
= 1.15 V or 1.35 V
= 1.15 V or 1.35 V
= 1.15 V or 1.35 V
2.7 V
3.6 V
2.7 V
3.6 V
REF
REF
REF
REF
V = 2.7 V or 0
±5
I
Data inputs
µA
mA
µA
mA
pF
V = 1.7 V or 0.8V
I
±5
V = 2.7 V or 0
I
±5
V = 1.7 V or 0.8V
I
±1
V = 2.7 V or 0
I
±1
I
I
CLK, CLK
RESET
V = 1.7 V or 0.8V
I
±1
V = 2.7 V or 0
I
±1
2.7 V
3.6 V
2.7 V
3.6 V
±5
V = V
I
or GND
CC
±5
±5
V
REF
V
REF
= 1.15 V or 1.35 V
±5
V = 1.7 V or 0.8 V
I
90
I
I
= 0
= 0
2.7 V
3.6 V
O
V = 2.7 V or 0
I
90
I
CC
V = 1.7 V or 0.8 V
I
90
O
V = 2.7 V or 0
I
90
RESET
3
2.5
3
†
V = 1.7 V or 0.8 V
I
2.5 V
Data inputs
RESET
C
i
‡
V = 1.7 V or 0.8 V
I
3.3 V
Data inputs
2.5
†
‡
All typical values are at V
All typical values are at V
= 2.5 V, T = 25°C.
A
CC
CC
= 3.3 V, T = 25°C.
A
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V = 2.5 V
CC
± 0.2 V
V = 3.3 V
CC
± 0.3 V
UNIT
MIN
MAX
MIN
MAX
f
t
Clock frequency
150
150
MHz
ns
clock
Pulse duration, CLK, CLK high or low
3.3
1.1
0.6
0.7
3.3
1.75
1.1
w
Data before CLK↑, CLK↓
t
Setup time
ns
ns
su
h
RESET high before CLK↑, CLK↓
t
Hold time, data after CLK↑, CLK↓
0.7
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL16857
14-BIT SSTL_2 REGISTERED BUFFER
SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
150
1.5
MAX
MIN
150
1.4
MAX
f
t
t
MHz
ns
max
CLK and CLK
RESET
Q
Q
3.8
4.3
3.7
3.5
pd
1.5
1.4
ns
PHL
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL16857
14-BIT SSTL_2 REGISTERED BUFFER
SCAS625C – FEBRUARY 1999 – REVISED OCTOBER 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V AND V
= 3.3 V ± 0.3 V
CC
CC
V
TT
Test
Point
25 Ω
25 Ω
C = 30 pF
L
(see Note A)
LOAD CIRCUIT
‡
t
w
V
V
IH
‡
Timing
Input
V
V
IH
†
V
REF
†
†
§
V
REF
V
REF
Input
IL
§
t
t
IL
su
h
‡
VOLTAGE WAVEFORMS
PULSE DURATION
V
V
IH
Data
Input
†
†
V
REF
V
REF
§
IL
‡
V
V
IH
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
†
†
V
REF
V
REF
§
IL
t
t
PLZ
PZL
‡
V
V
IH
Output
Waveform 1
(see Note B)
V
V
TT
†
†
V
REF
Input
V
REF
§
V
IL
§
V
IL
§
IL
OL
t
t
t
t
PHZ
PLH
PHL
PZH
V
V
V
†
Output
Waveform 2
(see Note B)
OH
OH
‡
‡
V
IH
†
Output
V
IH
V
REF
V
REF
V
OL
TT
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
†
‡
§
V
V
V
= V /2
REF
IH
IL
DDQ
= V
+ 350 mV (AC voltage levels)
– 350 mV (AC voltage levels)
REF
= V
REF
NOTES: A.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 1.25 ns/V,
C includes probe and jig capacitance.
L
O
r
t ≤ 1.25 ns/V.
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
H.
V
= V
and t
and t
= V
/2
TT
REF
DDQ
t
t
t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
.
and t
PHL
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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