SN74SSTU32864CGKER [TI]
25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL 18 INPUTS AND OUTPUTS; 25位可配置寄存缓冲器与SSTL 18的输入和输出
| 型号： | SN74SSTU32864CGKER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL 18 INPUTS AND OUTPUTS |
| 文件： | 总18页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
FEATURES
•
Differential Clock (CLK and CLK) Inputs
•
Member of the Texas Instruments Widebus+™
Family
•
Supports LVCMOS Switching Levels on
Control and RESET Inputs
•
•
Pinout Optimizes DDR2 DIMM PCB Layout
•
RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces
All Outputs Low
Configurable as 25-Bit 1:1 or 14-Bit 1:2
Registered Buffer
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
Chip-Select Inputs Gate Data Outputs From
Changing State and Minimize System Power
Consumption
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
•
•
Output Edge-Control Circuitry Minimizes
Switching Noise in Unterminated Line
Supports SSTL_18 Data Inputs
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1
pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout
configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are
edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.
The SN74SSTU32864C operates from a differential clock (CLK and CLK). Data are registered at the crossing of
CLK going high and CLK going low.
The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to
register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to
14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to
a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the
A6, D6, and H6 terminals are driven low and should not be used.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and
CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is
cleared and the data outputs are driven low quickly, relative to the time to disable the differential input receivers.
However, when coming out of reset, the register becomes active quickly, relative to the time required to enable
the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the
low-to-high transition of RESET until the input receivers are fully enabled, the design of the SN74SSTU32864C
must ensure that the outputs remain low, thus ensuring no glitches on the output.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the
low state during power up.
ORDERING INFORMATION
TA
PACKAGE(1)
Tape and reel
Tape and reel
ORDERABLE PART NUMBER
SN74SSTU32864CGKER
SN74SSTU32864CZKER
TOP-SIDE MARKING
S864C
LFBGA – GKE
LFBGA – ZKE
0°C to 70°C
S864C
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET and Cn inputs always
must be held at a valid logic high or logic low level.
The device also supports low-power active operation by monitoring both system chip select (DCS and CSR)
inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS
or CSR input is low, the Qn outputs function normally. The RESET input has priority over the DCS and CSR
control and forces the output low. If the DCS control functionality is not desired, the CSR input can be hard-wired
to ground, in which case the setup-time requirement for DCS is the same as for the other D data inputs.
The two VREF pins (A3 and T3) are connected together internally by approximately 150 Ω. However, it is
necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin
should be terminated with a VREF coupling capacitor.
2
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TERMINAL ASSIGNMENTS FOR 1:1 REGISTER (C0 = 0, C1 = 0)(1)(2)(3)
1
D1 (DCKE)
D2
2
NC
3
4
5
Q1 (QCKE)
Q2
6
A
VREF
GND
VCC
VCC
DNU
Q15
Q16
DNU
Q17
Q18
C0
B
C
D
E
F
D15
GND
VCC
D3
D16
Q3
D4 (DODT)
D5
NC
GND
VCC
GND
VCC
Q4 (QODT)
Q5
D17
D6
D18
GND
VCC
GND
VCC
Q6
G
H
J
NC
RESET
D7 (DCS)
CSR
D19
C1
CLK
CLK
D8
GND
VCC
GND
VCC
Q7 (QCS)
NC
DNU
NC
K
L
GND
VCC
GND
VCC
Q8
Q19
Q20
Q21
Q22
Q23
Q24
Q25
D9
D20
Q9
M
N
P
R
T
D10
D21
GND
VCC
GND
VCC
Q10
D11
D22
Q11
D12
D23
GND
VCC
GND
VCC
Q12
D13
D24
Q13
D14
D25
VREF
VCC
Q14
(1) Each pin name in parentheses indicates the DDR2 DIMM signal name.
(2) NC - No internal connection
(3) DNU - Do not use
3
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
LOGIC DIAGRAM FOR 1:1 REGISTER CONFIGURATION (POSITIVE LOGIC)
G2
RESET
H1
J1
CLK
CLK
A3, T3
A1
V
REF
D1 (DCKE)
D4 (DODT)
D7 (DCS)
CSR
D
R
A5
D5
Q1 (QCKE)
Q4 (QODT)
CLK
CLK
CLK
Q
Q
Q
D1
H2
J2
D
R
D
R
H5
Q7 (QCS)
One of 22 Channels
B1
D2
CE
D
R
B5
Q2
CLK
Q
To 21 Other Channels (D3, D5, D6, D8−D25)
4
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TERMINAL ASSIGNMENTS FOR 1:2 REGISTER A (C0 = 0, C1 = 1)(1)(2)(3)
1
D1 (DCKE)
D2
2
NC
3
4
5
Q1A (QCKEA)
Q2A
6
Q1B (QCKEB)
Q2B
A
VREF
GND
VCC
VCC
B
C
D
E
F
DNU
DNU
NC
GND
VCC
D3
Q3A
Q3B
D4 (DODT)
D5
GND
VCC
GND
VCC
Q4A (QODTA)
Q5A
Q4B (QODTB)
Q5B
DNU
DNU
RESET
D7 (DCS)
CSR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
D6
GND
VCC
GND
VCC
Q6A
Q6B
G
H
J
NC
C1
C0
CLK
CLK
D8
GND
VCC
GND
VCC
Q7A (QCSA)
NC
Q7B (QCSB)
NC
K
L
GND
VCC
GND
VCC
Q8A
Q8B
D9
Q9A
Q9B
M
N
P
R
T
D10
GND
VCC
GND
VCC
Q10A
Q10B
D11
Q11A
Q11B
D12
GND
VCC
GND
VCC
Q12A
Q12B
D13
Q13A
Q13B
D14
VREF
VCC
Q14A
Q14B
(1) Each pin name in parentheses indicates the DDR2 DIMM signal name.
(2) NC - No internal connection
(3) DNU - Do not use
5
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
LOGIC DIAGRAM 1:2 REGISTER-A CONFIGURATION (POSITIVE LOGIC)
G2
RESET
H1
J1
CLK
CLK
A3, T3
A1
V
REF
D1 (DCKE)
D4 (DODT)
D7 (DCS)
CSR
A5
A6
Q1A (QCKEA)
Q1B (QCKEB)
D
R
CLK
CLK
CLK
Q
Q
Q
D1
H2
J2
D5
D6
Q4A (QODTA)
Q4B (QODTB)
D
R
H5
H6
Q7A (QCSA)
Q7B (QCSB)
D
R
One of Eleven Channels
B1
D2
B5
B6
CE
Q2A
Q2B
D
R
CLK
Q
To 10 Other Channels (D3, D5, D6, D8−D14)
6
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TERMINAL ASSIGNMENTS FOR 1:2 REGISTER B (C0 = 1, C1 = 1)(1)(2)(3)
1
2
NC
3
4
5
Q1A
6
Q1B
A
D1
VREF
GND
VCC
VCC
B
C
D
E
F
D2
D3
DNU
DNU
NC
GND
VCC
Q2A
Q2B
Q3A
Q3B
D4
GND
VCC
GND
VCC
Q4A
Q4B
D5
DNU
DNU
RESET
D7 (DCS)
CSR
DNU
DNU
DNU
DNU
DNU
DNU
DNU
Q5A
Q5B
D6
GND
VCC
GND
VCC
Q6A
Q6B
G
H
J
NC
C1
C0
CLK
GND
VCC
GND
VCC
Q7A (QCSA)
NC
Q7B (QCSB)
NC
CLK
K
L
D8
GND
VCC
GND
VCC
Q8A
Q8B
D9
Q9A
Q9B
M
N
P
R
T
D10
GND
VCC
GND
VCC
Q10A
Q10B
D11 (DODT)
D12
Q11A (QODTA)
Q12A
Q11B (QODTB)
Q12B
GND
VCC
GND
VCC
D13
Q13A
Q13B
D14 (DCKE)
VREF
VCC
Q14A (QCKEA)
Q14B (QCKEB)
(1) Each pin name in parentheses indicates the DDR2 DIMM signal name.
(2) NC - No internal connection
(3) DNU - Do not use
7
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
LOGIC DIAGRAM 1:2 REGISTER-B CONFIGURATION (POSITIVE LOGIC)
G2
RESET
H1
J1
CLK
CLK
A3, T3
T1
V
REF
D14 (DCKE)
D11 (DODT)
D7 (DCS)
CSR
T5
T6
Q14A (QCKEA)
Q14B (QCKEB)
D
R
CLK
CLK
CLK
Q
Q
Q
N1
H2
J2
N5
N6
Q11A (QODTA)
Q11B (QODTB)
D
R
H5
H6
Q7A (QCSA)
Q7B (QCSB)
D
R
One of Eleven Channels
A1
D1
A5
A6
CE
Q1A
Q1B
D
R
CLK
Q
To 10 Other Channels (D2−D6, D8−D10, D12−D13)
8
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
TERMINAL FUNCTIONS
TERMINAL
NAME
ELECTRICAL
CHARACTERISTICS
DESCRIPTION
GND
VCC
Ground
Ground input
Power-supply voltage
Input reference voltage
Positive master clock input
Negative master clock input
1.8 V nominal
0.9 V nominal
Differential input
Differential input
LVCMOS inputs
VREF
CLK
CLK
C0, C1
Configuration control inputs – Register A, Register B, 1:1, 1:2 select
Asynchronous reset input – resets registers and disables VREF data and clock
differential-input receivers. When RESET is low, all Q outputs are forced low.
RESET
LVCMOS input
SSTL_18 inputs
Data inputs – clocked in on the crossing of the rising edge of CLK and the falling edge of
CLK
D1–D25
CSR, DCS
DODT
DCKE
Q1–Q25(2)
QCS
Chip select inputs – disables register clocking(1) when both inputs are high
The outputs of this register bit will not be suspended by the DCS and CSR control.
The outputs of this register bit will not be suspended by the DCS and CSR control.
Data outputs that are suspended by the DCS and CSR control
Data output that will not be suspended by the DCS and CSR control
Data output that will not be suspended by the DCS and CSR control
Data output that will not be suspended by the DCS and CSR control
No internal connection
SSTL_18 inputs
SSTL_18 input
SSTL_18 input
1.8-V CMOS outputs
1.8-V CMOS output
1.8-V CMOS output
1.8-V CMOS output
QODT
QCKE
NC
DNU
Do not use – inputs are in standby-equivalent mode, and outputs are driven low.
(1) Data inputs = D2, D3, D5, D6, D8–D25 when C0 = 0 and C1 = 0
Data inputs = D2, D3 D5, D6, D8-D14 when C0 = 0 and C1 = 1
Data inputs = D1–D6, D8–D12, D13 when C0 = 1 and C1 = 1
(2) Data outputs = Q2, Q3, Q5, Q6, Q8–when C0 = 0 and C1 = 0
Data outputs = Q2, Q3 Q5, Q6, Q8–Q14 when C0 = 0 and C1 = 1
Data outputs = Q1–Q6, Q8–Q10, Q12, Q13 when C0 = 1 and C1 = 1
FUNCTION TABLES
INPUTS
OUTPUT
Qn
RESET
DCS
L
CSR
X
CLK
CLK
Dn
L
H
H
H
H
H
H
L
↑
↓
L
H
L
X
↑
↓
H
L
X
L
↑
↓
L
X
L
↑
↑
↓
↓
H
X
H
H
H
Q0
Q0
L
X
X
L or H
L or H
X
X or floating X or floating X or floating X or floating X or floating
INPUTS
OUTPUTS
DCKE,
DCS,
QCKE,
QCS,
RESET
CLK
CLK
DODT
QODT
H
H
H
L
↑
↑
↓
↓
H
L
H
L
L or H
L or H
X
Q0
L
X or floating X or floating X or floating
9
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
2.5
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)(3)
Output voltage range(2)(3)
V
2.5
VCC + 0.5
±50
V
V
VO
IIK
Input clamp current
VI < 0 or VI > VCC
VO < 0 or VO > VCC
VO = 0 to VCC
mA
mA
mA
mA
°C/W
°C
IOK
IO
Output clamp current
±50
Continuous output current
Continuous current through each VCC or GND
Package thermal impedance(4)
Storage temperature range
±50
±100
36
θJA
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 2.5 V maximum.
(4) The package thermal impendance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
NOM
MAX
1.9
UNIT
V
VCC
VREF
VI
Supply voltage
1.7
0.49 × VCC
0
Reference voltage
0.5 × VCC
0.51 × VCC
VCC
V
Input voltage
V
VIH
VIL
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Common-mode input voltage range
Peak-to-peak input voltage
High-level output current
Low-level output current
Operating free-air temperature
Data inputs, CSR
Data inputs, CSR
Data inputs, CSR
Data inputs, CSR
RESET, Cn
VREF + 250 mV
V
VREF – 250 mV
VREF – 125 mV
V
VIH
VIL
VREF + 125 mV
V
V
VIH
VIL
0.65 × VCC
V
RESET, Cn
0.35 × VCC
V
VICR
VI(PP)
IOH
IOL
CLK, CLK
0.675
600
1.125
V
CLK, CLK
mV
mA
mA
°C
–8
8
TA
0
70
(1) The RESET and Cn inputs of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The
differential inputs must not be floating, unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS
Inputs, literature number SCBA004.
10
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.7 V to 1.9 V
1.7 V
MIN TYP(1)
VCC – 0.2
MAX
UNIT
IOH = –100 µA
IOH = –6 mA
IOL = 100 µA
IOL = 6 mA
VOH
V
1.3
1.7 V to 1.9 V
1.7 V
0.2
0.4
±5
VOL
II
V
All inputs(2)
VI = VCC or GND
1.9 V
µA
µA
Static standby
Static operating
RESET = GND
100
40
ICC
IO = 0
1.9 V
RESET = VCC, VI = VIH(AC) or VIL(AC)
mA
Dynamic operating – RESET = VCC, VI = VIH(AC) or VIL(AC)
,
33
19
µA/MHz
clock only
CLK and CLK switching 50% duty cycle
Dynamic operating –
per each data input,
1:1 configuration
RESET = VCC, VI = VIH(AC) or VIL(AC)
,
µA/
clock
MHz/
D input
ICCD
IO = 0
1.8 V
CLK and CLK switching 50% duty cycle,
One data input switching at one-half
clock frequency, 50% duty cycle
Dynamic operating –
per each data input,
1:2 configuration
35
34
Chip-select-enabled
low-power active
mode, clock only
RESET = VCC, VI = VIH(AC) or VIL(AC)
CLK and CLK switching 50% duty cycle
,
µA/MHz
Chip-select-enabled
low-power active
mode, 1:1
2
ICCDLP
IO = 0
1.8 V
RESET = VCC, VI = VIH(AC) or VIL(AC)
,
µA/
clock
MHz/
D input
configuration
CLK and CLK switching 50% duty cycle,
One data input switching at one-half
clock frequency, 50% duty cycle
Chip-select-enabled
low-power active
mode, 1:2
2
3
configuration
Data inputs, CSR
CLK, CLK
VI = VREF ± 250 mV
2.5
2
3.5
3
Ci
VICR = 0.9 V, VI(PP) = 600 mV
VI = VCC or GND
1.8 V
pF
RESET
2.5
(1) All typical values are at VCC = 1.8 V, TA = 25°C.
(2) Each VREF pin (A3 or T3) should be tested independently, with the other (untested) pin open.
Timing Requirements(1)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
MIN
MAX UNIT
500 MHz
ns
fclock
tw
Clock frequency
Pulse duration, CLK, CLK high or low
Differential inputs active time(2)
Differential inputs inactive time(3)
1
tact
10
15
ns
ns
tinact
DCS before CLK↑, CLK↓, CSR high; CSR before CLK↑, CLK↓, DCS high
0.6
0.5
0.5
0.5
tsu
Setup time
Hold time
DCS before CLK↑, CLK↓, CSR low
ns
ns
DODT, DCKE, and Data before CLK↑, CLK↓
DCS, DODT, DCKE, and Data after CLK↑, CLK↓
th
(1) All input slew rates are 1 V/ns ±20%.
(2) VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max after RESET is taken high.
(3) VREF data and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max after RESET is taken low.
11
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.1 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
500
1.4
MAX
fmax
MHz
ns
(1)
tpdm
CLK and CLK
CLK and CLK
RESET
Q
Q
Q
2.4
2.6
3
(1)
tpdmss
ns
(1)
tRPHL
ns
(1) Includes 350-ps test-load transmission-line delay
Output Slew Rates
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
VCC = 1.8 V
± 0.1 V
PARAMETER
FROM
TO
UNIT
MIN
1.9
MAX
4.9
dV/dt_r
dV/dt_f
dV/dt_∆(1)
20%
80%
80%
20%
V/ns
V/ns
V/ns
1.9
4.9
20% or 80%
80% or 20%
1.5
(1) Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
12
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Z
= 50 Ω,
= 350 ps
O
Test
Point
DUT
CLK
t
D
R
L
= 1 kΩ
Output
Test Point
Out
Clock Inputs
R
L
= 100 Ω
C
= 30 pF
L
Z
t
= 50 Ω,
= 350 ps
O
CLK
R
L
= 1 kΩ
(see Note A)
Test
Point
D
Z
= 50 Ω,
= 350 ps
O
t
D
LOAD CIRCUIT
t
w
V
V
IH
V
V
V
Input
REF
REF
V
IL
CC
LVCMOS
RESET
Input
V
/2
V
/2
CC
CC
VOLTAGE WAVEFORMS
PULSE DURATION
0 V
V
I(PP)
t
t
act
inact
Timing
Inputs
V
ICR
ICR
I
I
(operating)
I
CC
CC
90%
(see
10%
Note B)
(standby)
CC
t
t
PLH
PHL
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
V
OH
OL
Output
V /2
CC
V /2
CC
V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
I(PP)
V
V
IH
Timing
Inputs
LVCMOS
RESET
Input
V
ICR
V /2
CC
IL
t
PHL
t
su
t
h
V
V
V
OH
IH
V
REF
Output
Input
V
REF
V /2
CC
V
OL
IL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A. C includes probe and jig capacitance.
L
B.
I tested with clock and data inputs held at V or GND, and I = 0 mA.
CC CC O
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω,
O
input slew rate = 1 V/ns ±20% (unless otherwise noted).
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
H.
I.
V
V
V
V
= V /2
CC
REF
= V
+ 250 mV (ac voltage levels) for differential inputs. V = V for LVCMOS input.
IH CC
IH
REF
= V
− 250 mV (ac voltage levels) for differential inputs. V = GND for LVCMOS input.
IL
IL
REF
= 600 mV
I(PP)
t
and t
are the same as t .
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
13
SN74SSTU32864C
25-BIT CONFIGURABLE REGISTERED BUFFER
WITH SSTL_18 INPUTS AND OUTPUTS
www.ti.com
SCES542A–JANUARY 2004–REVISED FEBRUARY 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
DUT
R
L
= 50 Ω
V
V
OH
Out
Test Point
80%
C
= 5 pF
Output
L
20%
(see Note A)
OL
dV_f
dt_f
VOLTAGE WAVEFORMS
LOAD CIRCUIT
HIGH-TO-LOW SLEW-RATE MEASUREMENT
HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
Out
dt_r
dV_r
Test Point
= 50 Ω
V
V
OH
80%
C
= 5 pF
L
Output
R
L
(see Note A)
20%
OL
LOAD CIRCUIT
LOW-TO-HIGH SLEW-RATE MEASUREMENT
VOLTAGE WAVEFORMS
LOW-TO-HIGH SLEW-RATE MEASUREMENT
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Z = 50 Ω, input slew rate = 1 V/ns ± 20% (unless otherwise specified).
O
Figure 2. Output Slew-Rate Measurement Information
14
PACKAGE OPTION ADDENDUM
www.ti.com
7-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74SSTU32864CGKER
SN74SSTU32864CZKER
ACTIVE
LFBGA
LFBGA
GKE
96
96
1000
None
Call TI
/
Call TI
PREVIEW
ZKE
Green (RoHS &
no Sb/Br)
Level-3-250C-1WEEK
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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