SN74SSTL32867GKER [TI]
SSTL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, PLASTIC, FBGA-96;
| 型号： | SN74SSTL32867GKER |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SSTL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, PLASTIC, FBGA-96 输出元件 逻辑集成电路 触发器 |
| 文件： | 总5页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74SSTL32867
DESIGNGOAL
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SCES240A – APRIL 1999 – REVISED MAY 1999
D
Member of the Texas Instruments
Widebus Family
D
D
Differential CLK Signal
Advanced ULTTL Output Circuitry
Eliminates Switching Noise in
Unterminated Line
D
Supports SSTL_2 Signal Data Inputs
D
Supports LVTTL Switching Levels on the
RESET Pin
D
Packaged in Plastic Fine-Pitch
Ball-Grid-Array Package
D
Flow-Through Architecture Optimizes PCB
Layout
description
This 26-bit registered buffer is designed for 2.3-V to 2.7-V V
LVCMOS-output applications.
operation and SSTL_2 input and unterminated
CC
Data flow from A to Y is controlled by differential clock (CLK, CLK) inputs and the LVTTL reset (RESET) input.
Data are triggered on the positive edge of the positive clock (CLK). The negative clock (CLK) is used to maintain
noise margins. When RESET is low, all registers are reset, and all outputs are low.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
The SN74SSTL32867 is characterized for operation from 0°C to 70°C.
GKE PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
A1
V
GND
V
Y1
Y2
Y4
Y6
Y8
CC
DDQ
A
B
C
D
A3
A2
A4
V
REF
NC
GND
GND
Y3
A5
Y5
A7
A6
GND
V
DDQ
GND
Y7
A9
A8
V
CC
GND
Y9
V
DDQ
E
F
G
H
J
A11
A13
A15
CLK
CLK
A16
A18
A20
A22
A24
A26
A10
A12
A14
NC
V
DDQ
Y10
Y12
GND
GND
Y15
Y17
Y18
Y20
Y22
Y24
Y26
GND
Y11
G
H
J
V
CC
V
DDQ
GND
GND
GND
GND
Y13
Y14
Y16
GND
K
L
RESET
A17
A19
A21
A23
A25
V
CC
V
DDQ
GND
V
DDQ
K
L
M
N
P
R
T
V
CC
GND
V
DDQ
Y19
GND
NC
V
DDQ
GND
M
N
P
R
T
Y21
Y23
Y25
NC
GND
V
CC
GND
V
DDQ
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6–21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL32867
DESIGN GOAL
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SCES240A – APRIL 1999 – REVISED MAY 1999
FUNCTION TABLE
INPUTS
OUTPUT
Y
RESET
CLK
CLK
A
H
↑
↓
H
H
L
H
H
L
↑
L or H
X
↓
L or H
X
L
X
X
Y
0
L
logic diagram (positive logic)
K2
RESET
J1
CLK
CLK
K1
B3
A1
V
REF
A1
1D
C1
A5
Y1
R
To 25 Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
or V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
DDQ
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V
CC
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
DDQ
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V , V
O
DDQ
CC DDQ
, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, q (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. Current flows only when the output is in the high state and V > V
.
DDQ
O
3. The package thermal impedance is calculated in accordance with JESD 51.
6–22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL32867
DESIGN GOAL
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SCES240A – APRIL 1999 – REVISED MAY 1999
recommended operating conditions (see Note 4)
MIN
NOM
MAX
2.7
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Supply voltage
V
CC
DDQ
REF
TT
I
DDQ
2.3
Output supply voltage
2.7
V
Reference voltage (V
Termination voltage
Input voltage
= V
/2)
DDQ
1.15
1.25
1.35
V
REF
V
–40mV
V
V
+40mV
REF
V
REF
REF
0
V
CC
V
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Data input
Data input
Data input
Data input
RESET
V
+350mV
+180mV
1.7
V
IH
REF
V
–350mV
REF
V
IL
V
V
IH
REF
V
–180mV
REF
V
IL
V
IH
RESET
0.7
V
IL
Common-mode input voltage range
Peak-to-peak input voltage
High-level output current
CLK, CLK
CLK, CLK
0.97
360
1.53
V
ICR
I(PP)
mV
I
I
–8
8
OH
mA
Low-level output current
OL
T
Operating free-air temperature
0
70
_C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
MAX
UNIT
V
IK
I = –18 mA
I
2.3 V
–1.2
V
I
I
I
I
I
I
= –100 µA
= –4 mA
= –8 mA
= 100 µA
= 4 mA
2.3 V to 2.7 V
V
–0.2
OH
OH
OH
OL
OL
OL
CC
V
2
V
V
OH
2.3 V
2.3 V to 2.7 V
2.3 V
1.7
0.2
0.3
0.6
±5
±5
±5
±5
±5
V
OL
= 8 mA
Data inputs
V = 1.7 V or 0.8V
V
V
= 1.15 V or 1.35 V
= 1.15 V or 1.35 V
I
REF
2.7 V
RESET input
V = 2.7 V or 0
I
V = 1.7 V or 0.8V
I
I
I
µA
2.7 V
2.7 V
2.7 V
CLK, CLK
REF
V = 2.7 V or 0
I
V
REF
V
= 1.15 V or 1.35 V
REF
V = 1.7 V or 0.8 V
I
I
I
O
= 0
mA
pF
pF
CC
V = 2.7 V or 0
I
RESET input
Data inputs
†
C
C
V = 1.7 V or 0.8 V
I
2.5 V
i
†
Outputs
V
= 1.7 V or 0.8 V
2.5 V
o
O
†
All typical values are at V
= 2.5 V, T = 25°C.
A
CC
6–23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL32867
DESIGN GOAL
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SCES240A – APRIL 1999 – REVISED MAY 1999
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
= 2.5 V ± 0.2 V
CC
UNIT
MIN
200
1.6
1.1
1.1
0.5
TYP
MAX
f
t
Clock frequency
MHz
ns
clock
Pulse duration, CLK, CLK high or low
0.8
0.5
0.5
0
w
Data before CLK↑, CLK↓
t
Setup time
ns
ns
su
h
RESET high before CLK↑, CLK↓
t
Hold time, data after CLK↑, CLK↓
switching characteristics over recommended operating free-air temperature range,
= V /2 and C = 10 pF (unless otherwise noted) (see Figure 1)
V
REF
DDQ
L
V
CC
MIN
= 2.5 V ± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MAX
f
t
200
2.8
MHz
ns
max
CLK and CLK
RESET
Y
Y
1.9
2.2
pd
t
3.2
ns
PHL
switching characteristics over recommended operating free-air temperature range,
V
= V
/2 and C = 30 pF (unless otherwise noted) (see Figure 1)
REF
DDQ L
V
CC
MIN
= 2.5 V ± 0.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
TYP
MAX
200
3.8
f
t
MHz
ns
max
CLK and CLK
RESET
Y
Y
2.6
2.9
pd
t
4.4
ns
PHL
6–24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74SSTL32867
DESIGN GOAL
26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SCES240A – APRIL 1999 – REVISED MAY 1999
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
From Output
Under Test
Test
Point
C
= 10 pF or 30 pF
L
(see Note A)
LOAD CIRCUIT
t
w
‡
‡
§
V
V
V
IH
IH
†
†
Input
V
REF
V
REF
†
†
Input
V
REF
V
REF
§
IL
V
IL
t
PLH
t
PHL
VOLTAGE WAVEFORMS
PULSE DURATION
V
V
OH
Output
V
CC
/2
V
/2
CC
OL
‡
V
V
IH
Timing
Input
†
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
V
REF
§
IL
t
t
h
su
‡
V
V
IH
Data
Input
†
†
V
REF
V
REF
§
IL
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
†
‡
§
V
V
V
= V
/2
DDQ
REF
IH
IL
= V
+350mV (ac voltage levels) for SSTL inputs. V = V for LVTTL inputs.
REF IH
CC
= V
–350mV (ac voltage levels) for SSTL inputs. V = GND for LVTTL inputs.
REF IL
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 1.25 ns/V,
O
r
t ≤ 1.25 ns/V.
f
C. The outputs are measured one at a time with one transition per measurement.
D.
t
and t
are the same as t
.
pd
PLH
PHL
Figure 1. Load Circuit and Voltage Waveforms
6–25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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