SN75ALS085DW [TI]
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER; 局域网接入单元接口双驱动器/接收器
| 型号： | SN75ALS085DW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER |
| 文件： | 总17页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
DW OR NT PACKAGE
Meets or Exceeds the Requirements of IOS
8802.3:1989 and ANSI/IEEE Std 802.3-1988
(TOP VIEW)
Interdevice Loop-Back Paths for System
Testing
TXI1
TXEN1
LOOP1
GND
TXO1
TXO1
1
24
23
22
21
20
2
Squelch Function Implemented on the
Receiver Inputs
V
3
CC
RXI1
RXI1
4
RXEN1
RXO1
RXO2
RXEN2
GND
5
Drivers Will Drive a Balanced 78-Ω Load
6
19 GND
Transformer Coupling Not Required in
System
7
18
17
16
15
14
13
GND
RXI2
RXI2
8
Power-Up/Power-Down Protection (Glitch
Free)
9
10
11
12
LOOP2
TXEN2
TXI2
V
CC
Isolated Ground Pins for Reduced Noise
Coupling
TXO2
TXO2
Fault-Condition Protection Built into the
Device
Driver Inputs Are Level-Shifted ECL
Compatible
description
The SN75ALS085 is a monolithic, high-speed, advanced low-power Schottky, dual-channel driver/receiver
device designed for use in the AUI of ANSI/IEEE Std 802.3-1988. The two drivers on the device drive a 78-Ω
balanced, terminated twisted-pair transmission line up to a maximum length of 50 meters. In the off (idle) state,
the drivers maintain minimal differential output voltage on the twisted-pair line and, at the same time, remain
within the required output common-mode range.
With the driver enable (TXEN) high, upon receiving the first falling edge into the driver input, the differential
outputs will rise to full-amplitude output levels within 25 ns. The output amplitude is maintained for the remainder
of the packet. After the last positive packet edge is transmitted into the driver, the driver will maintain a minimum
of 70% full differential output for a minimum of 200 ns, then decay to a minimum level for the reset (idle) condition
within 8 µs. Disabling the driver by taking the driver enable low will also force the output into the idle condition
after the normal 8-µs timeout. While operating, the drivers are able to withstand a set of fault conditions and not
suffer damage due to the faults being applied. The drivers power up in the idle state to ensure that no activity
is placed on the twisted-pair cable that could be interpreted as network traffic.
The line receiver squelch function interfaces to a differential twisted-pair line terminated external to the device.
The receiver squelch circuit allows differential receive signals to pass through as long as the input amplitude
and pulse duration are greater than the minimum squelch threshold. This ensures a good signal-to-noise ratio
while the data path is active and prevents system noise from causing false data transitions during line shutdown
and line-idle conditions. The RXO outputs default to a high level and the RXEN outputs default to a low level
while the squelch function is blocking the data path through the receiver (idle). The line receiver squelch will
become active within 50 ns when the input squelch threshold is exceeded. RXEN will be driven high when the
squelch circuit is allowing data to pass through the receiver. The receiver squelch circuit can also withstand a
set of fault conditions while operating without causing permanent damage to the device.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
description (continued)
The purpose of the loop functions is to provide a means by which system data path verification can be done
to isolate faulty interfaces and assist in network diagnosis. The LOOP pins are TTL compatible and must be
held high for normal operation. When LOOP1 is taken low, the output of driver 1 (TXO1) immediately goes into
the idle state. Also, the input to receiver 1 is ignored and a path from TXI1 to RXO1 is established. When LOOP1
is taken back high, driver 1 and receiver 1 revert back to their normal operation. When LOOP2 is taken low, a
similar data path is established between TXI1 and RXO2. TXEN1 must be high for the loop functions to operate
and TXEN1 can be used to gate the loop function if desired. During loop operation, the respective receiver
enable output (RXEN) will reflect the status of TXEN1.
Function Tables
RECEIVER – LOOP = H
OUTPUTS
RXI
= 1315 mV to –175 mV,
= –275 mV to –1315 mV,
= 318 mV to 1315 mV,
= 318 mV to 1315 mV,
PREVIOUS RXEN
RXEN
RXO
H
V
ID
V
ID
V
ID
V
ID
t
w
t
w
t
w
t
w
< 25 ns
> 50 ns
< 142 ns
> 187 ns
L
X
H
X
L
H
H
L
L
H
H
H = high level, L = low level, X = don’t care
DRIVER – LOOP = H
TXI
TXEN
PREVIOUS TXO
Idle
OUTPUT TXO
L
L
Idle
Idle
L
H
L
H
Idle
↓
Idle
L
H
Active
Active
Active
Active
Active
Active
Active
Active
L
H < 260 µs
H > 8 µs
L
H
H
H
Idle
Idle
Idle
H
L > 8 µs
L > 8 µs
L < 260 ns
L < 260 ns
L < 260 ns
H < 260 ns
H < 260 ns
H > 8 µs
L
Idle
L
H = V ≥ V max, L = V ≤ V min
I
T
I
T
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
Function Tables (continued)
LOOP
INPUTS
OUTPUTS
LOOP1
LOOP2
TXI1
TXEN1
RXI1
RXI2
RXO1
RXO2
RXEN1
RXEN2
TXO1
Idle
L
L
L
L
L
H
X
X
L
L
H
H
H
H
X
X
X
X
H
H
H
H
H
L
H
L
Idle
L
L
X
L
Idle
L
H
H
H
L
L
H
X
Normal
Normal
Normal
X
L
Normal
Normal
Normal
L
H
Normal
Normal
Normal
H
Idle
L
H
H
X
H
H
Idle
L
X
L
X
H
L
Idle
H
H
H
H
L
H
H
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Idle
L
H
L
X
H
H
Idle
L
X
X
H
L
Idle
H
Normal
Normal
Normal
Normal
Normal
Normal
H = high level, L = low level, X = don’t care
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
logic diagram (positive logic)
20
RX11
RX11
Noise
Filter
21
5
6
RXEN1
+
–
150 ns
225 mV
RXO1
3
LOOP1
24
23
1
2
TXO1
TXO1
TXI1
ECL/TTL
250 ns
1
1
TXEN1
X1
4 µS
10
LOOP2
7
8
RXO2
17
16
150 ns
RXI2
RXI2
Noise
Filter
RXEN2
+
–
225 mV
14
13
12
TXO2
TXO2
ECL/TTL
TXI2
250 ns
11
1
1
4 µS
TXEN2
X1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
schematics of inputs and outputs
RXI AND RXI INPUTS
LOOP AND TXEN INPUTS
V
CC
V
CC
20 kΩ
4 kΩ
4 kΩ
4 kΩ
4 kΩ
4 kΩ
LOOP
RXI
RXI
and
TXEN
ESD
ESD
3 kΩ
ESD
+
–
1 kΩ
TXI INPUTS
RXO AND RXEN OUTPUTS
V
CC
V
CC
200 Ω
50 kΩ
50 Ω
TXI
ESD
RXO
and
5 kΩ
RXEN
ESD
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
CC
TXI and LOOP input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
TXO and TXO output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
RXI and RXI input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
RXO and RXEN output voltage, V
I
O
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65 °C to 150 °C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
NOTE 1: Voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T = 70°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
DW
NT
1350 mW
10.8 mW/°C
10.0 mW/°C
864 mW
1250 mW
800 mW
recommended operating conditions
MIN NOM
MAX
5.25
UNIT
V
Supply voltage, V
4.75
1
5
CC
Common-mode voltage at RXI inputs, V
4.2
V
IC
Differential voltage between RXI inputs, V
ID
High-level input voltage, LOOP and TXEN, V
±318
2
±1315
mV
V
IH
Low-level input voltage, LOOP and TXEN, V
IL
0.8
– 0.4
16
V
High-level output current, RXO and RXEN, I
mA
mA
ns
ns
ns
ns
ns
°C
OH
OL
Low-level output voltage, RXO and RXEN, I
Setup time, driver mode, TXEN high before TXI↓, t
su1
Setup time, loop mode, LOOP low before TXEN↑, t
(see Figure 7)
(see Figure 9)
10
15
10
10
15
0
su2
Setup time, loop mode, TXEN high before TXI↓, t
(see Figure 9)
su3
Hold time, loop mode, TXEN high after TXI↑, t (see Figure 8)
h1
Hold time, loop mode, LOOP low after TXEN↓, t (see Figure 8)
h2
Operating free-air temperature, T
70
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
Clamp voltage at all inputs
TEST CONDITIONS
I = –18 mA
MIN
MAX
UNIT
V
IK
–1.5
V
I
V
V
V
V
V
V
V
V
V
= 4.75 V
= 5 V
3.202 3.752
3.389 3.998
3.577 4.244
3.213 3.797
3.400 4.043
3.588 4.289
3.239 3.849
3.426 4.095
3.614 4.341
–275
CC
CC
CC
CC
CC
CC
CC
CC
CC
T
= 0°C
V
V
A
= 5.25 V
= 4.75 V
= 5 V
V
Driver input (TXI) threshold voltage
T
A
= 25°C
= 70°C
(TO)
= 5.25 V
= 4.75 V
= 5 V
T
A
V
= 5.25 V
Receiver differential input threshold voltage
Driver output (TXO) common-mode voltage
mV
TXEN at 0.8 V,
LOOP2 at 2 V,
LOOP1 at 2 V,
See Figure 1
Idle
1
4.2
TXEN at 2 V,
LOOP2 at 2 V,
See Figure 1
LOOP1 at 2 V,
TXI at 3.2 V,
Active
1
4.2
V
OC
V
TXEN at 2 V,
LOOP2 at 2 V,
See Figure 1
LOOP1 at 2 V,
TXI at 4.4 V,
Active
Idle
1
4.2
±40
TXEN at 0.8 V,
LOOP2 at 2 V,
LOOP1 at 2 V,
See Figure 1
TXEN at 2 V,
LOOP2 at 2 V,
See Figure 1
LOOP1 at 2 V,
TXI at 3.2 V,
Active
– 600
1315
V
OD
Driver output (TXO) differential voltage
mV
TXEN at 2 V,
LOOP2 at 2 V,
See Figure 1
LOOP1 at 2 V,
TXI at 4.4 V,
Active
600
2.4
1315
V
V
High-level output voltage
Low-level output voltage
RXO, RXEN
RXO, RXEN
TXEN, LOOP
TXI
I
I
= –0.4 mA
= 16 mA
V
V
OH
OH
0.5
20
OL
OL
V = 2 V
I
I
IH
High-level input current
V = 4.5 V
I
400
µA
RXI, RXI
V
= –0.5 V,
V
V
= 1 V to 4.2 V
= 1 V to 4.2 V
1000
–200
100
ID
V = 0.8 V
IC
IC
TXEN, LOOP
I
V = 3.1 V
I
I
IL
Low-level input current
TXI
mA
V = 0.3 V
I
4
10
RXI, RXI
Idle
V
ID
= 0.5 V,
1000
TXEN at 0.8 V,
LOOP2 at 2 V,
LOOP1 at 2 V,
See Figure 2
I
I
I
Driver differential output current
±4
mA
mA
mA
OD
OS
CC
V
at 0 V,
RXI at 3 V,
O
†
Short-circuit output current
Supply current
RXO, RXEN
– 40 – 150
225
RXI at 2 V
LOOP2 at 2 V,
TXI at 4.5 V,
TXEN at 2 V,
Outputs open
†
Not more than one output should be shorted at a time, and the duration of the test should not exceed 1 second.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
†
PARAMETER
TEST CONDITIONS
TXO shorted to TXO, Current measured in short
MIN
MAX
150
150
150
150
150
150
150
10
UNIT
TXO at 0 V,
TXO is open,
TXO at 0,
Current measured at TXO
TXO is open,
TXO at 0 V,
Current measured at TXO
Driver fault condition current
TXO at 0 V,
TXO is open,
TXO at 16 V,
TXO at 16 V,
Current measured at TXO and TXO
Current measured at TXO
mA
TXO at 16 V,
TXO is open,
TXO at 16 V,
RXI shorted to RXI,
RXI at 0 V,
Current measured at TXO
Current measured at TXO and TXO
Current measured in short
RXI is open,
RXI at 0 V,
RXI at 0 V,
RXI at open,
RXI at 16 V,
RXI at 16 V,
Current measured at RXI
3
RXI is open,
Current measured at RXI
3
Receiver fault condition current RXI at 0 V,
Current measured at RXI and RXI
Current measured at RXI
3
mA
RXI at 16 V,
RXI at open,
RXI at 16 V,
10
Current measured at RXI
10
Current measured at RXI and RXI
10
†
Fault conditions should be measured on only one channel at a time.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
driver
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
MAX
15
UNIT
ns
Propagation delay time,
low-to-high level output
t
t
t
t
t
TXI
TXI
TXO, TXO TXEN at 2 V,
TXO, TXO TXEN at 2 V,
TXO, TXO TXEN at 2 V,
TXO, TXO TXI at 3.2 V,
TXO, TXO TXEN at 2 V,
TXO, TXO TXEN at 2 V,
TXO, TXO TXEN at 2 V,
See Figure 3
See Figure 3
See Figure 4
See Figure 5
See Figure 6
See Figure 6
See Figure 3
PLH
PHL
PIL
PIL
w
Propagation delay time,
high-to-low level output
15
ns
Propagation delay time,
idle-to-low level output
TXI
25
ns
Propagation delay time,
idle-to-low level output
TXEN
25
ns
Output pulse duration from low-
to-high level to 70% output level
260
8000
–100
±3
ns
Driver output differential
undershoot voltage
V
TXI
TXI
mV
ns
OD(U)
Driver caused signal skew
t
sk
t
– t
PLH PHL
t
t
Rise time, TXO, TXO
Fall time, TXO, TXO
TXEN at 2 V,
TXEN at 2 V,
See Figure 3
See Figure 3
1
1
5
5
ns
ns
r
f
receiver
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
MAX
15
UNIT
ns
Propagation delay time,
low-to-high level output
t
t
t
t
t
t
t
t
t
t
RXI, RXI
RXI, RXI
RXI, RXI
RXI, RXI
RXI, RXI
RXO
V
= 1 V to 4.2 V, See Figure 10
= 1 V to 4.2 V, See Figure 10
PLH
PHL
PLH
PHL
sk
IC
Propagation delay time,
high-to-low level output
RXO
RXEN
RXEN
RXO
V
V
15
ns
IC
Start-up delay time,
low-to-high level output
= 1 V to 4.2 V,
See Figure 12
V
ID
V
ID
V
ID
V
ID
V
ID
V
ID
V
ID
V
ID
V
ID
= –500 mV,
= 500 mV,
= 500 mV,
= –175 mV,
= –275 mV,
= ±500 mV,
= ±500 mV,
= ±500 mV,
= ±500 V,
IC
55
ns
Shutdown delay time,
high-to-low level output
V
= 1 V to 4.2 V,
IC
See Figure 12
142
25
181
±3
ns
Receiver caused signal
V
= 1 V to 4.2 V,
IC
See Figure 10
ns
skew (t
– t )
PLH PHL
Pulse duration at RXI and RXI
(to not activate squelch)
V
= 1 V to 4.2 V,
IC
See Figure 11
ns
w
Pulse duration at RXI and RXI
(to activate squelch)
V
= 1 V to 4.2 V,
IC
See Figure 11
50
8
ns
w
V
= 1 V to 4.2 V,
IC
See Figure 10
Rise time, RXO
Rise time, RXEN
Fall time, RXO
1
1
1
ns
r1
V
= 1 V to 4.2 V,
IC
See Figure 12
8
ns
r2
V
= 1 V to 4.2 V,
IC
See Figure 10
8
ns
f1
V
IC
= 2.5 V,
See Figure 12
t
t
Fall time, RXEN
1
8
ns
ns
f2
RXO valid after RXEN high
See Figure 10
–10
15
v
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
loop
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITIONS
MIN
MAX
30
UNIT
ns
Propagation delay time,
low-to-high level output
LOOP at 0.8 V,
TXEN at 2 V,
TXEN at 2 V,
t
t
t
t
TXI
TXI
RXO
RXO
PLH
PHL
PLH
PHL
See Figure 13
Propagation delay time,
high-to-low level output
LOOP at 0.8 V,
See Figure 13
30
ns
Propagation delay time,
low-to-high level output
TXEN
TXEN
RXEN
RXEN
LOOP at 0.8 V,
LOOP at 0.8 V,
See Figure 14
See Figure 14
50
ns
Propagation delay time,
high-to-low level output
50
ns
PARAMETER MEASUREMENT INFORMATION
V
TXO
TXO
TXO
39 Ω
V
OD
TXI
39 Ω
V
OC
V
TXO
Figure 1. Driver Test Circuit
TXO
I
OD
TXI
TXO
Figure 2. Driver Test Circuit
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
TXO
39 Ω
0.01 µF
25 pF
V
OD
3 kΩ
3 kΩ
TXI
39 Ω
TXO
25 pF
TEST CIRCUIT
50% 50%
4.5 V
3 V
TXI
t
t
PHL
PLH
V
OD+
90%
90%
TXO
0 V
0 V
10%
10%
V
OD–
t
r
t
f
VOLTAGE WAVEFORMS
TRANSFORMER SPECIFICATIONS
Turns Ratio
1:1
Magnetizing Inductance
Winding Resistance
Rise Time 10% to 90%
Interwinding Capacitance
Leakage Inductance
Inductive Q
26 to 30 µH
0.6 Ω Max
5 ns Max
25 pF
0.25 µH Max
1250 Min
Figure 3. Test Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
TXO
39 Ω
0.01 µF
25 pF
V
OD
3 kΩ
3 kΩ
†
TXI
39 Ω
TXO
25 pF
†
See Figure 3
TEST CIRCUIT
50%
4.5 V
3 V
TXI
t
PIL
IDLE
TXO
90%
V
OD–
VOLTAGE WAVEFORMS
NOTE: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 4. Test Circuit and Voltage Waveforms
TXEN
TXI
TXO
39 Ω
0.01 µF
25 pF
V
3 kΩ
3 kΩ
OD
†
39 Ω
TXO
25 pF
†
See Figure 3
TEST CIRCUIT
50%
2 V
TXEN
0.8 V
t
PIL
Idle
TXO
90%
V
OD–
VOLTAGE WAVEFORMS
Figure 5. Test Circuit and Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
TXO
39 Ω
25 pF
V
OD
3 kΩ
3 kΩ
†
TXI
0.01 µF
39 Ω
TXO
25 pF
†
See Figure 3
TEST CIRCUIT
V
OH
70%
TXO
50%
V
OD(U)
V
OL
t
w
VOLTAGE WAVEFORMS
Figure 6. Test Circuit and Voltage Waveforms
2 V
TXEN
50%
0.8 V
t
su1
4.5 V
3 V
50%
TXI
NOTE: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 7
4.5 V
3 V
TXI
50%
t
h1
2 V
50%
TXEN
LOOP
0.8 V
t
h2
2 V
50%
0.8 V
NOTE: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 8
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
2 V
50%
LOOP
0.8 V
t
su2
2 V
TXEN
50%
0.8 V
t
su3
4.5 V
3 V
50%
TXI
NOTE: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 9
RXEN
6 kΩ
20 pF
RXI
RXI
RXO
20 pF
6 kΩ
TEST CIRCUIT
1 V
RXI
0 V
–1 V
V
OH
IL
RXEN
90%
V
t
PHL
t
PLH
t
v
t
f1
t
r1
V
V
OH
90%
10%
VOLTAGE WAVEFORMS
90%
10%
1.3 V
1.3 V
1.3 V
RXO
OL
NOTE: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 10. Test Circuit and Voltage Waveforms
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
RXEN
6 kΩ
20 pF
RXI
RXO
RXI
TEST CIRCUIT
0 V
– 40 mV
– 40 mV
RXI
V
IO
t
w
V
OH
OL
RXEN
V
VOLTAGE WAVEFORMS
NOTE: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 11. Test Circuit and Voltage Waveforms
RXEN
6 kΩ
20 pF
RXI
RXO
RXI
TEST CIRCUIT
1 V
RXI
0
– 40 mV
–1 V
t
PLH
t
PHL
V
V
OH
90%
t
90%
RXEN
10%
10%
t
OL
r2
f2
VOLTAGE WAVEFORMS
NOTE: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 12. Test Circuit and Voltage Waveforms
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75ALS085
LAN ACCESS UNIT INTERFACE DUAL DRIVER/RECEIVER
SLLS054B – APRIL 1989 – REVISED MAY 1995
PARAMETER MEASUREMENT INFORMATION
4.5 V
3 V
50%
50%
TXI
t
t
PLH
PHL
V
OH
OL
1.3 V
1.3 V
RXO
V
NOTE: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 13
2 V
TXEN
RXEN
50%
50%
0.8 V
t
PLH
t
PHL
V
V
OH
1.3 V
1.3 V
OL
NOTE: Input t ≤ 5 ns; t ≤ 5 ns
r
f
Figure 14
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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