SN75DPHY440SSRHRR [TI]
工作温度为 0°C 至 70°C 的 MIPI® CSI-2/DSI DPHY 重定时器 | RHR | 28 | 0 to 70;
| 型号： | SN75DPHY440SSRHRR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 工作温度为 0°C 至 70°C 的 MIPI® CSI-2/DSI DPHY 重定时器 | RHR | 28 | 0 to 70 商用集成电路 |
| 文件： | 总36页 (文件大小：1452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN65DPHY440SS, SN75DPHY440SS
ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
SNx5DPHY440SS CSI-2/DSI DPHY 重计时器
1 特性
3 说明
1
•
•
•
符合 MIPI DPHY 1.1 规范
DPHY440 是一款 1 至 4 通道时钟 MIPI DPHY 重定时
器，用于重新生成 DPHY 信令。该器件符合 MIPI
DPHY 1.1 标准，可在高达 1.5Gbps 的数据速率下应
用于 MIPI CSI-2 或 MIPI DSI 应用。
实现低成本电缆解决方案
在 1.5Gbps 速率时最多支持 4 条通道
–
CSI-2/DSI 时钟频率范围为
100MHz 至 750MHz
该器件会补偿 PCB、连接器和电缆相关频率损耗和开
关相关损耗，以在 CSI2/DSI 源设备和接收设备之间提
供最佳 DP 电气性能。DPHY440 的 DPHY 输入端具
有可配置的均衡器。
•
•
•
•
•
•
•
•
•
•
关断状态下的功耗低于 mW
支持 MIPI DSI 双向 LP 模式
支持 ULPS 和 LP 功耗状态
可调输出电压摆幅
输出引脚会自动补偿在器件输入端口上接收的时钟和数
据间的不一致偏移。DPHY440 输出电压摆幅和边沿速
率可分别通过更改 VSADJ_CFG0 引脚和 ERC 引脚的
状态进行调节。
可选 TX 预加重电平
可调 Rx EQ 以补偿 ISI 损耗
可配置边沿速率控制
动态数据和时钟偏移补偿
具有 3kV ESD HBM 保护功能
DPHY440 针对移动 应用进行了优化，并且在 DPHY
链路接口上装有活动检测电路，以便在检测到 ULPS
和 LP 状态时切换到低功耗模式。
工业温度范围：-40°C 至 85°C
(SN65DPHY440SS)
•
•
商业级温度范围：0°C 至 70°C
(SN75DPHY440SS)
SN65DPHY440SS 在 -40ºC 至 85ºC 的工业级温度范
围内额定运行，而 SN75DPHY440SS 在 0ºC 至 70ºC
的商业级温度范围内额定运行。
由 1.8V 单电源供电
2 应用
器件信息 (1)
•
•
•
•
笔记本电脑
器件型号
封装
封装尺寸（标称值）
翻盖结构
平板电脑
摄像机
SN65DPHY440SS
SN75DPHY440SS
WQFN (28)
3.50mm x 5.50mm
(1) 要了解所有可用封装，请参阅数据表末尾的可订购产品附录。
简化原理图
典型应用
Camera
APU
(CSI-2 Source)
(CSI-2 Sink)
DPHY440
CSI TX
CSI RX
DB0P/N
DB1P/N
DBCP/N
DB2P/N
DB3P/N
CSI0P/N
CSI1P/N
CSICP/N
CSI2P/N
CSI3P/N
DA0P/N
DA1P/N
DACP/N
DA2P/N
DA3P/N
CSI0P/N
CSI1P/N
CSICP/N
CSI2P/N
CSI3P/N
Vio
CSI Slave
SCL
CSI Master
SCL
SDA
SDA
Copyright © 2016, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEO9
SN65DPHY440SS, SN75DPHY440SS
ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
www.ti.com.cn
目录
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 14
7.5 Register Maps......................................................... 15
Application and Implementation ........................ 21
8.1 Application Information, ......................................... 21
8.2 Typical Application, CSI-2 Implementations ........... 21
Power Supply Recommendations...................... 25
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics, Power Supply ................. 7
6.6 Electrical Characteristics........................................... 7
6.7 Timing Requirements................................................ 8
6.8 Switching Characteristics.......................................... 9
6.9 Typical Characteristics............................................ 10
Detailed Description ............................................ 11
7.1 Overview ................................................................. 11
7.2 Functional Block Diagram ....................................... 11
8
9
10 Layout................................................................... 26
10.1 Layout Guidelines ................................................. 26
10.2 Layout Example .................................................... 26
11 器件和文档支持 ..................................................... 27
11.1 相关链接................................................................ 27
11.2 社区资源................................................................ 27
11.3 商标....................................................................... 27
11.4 静电放电警告......................................................... 27
11.5 Glossary................................................................ 27
12 机械、封装和可订购信息....................................... 27
7
4 修订历史记录
Changes from Revision B (August 2017) to Revision C
Page
•
Changed F(BR) MAX value From: 1 Gbps To: 1.5 Gbps in the Switching Characteristics table............................................. 9
Changes from Revision A (April 2016) to Revision B
Page
•
•
将特性 从“CSI-2/DSI 时钟频率范围为 100MHz 至 500MHz”更改为“CSI-2/DSI 时钟频率范围为 100MHz 至 750MHz”......... 1
更改了说明 部分的文本，将“高达 1Gbps 的数据速率下的 MIPI DSI 应用。” 更改为“高达 1.5Gbps 的数据速率下的
MIPI DSI 应用。” .................................................................................................................................................................... 1
•
•
•
•
•
•
•
•
Changed VIH = 4 dB To: VIH = 5 dB in the Pin Functions table.............................................................................................. 4
Added a Test Condition of EQ is at 750 MHz to V(RXEQ1) n the Electrical Characteristics table ............................................ 7
Changed V(RXEQ2) TYP value From: 4 dB To: 5 dB in the Electrical Characteristics table .................................................... 7
Changed the MIPI DPHY HS Interface section in the Timing Requirements table................................................................ 8
Changed F(HSCLK) From 500 µsMHz To: 750 MHz in the Switching Characteristics table ..................................................... 9
Changed F(DESKEW) from 500 MHz To: 750 MHz. .................................................................................................................. 9
Changed tR and tF Datarate Test Conditions and values ...................................................................................................... 9
Changed text From: application at datarates of up to 1 Gbps To: application at datarates of up to 1.5 Gbps in the
Overview section .................................................................................................................................................................. 11
•
•
•
•
Changed Table 1 ................................................................................................................................................................. 12
Changed 11 – 4 dB To: 11 – 5 dB for RXEQ_CLK in Table 8 ............................................................................................ 17
Changed 11 – 4 dB To: 11 – 5 dB for RXEQ_DATA in Table 8 ......................................................................................... 17
Changed From: Data Rate To: Data Rate (200 Mbps to 1.5 Gbps) in Table 15.................................................................. 22
2
版权 © 2016–2019, Texas Instruments Incorporated
SN65DPHY440SS, SN75DPHY440SS
www.ti.com.cn
ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
Changes from Original (March 2016) to Revision A
Page
•
•
•
•
•
•
•
•
•
•
将特性从“具有 3kV ESD HBM 保护功能”更改为“具有 2kV ESD HBM 保护功能”................................................................... 1
Changed From: (approx. 100K) To: (100K) in the Pin Functions table for pins 13 and 14.................................................... 4
Changed From: (approx. 100K) To: (100K) in the Pin Functions table for pins 26, 27, and 28............................................. 5
Changed ESD Ratings values. HBM From: ±2000 To: ±3000, and CDM Form: ±500 To: ±1000 ........................................ 6
Changed V(RXEQ2) TYP value From: 5 dB To: 4 dB in the Electrical Characteristics table .................................................... 7
Added MIN and MAX values to |VOD(VD0)|, |VOD(VD1)|, and |VOD(VD2)| in the Electrical Characteristics table ............................ 7
Deleted rows ZOS and ΔZOS from the Electrical Characteristics table .................................................................................... 8
Updated the MIPI DPHY LP Transmitter Interface section of the Switching Characteristics table........................................ 9
Changed 5 dB to 4 dB in HS Receive Equalization and Table 1 ........................................................................................ 12
Changed 11 – 4 dB To: 11 – 5 dB in Table 8 ..................................................................................................................... 17
Copyright © 2016–2019, Texas Instruments Incorporated
3
SN65DPHY440SS, SN75DPHY440SS
ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
www.ti.com.cn
5 Pin Configuration and Functions
RHR Package
28 Pin (WQFN)
Top View
DA0P
DA0N
DA1P
DA1N
DACP
DACN
DA2P
DA2N
DA3P
DA3N
1
24
23
22
21
20
19
18
17
16
15
DB0P
DB0N
DB1P
DB1N
DBCP
DBCN
DB2P
DB2N
DB3P
DB3N
2
3
4
Thermal
Pad
5
6
7
8
9
10
Pin Functions
PIN
INTERNAL
PULLUP/PULLDOWN
I/O
DESCRIPTION
NAME
NO.
CSI-2/DSI Lane 0 Differential positive Input. Supports DSI LP Backchannel.
If unused, this pin should be tied to GND.
DA0P
1
100-Ω
Differential
Input
CSI-2/DSI Lane 0 Differential negative Input. Supports DSI LP Backchannel.
If unused, this pin should be tied to GND.
DA0N
DA1P
2
3
CSI-2/DSI Lane 1 Differential positive Input. If unused, this pin should be
tied to GND.
100-Ω
Differential
Input
CSI-2/DSI Lane 1 Differential negative input. If unused, this pin should be
tied to GND.
DA1N
DACP
4
5
(Failsafe)
100-Ω
Differential
Input
CSI-2/DSI Differential Clock positive Input
DACN
6
CSI-2/DSI Differential Clock negative Input
(Failsafe)
CSI-2/DSI Lane 2 Differential positive Input. If unused, this pin should be
tied to GND.
100-Ω
Differential
Input
DA2P
DA2N
DA3P
DA3N
7
8
CSI-2/DSI Lane 2 Differential negative Input. If unused, this pin should be
tied to GND.
(Failsafe)
CSI-2/DSI Lane 3 Differential positive Input. If unused, this pin should be
tied to GND.
100-Ω
Differential
Input
9
CSI-2/DSI Lane 3 Differential negative Input. If unused, this pin should be
tied to GND.
10
(Failsafe)
VCC
11
12
Power
Power
1.8V (±10%) Supply.
VREG_OUT
1.2 V Regulator Output. Requires a 0.1 µF capacitor to GND.
RX Equalization Select. Pin state sampled on rising edge of RSTN. This pin
also functions as I2C SCL pin.
VIL = 0 dB
VIM = 2.5 dB
I/O
(3-level)
PU (100K)
PD (100K)
EQ/SCL
13
14
VIH = 5 dB
Edge Rate Control for DB[4:0]P/N High speed transmitter rise and fall time.
Pin state sampled on rising edge of RSTN. This pin also functions as I2C
SDA pin.
VIL = 200 ps typical
VIM = 150 ps typical
VIH = 250 ps typical
I/O
(3-level)
PU (100K)
PD (100K)
ERC/SDA
4
Copyright © 2016–2019, Texas Instruments Incorporated
SN65DPHY440SS, SN75DPHY440SS
www.ti.com.cn
ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
Pin Functions (continued)
PIN
INTERNAL
PULLUP/PULLDOWN
I/O
DESCRIPTION
NAME
NO.
CSI-2/DSI Lane 3 Differential negative Output. If unused, this pin should be
left unconnected.
DB3N
15
100-Ω
Differential
Output
CSI-2/DSI Lane 3 Differential positive Output. If unused, this pin should be
left unconnected.
DB3P
DB2N
DB2P
16
17
18
CSI-2/DSI Lane 2 Differential negative Output. If unused, this pin should be
left unconnected.
100-Ω
Differential
Output
CSI-2/DSI Lane 2 Differential positive Output. If unused, this pin should be
left unconnected.
DBCN
DBCP
19
20
100-Ω
Differential
Output
CSI-2/DSI Differential Clock negative Output
CSI-2/DSI Differential Clock positive Output
CSI-2/DSI Lane 1 Differential negative Output. If unused, this pin should be
left unconnected.
DB1N
DB1P
DB0N
DB0P
VDD
21
22
23
24
25
100-Ω
Differential
Output
CSI-2/DSI Lane 1 Differential positive Output. If unused, this pin should be
left unconnected.
CSI-2/DSI Lane 0 Differential negative Output. Supports DSI LP Back
channel. If unused, this pin should be left unconnected.
100-Ω
Differential
Output
CSI-2/DSI Lane 0 Differential positive Output. Supports DSI LP Back
channel. If unused, this pin should be left unconnected.
This pin must be connected to the VREG_OUT pin through at least a 10-mil
trace and a 0.1 µF capacitor to ground.
Power
Controls DPHY TX HS pre-emphasis level and the LP TX rise and fall times.
Pin state is sampled on the rising edge of RSTN.
I/O
(3-level)
PU (100K)
PD (100K)
PRE_CFG1
26
27
VIL = 0 dB
VIM = 0 dB
VIH = 2.5 dB
Controls output voltage swing for DB HS transmitters and the LP TX rise
and fall times. Pin state is sampled on the rising edge of RSTN. Refer to
Table 3 for details on voltage swing settings based on this pin and
PRE_CFG1 sampled state.
VIL = 200 mV or 220 mV based on PRE_CFG1 sampled state.
VIM = 200 mV typical
I
PU (100K)
PD (100K)
VSADJ_CFG0
(3-level)
VIH = 220 mV typical
Reset, active low. When low, all internal CSR are reset to default and
DPHY440 is placed in low power state.
RSTN
GND
28
I
PU (300K)
Thermal pad
GND
Ground.
Copyright © 2016–2019, Texas Instruments Incorporated
5
SN65DPHY440SS, SN75DPHY440SS
ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
2.175
1.4
UNIT
V
Supply voltage range
Voltage range
VCC
DPHY Lane I/O Differential Voltage
RSTN
V
2.175
2.175
105
V
All other terminals
V
Maximum junction temperature, TJ
Storage temperature, Tstg
°C
°C
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Charged-device model (CDM), per JEDEC specification JESD22-C101
±3000
V(ESD)
Electrostatic discharge
V
±1000
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.62
–40
0
NOM
MAX
1.98
85
UNIT
VCC
TA
Supply voltage
1.8
V
Operating free-air temperature [SN65DPHY440SS]
Operating free-air temperature [SN75DPHY440SS]
°C
70
6.4 Thermal Information
SNx5DPHY440SS
(1)
THERMAL METRIC
RHR (WQFN)
12 PINS
42.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
32.3
12.8
ψJT
0.5
ψJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
12.6
RθJC(bot)
5.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6
Copyright © 2016–2019, Texas Instruments Incorporated
SN65DPHY440SS, SN75DPHY440SS
www.ti.com.cn
ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
6.5 Electrical Characteristics, Power Supply
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Power under normal operation for 4 data
lanes + clock.
DPHY Lanes at 1 Gbps; VCC supply stable,
VCC = 1.8 V;
PACTIVE1_SS
PACTIVE2_SS
PLP11_SS
150
mW
Power under normal operation for 2 data
lanes + clock.
DPHY Lanes 1 Gbps; VCC supply stable,
VCC = 1.8 V;
115
14
mW
mW
mW
All DPHY lanes in LP11; VCC supply stable;
VCC = 1.8 V;
LP11 Power
RSTN Power
RSTN held in asserted state (low); VCC
supply stable; VCC = 1.8 V;
PRSTN_SS
0.75
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Standard IO (RSTN, ERC, EQ, CFG[1:0])
VIL
VIM
VIH
VF
Low-level control signal input voltage
0.2 x VCC
V
V
V
V
Mid-level control signal input voltage
High-level control signal input voltage
Floating Voltage
VCC / 2
VCC / 2
0.8 x VCC
VIN = High Impedance
At IOL max.
Low level output voltage (open-drain).
ERC (SDA) only
VOL
0.2 x VCC
V
IOL
Low Level Output Current
High level input current
3
±36
±36
mA
µA
µA
kΩ
kΩ
kΩ
IIH
IIL
Low level input current
RPU
RPD
R(RSTN)
Internal pull-up resistance
Internal pull-down resistance
RSTN control input pullup resistor
100
100
300
MIPI Input Leakage (DA1P/N, DA2P/N, DA3P/N, DACP/N)
VCC = 0 V; VDD = 0 V; MIPI DPHY pulled
up to 1.35 V
Ilkg
Input failsafe leakage current
–65
65
µAV
MIPI DPHY HS RECIEVER INTERFACE (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N)
Differential Input Common-mode voltage
HS Receive mode
V(CM-RX_DC)
| VID
V(CM-RX) = (VA x P + VA x N)/2
70
70
330
mV
|
HS Receiver input differential voltage
Single-ended input high voltage
Single-ended input low voltage
Differential input impedance
| VID | = |VA x P – VA x N
|
mV
mV
mV
Ω
VIH(HS)
460
125
VIL(HS)
–40
80
R(DIFF-HS)
V(RXEQ0)
V(RXEQ1)
V(RXEQ2)
100
0
Rx EQ gain when EQ/SCL pin ≤ VIL
Rx EQ gain when EQ/SCL pin = VIM
Rx EQ gain when EQ/SCL pin ≥ VIH
dB
dB
dB
At 750 MHz
At 750 MHz
2.5
5
MIPI DPHY LP Receiver Interface (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N, DB0P/N)
V(LPIH)
V(LPIL)
V(HYST)
LP Logic 1 Input Voltage
LP Logic 0 Input voltage
LP Input Hysteresis
880
25
mV
mV
mV
550
MIPI DPHY HS Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N)
HS Transmit static common-mode
voltage
V(CMTX)
V(CMTX) = (V(BP) + V(BN)) / 2
150
200
300
5
mV
mV
VCMTX mismatch when output is
Differential-1 or differential-0.
|∆V(CMTX) (1,0)
|
∆V(CMTX) (1,0) = (V(CMTX) (1) – V(CMTX) (0)) /2
HS Transmit differential voltage for
CFG0 = 2’b00 with TX pre-emphasis
disabled or for non-transition bit when
TX pre-emphasis is enabled.
|VOD(VD0)
|
|
|VOD| = |V(DP) - V(DN)
|
140
160
180
200
220
250
mV
mV
HS Transmit differential voltage for
CFG0 = VIM with TX pre-emphasis
disabled or for non-transition bit when
TX pre-emphasis is enabled.
|VOD(VD1)
|VOD| = |V(DP) - V(DN)| CFG0 = VIM
Copyright © 2016–2019, Texas Instruments Incorporated
7
SN65DPHY440SS, SN75DPHY440SS
ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
HS Transmit differential voltage for
CFG0 = VIH with TX pre-emphasis
disabled or for non-transition bit when
pre-emphasis is enabled..
|VOD(VD2)
|
|VOD| = |V(DP) - V(DN)| CFG0 ≥ VIH
170
220
270
mV
VOD mismatch when output is
differential-1 or differential-0.
|∆VOD
|
∆VOD = |∆VO(D1)| - |∆VO(D0)
|
14
mV
mV
dB
HS Output high voltage for non-
transition bit.
VOH(HS)
V(PRE1)
V(PRE2)
CFG0 ≥ VIH HS Pre = 2.5 dB
430
Pre-emphasis Level for HSTX_PRE =
2’b00.. Refer to Figure 3
PRE = 20 x LOG (VOD(TBx) / VOD(VDX)
PRE = 20 x LOG (VOD(TBx) / VOD(VDX)
)
)
1.5
2.5
Pre-emphasis level for HSTX_PRE =
2’b1X. Refer to Figure 3
dB
MIPI DPHY LP Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N, DA0P/N)
V(LPOH)
V(LPOL)
VIH(CD)
VIL(CD)
ZO(LP)
LP Output High Level
1.1
–50
450
1.2
1.3
50
V
LP Output Low Level
mV
mV
mV
Ω
LP Logic 1 contention threshold
LP Logc 0 contention threshold
Output Impedance of LP transmitter
200
110
6.7 Timing Requirements
MIN
NOM
MAX
UNIT
I2C (ERC (SDA), EQ (SCL))
tHD;STA
tLOW
Hold Time (repeated) START condition. After this period, the first clock pulse is generated
Low period of SCL clock
4
4.7
4
µs
µs
µs
µs
µs
µs
µs
µs
tHIGH
High period of SCL clock
tSU;STA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Setup time for a repeated START condition
Data hold time
4.7
5
Data setup time
4
Setup time for STOP condition
4
Bus free time between a STOP and START condition
4.7
MIPI DPHY HS Interface
tHSPD
Propagation delay from DA to DB.
4 + 12ns
–5
4 + 40ns
UI
%
750 MHz clock with 50%-50%
duty cycle at DAC input.
tDBC_DCYCLE DAC to DBC output duty cycle distortion percentage
5
tSKEW-TX-1G
tSETUP-RX-1G Data to Clock setup time. Refer to Figure 2
tHOLD-RX-1G Clock to data hold time. Refer to Figure 2
Data to Clock variation from 0.5UI. Refer to Figure 2
Datarate ≤ 1 Gbps
Datarate ≤ 1 Gbps
Datarate ≤ 1 Gbps
Datarate > 1 Gbps
–0.1
0.1
0.1
UI
UI
UI
UI
0.1
tSKEW-TX-1P5G Data to Clock variation from 0.5UI. Refer to Figure 2
–0.15
0.15
tSETUP-RX-
Data to Clock setup time. Refer to Figure 2
Datarate > 1 Gbps
Datarate > 1 Gbps
0.15
0.15
UI
UI
1P5G
tHOLD-RX-1P5G Clock to data hold time. Refer to Figure 2
8
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6.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I2C (ERC (SDA), EQ (SCL))
F(SCL)
tF_I2C
I2C Clock Freqency
100
300
kHz
ns
Fall time of both SDA and SCL signals
Load of 350 pF with 2-K pullup
resistor.
Measure at 30% - 70%
tR_I2C
Rise Time of both SDA and SCL signals
1000
ns
DPHY LINK
F(BR)
Bit Rate
1.5
750
750
Gbps
MHz
MHz
F(HSCLK)
F(DESKEW)
HS Clock Input range
Automatic Deskew range
100
220
MIPI DPHY HS Receiver Interface (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N)
∆V(CMRX_HF)
∆V(CMRX_LF)
Common-mode Interface beyond 450 MHz
100
50
mV
mV
Common-mode interference 50 MHz – 450 MHz
–50
MIPI DPHY HS Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N)
∆V(CMRX_HF)
∆V(CMRX_LF)
Common-level variations above 450 MHz
5
25
mVrms
mVpeak
UI
Common-level variation between 50 MHz – 450 MHz.
Datarate ≤ 1 Gbps
Datarate > 1 Gbps
0.3
tR and tF
20% - 80% rise time and fall time
0.35
UI
100
20
ps
MIPI DPHY LP Receiver Interface (DA0P/N, DA1P/N, DA2P/N, DA3P/N, DACP/N, DB0P/N)
eSPIKE
tMIN(RX)
V(INT)
Input Pulse rejection
300
200
V ps
ns
Minimum pulse width response
Peak interference amplitude
Interference Frequency
mv
F(INT)
450
42
Mhz
First LP XOR clock pulse after Stop
state or last pulse before Stop
state.
ns
ns
Pulse Width of the XOR of DAxP and
DAxN
t(LP-PULSE-RX)
All other pulses.
22
MIPI DPHY LP Transmitter Interface (DB0P/N, DB1P/N, DB2P/N, DB3P/N, DBCP/N, DA0P/N)
Measured at end of HS
transmission.
tREOT
30% - 85% rise time and fall time
35
ns
ns
First LP XOR clock pulse after Stop
state or last pulse before Stop state
40
t(LP-PULSE-TX)
Pulse Width of the LP XOR clock
All other pulses
20
90
ns
ns
t(LP-PER-TX)
Period of the LP XOR clock
Slew Rate at CLOAD = 70 pF
150
70
mV/ns
mV/ns
mV/ns
pF
δV/δtsr
Slew Rate at CLOAD = 0 pF Fallng edge only
Slew Rate at CLOAD = 0 pF Rising edge only
Load Capacitance
30
30
CLOAD
(1) (1) All typical values are at VCC = 3.3 V, and TA = 25°C.
SDA
t
BUF
t
f
t
HD;STA
t
t
r
LOW
t
f
t
SP
t
r
SCL
t
t
HD;STA
SU;STA
t
SU;STO
t
HIGH
t
t
SU;DAT
HD;DAT
STOP START
START
REPEATED
START
Figure 1. I2C Timing
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0.0UI
1.0UI
0.5UI
TSKEW-TX
THOLD-RX
TSETUP-RX
DCLK
D[3:0]
Figure 2. DPHY HS RX and TX Timing
DB*P
DB*N
VOD_TBx
VOD_VDx
VCMTX
Pre-Emphasis = 20 LOG ( VOD_TBX
/
VOD_VDX
)
Figure 3. DPHY HS TX Pre-emphasis
6.9 Typical Characteristics
0
-5
-5
-10
-15
-20
-25
-30
-35
-40
-45
-10
-15
-20
-25
-30
-35
-40
-45
-50
10
100
1k
10k 100k 1M 10M 100M 1G 10G
Frequency (Hz)
1
10
100
1k
10k 100k 1M 10M 100M 1G
Frequency (Hz)
D003
D004
Figure 4. Return Loss (RL), Transmitter
Figure 5. Return Loss (RL), Receiver
10
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7 Detailed Description
7.1 Overview
The DPHY440SS is a one to four lane and clock MIPI DPHY re-driver that regenerates the DPHY signaling. The
device complies with MIPI DPHY 1.1 standard and can be used in either a MIPI CSI-2 or MIPI DSI application at
datarates of up to 1.5 Gbps.
The device compensates for PCB, connector, and cable related frequency loss and switching related loss to
provide the optimum electrical performance from a CSI2/DSI source to sink. The DPHY440 DPHY inputs feature
configurable equalizers.
The output pins will automatically compensate for uneven skew between clock and data lanes. The DPHY440
output swing and edge rate can be adjusted by changing the state of the VSADJ_CFG0 pin and ERC pin
respectively.
The DPHY440 is optimized for mobile applications, and contains activity detection circuitry on the DPHY Link
interface that can transition into a lower power mode when in ULPS and LP states.
The device is characterized for an extended operational temperature range from –40ºC to 85ºC.
7.2 Functional Block Diagram
DB0P
DB0N
DA0P
DA0N
HS RX
LP RX/TX
HS TX
LP RX/TX
CHANNEL
CONTROL
DB1P
DB1N
DA1P
DA1N
HS RX
LP RX
HS TX
LP TX
CHANNEL
CONTROL
DBCP
DBCN
DACP
DACN
HS RX
LP RX
HS TX
LP TX
CHANNEL
CONTROL
DB2P
DB2N
DA2P
DA2N
HS RX
LP RX
HS TX
LP TX
CHANNEL
CONTROL
DB3P
DB3N
DA3P
DA3N
HS RX
LP RX
HS TX
LP TX
CHANNEL
CONTROL
I2C
Slave
VSADJ_CFG0
ERC/SDA
EQ/SCL
PRE_CFG1
VCC
RRST=300k
VREG_OUT
CSR
Space
VREG
LDO
VCore
VCC
GND
RESET/EN
RSTN
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7.3 Feature Description
7.3.1 HS Receive Equalization
The DPHY440 supports three levels of receive equalization to compensate for ISI loss in the channel. These
three levels are 0 dB, 2.5 dB, and 5 dB at 750MHz. The equalization level used by the DPHY440 is determined
by the state of the EQ/SCL pin at the rising edge of RSTN. If necessary, the receiver equalization level can also
be set through writing to the RXEQ register via the local I2C interface
Table 1. EQ/SCL pin Function
EQ/SCL PIN
≤ VIL
HS Rx EQUALIZATION
0 dB
VIM
2.1 dB at 500 MHz / 2.5 dB at 750 MHz
4 dB at 500 MHz / 5 dB at 750 MHz
≥ VIH
7.3.2 HS TX Edge Rate Control
The DPHY440 supports control of the rise and fall time for the DB[3:0]P/N and DBCP/N High Speed (HS)
transmitters. Depending on system operating datarate, the HS edge rate may need to be adjusted to help
improve EMI performance. The HS edge rate setting is determined through the sampled state of ERC/SDA pin at
the rising edge of RSTN. If necessary, the HS edge rate can be adjusted by writing to the HS_ERC register via
the local I2C interface.
Table 2. 8.3.2 HS TX Edge Rate Control
ERC/SDA PIN
≤ VIL
HS RISE/FALL TIMES
200 ps typical
VIM
150 ps typical
≥ VIH
250 ps typical
The DPHY440 also supports edge rate control for the LP interface. The adjustment of LP TX edge rate is
determined by the state of the VSADJ_CFG0 and PRE_CFG1 pins as depicted in Table 3, but can also be
modified by changing LP_ERC register through the local I2C interface
7.3.3 TX Voltage Swing and Pre-Emphasis Control
In some applications, the DPHY440 may be placed at a location in the system where the channel from DPHY440
DB[3:0]P/N interface to the DPHY Sink (CSI-2 or DSI) is extremely long and the DPHY Sink does not have
enough receive equalization to compensate for the ISI loss. In this application, the system architect may want to
use the DPHY440 TX pre-emphasis feature to compensate for the lack of equalization at the DPHY sink. The
DPHY440 provides two levels of pre-emphasis: 0 dB, and 2.5 dB. The TX Pre-emphasis settings is determined
through the sampled sate of PRE_CFG[1:0] pins at the rising edge of RSTN. If necessary, the TX Pre-emphasis
settings can be adjusted by writing to the HSTX_PRE register through the local I2C interface.
This feature must only be used when the HS pre-emphasis bit (transition bit) is attenuated by the channel.
Enabling pre-emphasis in a system that has little channel loss (transition bit is not attenuated) may result in
negative impact to system performance.
12
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Table 3. HS Voltage Swing, HS Pre-emphasis, LPTX Edge Rate Controls
DB[3:0] LP TX RISE/FALL
TIME
VSADJ_CFG0
PRE_CFG1
HS TX VOD
HS TX PRE-EMPHASIS
≤ VIL
VIM
≤ VIL
≤ VIL
≤ VIL
VIM
200 mV
200 mV
220 mV
200 mV
200 mV
220 mV
220 mV
200 mV
220 mV
0 dB
0 dB
18 ns
27 ns
18 ns
27 ns
21 ns
21 ns
27 ns
21 ns
21 ns
≥ VIH
≤ VIL
VIM
0 dB
0 dB
VIM
0 dB
≥ VIH
≤ VIL
VIM
VIM
0 dB
≥ VIH
≥ VIH
≥ VIH
2.5 dB
2.5 dB
2.5 dB
≥ VIH
7.3.4 Dynamic De-skew
The DPHY440 implements a dynamic de-skew feature which will continuously de-skew the HS data received on
the DA[3:0]P/N interface and provide a retimed version on the DB[3:0]P/N interface. The retimed version is
centered within the DBCP/N clock.
Lanes are skewed at Input
Lanes Deskewed at Output.
DACP
DACN
DBCP
DBCN
DA0P
DA0N
DB0P
DB0N
DA1P
DA1N
DB1P
DB1N
DA2P
DA2N
DB2P
DB2N
DA3P
DA3N
DB3P
DB3N
Data centered within clock
Data Delayed by
2 Clocks (4UI)
Figure 6. Dynamic De-skew
NOTE
The dynamic de-skew feature is only enabled in HS mode, and causes a 2 clock (4 UI)
delay of data while data traverses from DA to DB.
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7.4 Device Functional Modes
LP MODE
ULPS Exit
(LP11)
RSTN = 1
ULPS Entry
RSTN = 0
RSTN = 0
ULPS
HS Exit
(LP11)
HS Entry
SHUTDOWN
RSTN = 0
RSTN = 0
HS MODE
Figure 7. Functional Modes
7.4.1 Shutdown Mode
The DPHY440 can be placed into a low power consumption state by asserting the RSTN pin low while
maintaining a stable VCC and VDD power supply. While in the Shutdown state, the DPHY440 drives DB[3:0]P/N
and DBCP/N pins to the LP00 state. The DPHY440 ignores all activity on the DA[3:0]P/N and DACP/N pins while
in Shutdown mode. The Shutdown mode is exited by de-asserting the RSTN pin high. Upon exiting Shutdown
mode, the DPHY440 enters LP Mode operation and pass what is received on the DA interface to the DB
interface.
7.4.2 LP Mode
In this mode, the DPHY440 passes LP signals between DA[3:0]P/N and DB[3:0]P/N. The internal terminations for
the HS receiver and HS transmitter are disabled when operating in this mode.
The MIPI DSI specification defines bidirectional communication between the host and peripheral. When a
response is needed by the peripheral, the response is returned using LP signaling from DB0P/N to DA0P/N. The
DPHY440 only supports this communication over lane 0 (DB0P/N to DA0P/N). The remaining lanes cannot be
used for LP communications from peripheral to host (reverse direction).
7.4.3 ULPS Mode
The DPHY440 is continuously monitoring the DPHY LP protocol for entry into the ULPS state. Upon entry into
the ULPS state, the DPHY440 keeps active the logic necessary for LP signaling (LP rx, LPtx, LP state machine,
so forth). All logic needed for HS operation are disabled. This allows for a lower power state than can be
achieved when in operating other LP power states.
NOTE
ULPS mode can only be entered from LP Mode.
7.4.4 HS Mode
The HS mode is entered when the required sequence of LP signals is detected by the LP state machine. In this
mode, the internal termination for both the HS receiver and HS transmitter is enabled and the dynamic de-skew
feature is enabled. The DPHY440 remains in this mode until a HS exit is detected by the LP state machine.
Upon detecting the HS exit, the DPHY440 immediately transitions to LP Mode.
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7.5 Register Maps
The DPHY440 local I2C interface is enabled when RSTN is input high. Access to the CSR registers is supported
during ultra-low power state (ULPS). The EQ/SCL and ERC/SDA terminals are used for I2C clock and I2C data
respectively. The DPHY440 I2C interface conforms to the two-wire serial interface defined by the I2C Bus
Specification, Version 2.1 (January 2000) and supports up to 100 kHz.
The device address byte is the first byte received following the START condition from the master device. The 7
bit device address for DPHY440 is factory preset to 1101100.
Table 4. DPHY440 I2C Target Address Description
Bit 7 (MSB)
1
Bit 6
1
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
0
Bit 1
0
Bit 0 (W/R)
0/1
Address Cycle is 0xD8 (Write) and 0xD9 (Read)
The following procedure should be followed to write to the DPHY440 I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the DPHY440 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The DPHY440 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within DPHY440) to be written, consisting of one byte of
data, MSB-first
4. The DPHY440 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The DPHY440 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the DPHY440.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the DPHY440 I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the DPHY440 7-bit
address and a one-value “W/R” bit to indicate a read cycle
2. The DPHY440 acknowledges the address cycle.
3. The DPHY440 transmit the contents of the memory registers MSB-first starting at register 00h or last read
sub-address+1. If a write to the DPHY440 I2C register occurred prior to the read, then the DPHY440 starts at
the sub-address specified in the write.
4. The DPHY440 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after
each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the DPHY440 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
The following procedure should be followed for setting a starting sub-address for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the DPHY440 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The DPHY440 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within DPHY440) to be written, consisting of one byte of
data, MSB-first.
4. The DPHY440 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
NOTE
If no sub-addressing is included for the read procedure, and reads start at register offset
00h and continue byte by byte through the registers until the I2C master terminates the
read operation. If a I2C write occurred prior to the read, then the reads start at the sub-
address specified by the write.
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7.5.1 BIT Access Tag Conventions
A table of bit descriptions is typically included for each register description that indicates the bit field name, field
description, and the field access tags. The field access tags are described in Table 5.
Table 5. Tag Conventions
ACCESS TAG
NAME
Read
DEFINITION
The field may be read by software.
R
W
S
Write
The field may be written by software
Set
The field may be set by a write of one. Writes of zero to the field have no effect.
The field may be cleared by a write of one. Write of zero to the field have no effect.
Hardware may autonomously update this field
C
Clear
U
Update
No Access
N/A
Not accessible or not applicable
7.5.2 Standard CSR Registers (address = 0x000 - 0x07)
Figure 8. Standard CSR Registers (0x000 - 0x07)
7
6
5
4
3
2
1
0
DEVICE_ID
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. Standard CSR Registers (0x000 - 0x07)
Bit
Field
Type
Reset
Description
7:0
DEVICE_ID
R
0
For the DPHY440 these fields return a string of ASCII characters
returning “DPHY100”.
Addresses 0x07 - 0x00 = {0x20, 0x30, 0x30, 0x31, 0x59, 0x48,
0x50, 0x44}
7.5.3 Standard CSR Register (address = 0x08)
Figure 9. Standard CSR Register (0x08)
7
6
5
4
3
2
1
0
DEVICE_REV
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. Standard CSR Register (0x08)
Bit
Field
Type
Reset
Description
7:0
DEVICE_REV
R
0
Device revision.
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7.5.4 Standard CSR Register (address = 0x09)
Figure 10. Standard CSR Register(0x09)
7
6
5
4
3
2
1
0
Reserved
RXEQ_CLK.
RXEQ_DATA
R
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. Standard CSR Register (0x09)
Bit
7:4
3:2
Field
Type
R
Reset
Description
Reserved
RXEQ_CLK
0
0
Reserved
RW
This field selects the EQ level of the DACP/N. The value in this
field will match the sampled state of EQ/SCL pin at the rising
edge of RSTN. Software can change the value of this field at a
later time.
00 – 0 dB (EQ/SCL pin = VIL)
01 – 2.5 dB (EQ/SCL pin = VIM
)
10 – Reserved.
11 – 5 dB (EQ/SCL pin = VIH
)
1:0
RXEQ_DATA
RW
0
This field selects the EQ level of the DA[3:0]P/N . The value in
this field will match the sampled state of EQ/SCL pin at the
rising edge of RSTN. Software can change the value of this field
at a later time.
00 – 0 dB. (EQ/SCL pin = VIL)
01 – 2.5 dB (EQ/SCL pin = VIM
)
10 – Reserved.
11 – 5 dB. (EQ/SCL pin = VIH
)
7.5.5 Standard CSR Register (address = 0x0A)
Figure 11. Standard CSR Register (0x0A)
7
6
5
4
3
2
1
0
LPTXDA_ERC
LPTXDB_ERC
Reserved
HSC_ERC
RW
RW
RW
RW
R
R
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. Standard CSR Register (0x0A)
Bit
Field
Type
Reset
Description
7:6
LPTXDA_ERC
RW
0
This field controls the edge rate of the DA0P/N LP transmitters.
00 – 18 ns at 70 pF (Default)
01 – 21 ns at 70 pF
10 – 15 ns at 70 pF
11 – 27 ns at 70 pF
5:4
LPTXDB_ERC
RW
0
This field controls the edge rate of the DB[3:0]P/N LP
transmitters. The value in this field will be updated by hardware
based on the state of the CFG[1:0] pin. Refer to Table 3 for
settings based on sampled state of CFG[1:0] Software can
change the value of this field at a later time.
00 – 18 ns at 70 pF
01 – 21 ns at 70 pF
10 – 15 ns at 70 pF
11 – 27 ns at 70 pF
3:2
1:0
Reserved
R
Reserved
HSC_ERC
RW
0
This field controls the edge rate of the DBCP/N high speed
transmitter. The value of this field will match the sampled state
of the ERC pin. Software can change the value of this field at a
later time.
00 – 200 ps at 1 Gbps. (ERC pin = VIL)
01 – 150 ps at 1 Gbps. (ERC pin = VIM
)
10 – 250 ps at 1 Gbps. (ERC pin = VIH
)
11 – 300 ps at 1 Gbps
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7.5.6 Standard CSR Register (address = 0x0B)
Figure 12. Standard CSR Register (0x0B)
7
6
5
4
3
2
1
0
HSDB3_ERC
HSDB2_ERC
RHSDB1_ERC
HSDB0_ERC
RW
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. Standard CSR Register (0x0B)
Bit
Field
Type
Reset
Description
7:6
HSDB3_ERC
RW
0
This field controls the edge rate of the DB3P/N high speed
transmitter. The value of this field will match the sampled state
of the ERC pin. Software can change the value of this field at a
later time.
00 – 200 ps at 1 Gbps. (ERC pin = VIL)
01 – 150 ps at 1 Gbps. (ERC pin = VIM
)
10 – 250 ps at 1 Gbps. (ERC pin = VIH
)
11 – 300 ps at 1 Gbps
5:4
3:2
1:0
HSDB2_ERC
RHSDB1_ERC
HSDB0_ERC
RW
RW
RW
0
0
0
This field controls the edge rate of the DB2P/N high speed
transmitter. The value of this field will match the sampled state
of the ERC pin. Software can change the value of this field at a
later time.
00 – 200 ps at 1 Gbps. (ERC pin = VIL)
01 – 150 ps at 1 Gbps. (ERC pin = VIM
)
10 – 250 ps at 1 Gbps. (ERC pin = VIH
)
11 – 300 ps at 1 Gbps
This field controls the edge rate of the DB1P/N high speed
transmitter. The value of this field will match the sampled state
of the ERC pin. Software can change the value of this field at a
later time.
00 – 200 ps at 1 Gbps. (ERC pin = VIL)
01 – 150 ps at 1 Gbps. (ERC pin = VIM
)
10 – 250 ps at 1 Gbps. (ERC pin = VIH
)
11 – 300 ps at 1 Gbps
This field controls the edge rate of the DB0P/N high speed
transmitter. The value of this field will match the sampled state
of the ERC pin. Software can change the value of this field at a
later time.
00 – 200 ps at 1 Gbps. (ERC pin = VIL)
01 – 150 ps at 1 Gbps. (ERC pin = VIM
)
10 – 250 ps at 1 Gbps. (ERC pin = VIH
)
11 – 300 ps at 1 Gbps
18
Copyright © 2016–2019, Texas Instruments Incorporated
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www.ti.com.cn
ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
7.5.7 Standard CSR Register (address = 0x0D)
Figure 13. Standard CSR Register (0x0D)
7
6
5
4
3
2
1
0
Reserved.
CDB0N_STATUS
R
CDB0P_STATUS
R
Reserved
CDA0N_STATUS
R
CDA0P_STATUS
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. Standard CSR Register (0x0D)
Bit
7:6
5
Field
Type
R
Reset
Description
Reserved.
CDB0N_STATUS
Reserved.
R
0
0
0 – Contention not detected on DB0N interface.(default)
1 – Contention detected on DB0N interface
4
CDB0P_STATUS
R
0 – Contention not detected on DB0P interface.(default)
1 – Contention detected on DB0P interface
3:2
1
Reserved
R
R
Reserved
CDA0N_STATUS
0
0
0 – Contention not detected on DA0N interface.(default)
1 – Contention detected on DA0N interface
0
CDA0P_STATUS
R
0 – Contention not detected on DA0P interface.(default)
1 – Contention detected on DA0P interface
7.5.8 Standard CSR Register (address = 0x0E)
Figure 14. Standard CSR Register (0x0E)
7
6
5
4
3
2
1
0
Reserved
HSTX_VSADJ
Reserved
HSTX_PRE
R
R
RW
RW
R
R
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. Standard CSR Register (0x0E)
Bit
7:6
5:4
Field
Type
R
Reset
Description
Reserved
HSTX_VSADJ
Reserved
RWU
0
This field controls the HS TX voltage swing level. The value of
this field will match the sampled state of the CFG[1:0] pins.
Software can change the value of this field at a later time.
00 – 180 mV
01 – 200 mV (CFG0 = VIM or (CFG0 = VIL and !CFG1 = VIH))
1X – 220mV (CFG0 = VIH or (CFG0 = VIL and CFG1 = VIH))
3:2
1:0
Reserved
R
Reserved
HSTX_PRE
RWU
0
This field controls the HS TX pre-emphasis level. The value of
this field will match the sampled state of CFG1 pin. Software can
change the value of this field at a later time.
00 – 1.5 dB
01 – 0 dB (CFG1 = VIM or VIL)
1X – 2.5 dB (CFG1 = VIH
)
Copyright © 2016–2019, Texas Instruments Incorporated
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www.ti.com.cn
7.5.9 Standard CSR Register (address = 0x10) [reset = 0xFF]
Figure 15. Standard CSR Register (0x10)
7
6
5
4
3
2
1
0
LPTXDA_ERC
RW
RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. Standard CSR Register (0x10)
Bit
Field
Type
Reset
Description
7:0
LPTXDA_ERC
RW
0xFF
This field represents the lower 8-bits of the 16-bit
BTA_TIMEOUT register. Timer is reset to default state when
BTA request is detected and is stopped when BTA is
acknowledged. If BTA is not acknowledged before this timer
expires, then DPHY440 will terminate BTA operation. This
counter operates on the LPTX clock. Defaults to 0xFF.
7.5.10 Standard CSR Register (address = 0x11) [reset = 0xFF]
Figure 16. Standard CSR Register (0x11)
7
6
5
4
3
2
1
0
BTA_TIMEOUT_HI
RW RW
RW
RW
RW
RW
RW
RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. Standard CSR Register (0x11)
Bit
Field
Type
Reset
Description
7:0
BTA_TIMEOUT_HI
RW
0xFF
This field represents the upper 8-bits of the 16-bit
BTA_TIMEOUT register. Timer is reset to default state when
BTA request is detected and is stopped when BTA is
acknowledged. If BTA is not acknowledged before this timer
expires, then DPHY440 will terminate BTA operation. This
counter operates on the LPTX clock. Defaults to 0xFF.
20
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ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information,
The DPHY440 supports up to 4 DSI DPHY lanes and a clock lane. One of the four lanes is used for back
channel communications between GPU and DSI panel. DPHY440’s lane 0 is the only lane that supports the back
channel. For this reason, DPHY440 lane 0 must always be connected to lane 0 of GPU and panel.
Other combinations, like 1 and 3 lane, examples are not shown, but are fully supported by the DPHY440. For all
DSI implementations, the polarity must be maintained between the DSI Source and DSI Sink. The DPHY440
does not support polarity inversion.
8.2 Typical Application, CSI-2 Implementations
The DPHY440 supports 4 CSI-2 DPHY lanes plus a clock. Unlike DSI, CSI-2 does not have a back channel path.
Because of this, there is no requirement on lane ordering. Because there is no lane ordering requirement, there
are more combinations which can be implemented. All possible combinations are supported by the DPHY440.
For all CSI-2 implementations, the polarity must be maintained between the CSI-2 Source and CSI-2 Sink. The
DPHY440 does not support polarity inversion.
12 inch FR-4,
10 mil
1 inch FR-4,
10 mil
SNx5D
PHY44
0SS
Camera
APU
Output
trace
Input trace
Figure 17. CSI-2 Example: Typical SNx5DPHY440SS Placement in the System
Copyright © 2016–2019, Texas Instruments Incorporated
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www.ti.com.cn
Typical Application, CSI-2 Implementations (continued)
VCC_1.8V
DPHY440SS
VCC
RSTN
100nF
VREG_OUT
APU
Camera
200nF
(CSI-2 Sink)
(CSI-2 Source)
VDD
100nF
CSI TX
CSI RX
DB0P
DB0N
DB1P
DB1N
DBCP
DBCN
DB2P
DB2N
DB3P
DB3N
DA0P
DA0N
DA1P
DA1N
DACP
DACN
DA2P
DA2N
DA3P
DA3N
CSI0P
CSI0N
CSICP
CSICN
CSI1P
CSI1N
CSI0P
CSI0N
CSICP
CSICN
CSI1P
CSI1N
Vio
2K
CSI Slave
SCL
2K
CSI Master
SDA
SCL
SDA
R3
R2
R1
R4
R6
R5
R7 R8
VCC_1.8V
Copyright © 2016, Texas Instruments Incorporated
Figure 18. CSI-2 Two Lane Example
8.2.1 Design Requirements
Typically, in CSI-2 applications, the system trace length from the Camera (Source) to the DPHY440 device is
different from that of the trace length from DPHY440 to the APU (Sink). Consequently, different pre-emphasis
and equalization settings are required on the receiver and transmitter side of the device respectively.
For this design example, refer to Figure 17 and Figure 18. Shown is a CSI-2 system implementation in which the
DPHY device is placed close to the Sink (APU). Here, the input trace length is about 12 inch while the output
trace length is just 1 inch. The input signal characteristics assumed are shown in Table 15.
Table 15. Design Parameters
PARAMETER
Data Rate (200 Mbps to 1.5 Gbps)
Input trace length
VALUE
1 Gbps
12 inch
1 inch
Output trace length
Trace width
10 mils
22
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ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
8.2.2 Detailed Design Procedure
The typical example describes how to configure the VSADJ, PRE, EQ and ERC configuration pins of the
DPHY440 device based on the board trace length between the Source (Camera) and DPHY440 and the
DPHY440 and Sink (APU). Actual configuration settings might differ due to additional factors such as board
layout, and connectors used in the signal path.
Though the data rate in this example is 1 Gbps, device is placed near to the Sink, with a short output trace of 1
inch. Consequently, the ERC pin can be configured to have a rise/fall time of 250 ps for the edge. Further, due to
the short output trace, the PRE pin must be configured to a setting of 0 dB and the VSADJ to be 200 mV. The
Application Curve in Figure 22 shows the FR-4 loss characteristics of a 10 mil wide, 12 inch long trace. From this
plot, the input signal trace suffers a loss of 1.5 dB at 500 MHz. Thus, the EQ setting can be either 0 dB or 2.5
dB. All the configuration settings and their corresponding inputs are tabulated in Table 16.
Table 16. Configuration Pin Settings
PIN
VSADJ
PRE
EQ
SETTING
200 mV
INPUT VALUE
VIM
VIM
0 dB
0 dB or 2.5 dB
250 ps
VIL or VIM
VIH
ERC
The configuration pins each have internal pull-up and pull-down resistors of 100 kΩ each. Thus, the
recommendation is an external pull-up/pull-down resistors of about 10 kΩ each, to meet the requirement of the
threshold levels for the VIL and VIH listed in the Electrical Characteristics table. The external resistors shown in
Figure 18 should be populated to produce corresponding configuration settings, according to the list given in
Table 17.
Table 17. Resistor Parameters
RESISTOR NAME
VALUE
R1
R2
R3
R4
R5
Leave unpopulated
Leave unpopulated
Leave unpopulated
Leave unpopulated
Leave unpopulated
10 kΩ (EQ = 0 dB) or
Leave unpopulated (EQ = 2.5 dB)
R6
R7
R8
10 kΩ
Leave unpopulated
Copyright © 2016–2019, Texas Instruments Incorporated
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www.ti.com.cn
8.2.2.1 Reset Implementation
The DPHY440 RSTN input gives control over the device reset and to place the device into low power mode. It is
critical to reset the digital logic of the DPHY440 after the VCC supply is stable (that is, the power supply has
reached the minimum recommended operating voltage). This is achieved by transitioning the RSTN input from a
low level to a high level. A system may provide a control signal to the RSTN signal that transitions low to high
after the power supply is (or supplies are) stable, or implement an external capacitor connected between RSTN
and GND, to allow delaying the RSTN signal during power up. Both implementations are shown in Figure 19 and
Figure 20.
VCC
GPO
RST
open drain
output
RST
REN=150 kꢀ
C
C
controller
DPHY440
DPHY440
Figure 19. External Capacitor Controlled RSTN
Figure 20. RSTN Input from Active Controller
When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of
the VCC supply, where a slower ramp-up results in a larger value external capacitor.
Refer to the latest reference schematic for the DPHY440 device and/or consider approximately 200-nF capacitor
as a reasonable first estimate for the size of the external capacitor.
When implementing an RSTN input from an active controller, it is recommended to use an open drain driver if the
RSTN input is driven. This protects the RSTN input from damage of an input voltage greater than VCC
.
td1
tsu2
RSTN
VCC
th2
CFG[1:0], EQ, ERC
Figure 21. Power-Up Timing Requirements
Table 18. Timing Requirements
DESCRIPTION(1)
MIN
MAX
tD1
VCC stable before de-assertion of RSTN.
100 µs
Setup of VSADJ_CFG0, PRE_CFG1, EQ and ERC pin before de-assertion of
RSTN.
tsu2
0
Hold of VSADJ_CFG0, PRE_CFG1, EQ and ERC pin after de-assertion of
RSTN.
th2
250 µs
0.2 ms
tVCC_RAMP
VCC supply ramp requirements
100 ms
(1) Unused DAxP/N pins shall be tied to GND.
24
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ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
8.2.3 Application Curves
0
-0.5
-1
0
-0.5
-1
-1.5
-2
-1.5
-2
-2.5
-2.5
1M
10M
100M
Frequency (Hz)
1G
1M
10M
100M
Frequency (Hz)
1G
D001
D002
12 inch long, 5 mil wide FR4 trace
Figure 22. Loss vs Frequency
12 inch long, 10 mil wide FR4 trace
Figure 23. Loss vs Frequency
9 Power Supply Recommendations
Texas Instruments recommends a 0.1-µF capacitor on each power pin.
RESETN
C2
C1
0.1uF
0.2 uF
U1
1
2
24
23
DPHYOUT_B0P
DPHYOUT_B0N
DPHYIN_A0P
DPHYIN_A0N
DA0P
DA0N
DB0P
DB0N
22
21
3
4
DPHYOUT_B1P
DPHYOUT_B1N
DPHYIN_A1P
DPHYIN_A1N
DA1P
DA1N
DB1P
DB1N
5
6
20
19
DPHYOUT_BCP
DPHYOUT_BCN
DPHYIN_ACP
DPHYIN_ACN
DACP
DACN
DBCP
DBCN
7
8
18
17
DPHYOUT_B2P
DPHYOUT_B2N
DPHYIN_A2P
DPHYIN_A2N
DA2P
DA2N
DB2P
DB2N
9
10
16
15
DPHYOUT_B3P
DPHYOUT_B3N
DPHYIN_A3P
DPHYIN_A3N
DA3P
DA3N
DB3P
DB3N
VCC_1.8 V
DPHY440SS
C3
0.1 uF
C4
0.1 uF
Copyright © 2016, Texas Instruments Incorporated
Figure 24. Supply Implementation
Copyright © 2016–2019, Texas Instruments Incorporated
25
SN65DPHY440SS, SN75DPHY440SS
ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
•
DAxP/N and DB*P/N pairs should be routed with controlled 100-Ω differential impedance (± 15%) or 50-Ω
single-ended impedance (± 15%).
•
•
•
•
•
Keep away from other high speed signals.
Keep lengths to within 5 mils of each other.
Length matching should be near the location of mismatch.
Each pair should be separated at least by 3 times the signal trace width.
The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left
and right bends should be as equal as possible and the angle of the bend should be ≥ 135 degrees. This will
minimize any length mismatch causes by the bends and; therefore, minimize the impact bends have on EMI.
•
•
•
•
•
Route all differential pairs on the same of layer.
The number of VIAS should be kept to a minimum. It is recommended to keep the VIAS count to 2 or less.
Keep traces on layers adjacent to ground plane.
Do NOT route differential pairs over any plane split.
Adding Test points will cause impedance discontinuity and will; therefore, negatively impact signal
performance. If test points are used, they should be placed in series and symmetrically. They must not be
placed in a manner that causes a stub on the differential pair.
10.2 Layout Example
Figure 25. Example Layout
26
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SN65DPHY440SS, SN75DPHY440SS
www.ti.com.cn
ZHCSES3C –MARCH 2016–REVISED AUGUST 2019
11 器件和文档支持
11.1 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
表 19. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
SN65DPHY440SS
SN75DPHY440SS
11.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016–2019, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN65DPHY440SSRHRR
SN65DPHY440SSRHRT
SN75DPHY440SSRHRR
SN75DPHY440SSRHRT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
WQFN
RHR
RHR
RHR
RHR
28
28
28
28
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
0 to 70
DPHY440
NIPDAU
NIPDAU
NIPDAU
DPHY440
DPHY440
DPHY440
0 to 70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65DPHY440SSRHRR WQFN
SN65DPHY440SSRHRT WQFN
SN75DPHY440SSRHRR WQFN
SN75DPHY440SSRHRT WQFN
RHR
RHR
RHR
RHR
28
28
28
28
3000
250
330.0
180.0
330.0
180.0
12.4
12.4
12.4
12.4
3.8
3.8
3.8
3.8
5.8
5.8
5.8
5.8
1.2
1.2
1.2
1.2
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN65DPHY440SSRHRR
SN65DPHY440SSRHRT
SN75DPHY440SSRHRR
SN75DPHY440SSRHRT
WQFN
WQFN
WQFN
WQFN
RHR
RHR
RHR
RHR
28
28
28
28
3000
250
346.0
210.0
346.0
210.0
346.0
185.0
346.0
185.0
33.0
35.0
33.0
35.0
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHR 28
3.5 x 5.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4210249/B
www.ti.com
PACKAGE OUTLINE
RHR0028A
WQFN - 0.8 mm max height
S
C
A
L
E
2
.
7
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
B
A
PIN 1 INDEX AREA
0.5
0.3
5.6
5.4
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
SEATING PLANE
0.08
0.05
0.00
2±0.1
2X 1.5
(0.2) TYP
EXPOSED
THERMAL PAD
11
14
24X 0.5
10
15
2X
4.5
4±0.1
SEE TERMINAL
DETAIL
1
24
0.3
28X
28
25
0.5
0.2
PIN 1 ID
(OPTIONAL)
0.1
C A
B
28X
0.3
0.05
4219075/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RHR0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2)
SYMM
28X (0.6)
28X (0.25)
25
28
1
24
24X (0.5)
(0.66)
(5.3)
TYP
SYMM
(4)
(
0.2) TYP
VIA
15
10
11
14
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219075/A 11/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RHR0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.55) TYP
28
25
28X (0.6)
28X (0.25)
1
24
24X (0.5)
SYMM
(1.32)
TYP
(5.3)
METAL
TYP
6X (1.12)
15
10
14
11
6X (0.89)
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4219075/A 11/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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