SN75LVDS83DGGG4 [TI]
FlatLink TRANSMITTER; FlatLink变送器
| 型号： | SN75LVDS83DGGG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | FlatLink TRANSMITTER |
| 文件： | 总21页 (文件大小：701K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Not Recommended for New Designs
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SLLS271I − MARCH 1997 − REVISED MAY 2009
DGG PACKAGE
(TOP VIEW)
D
D
4:28 Data Channel Compression at up to
238 MBytes/s Throughput
Suited for SVGA, XGA, or SXGA Display
Data Transmission From Controller to
Display With Very Low EMI
V
D4
1
56
55
54
53
52
51
50
49
48
47
46
CC
D5
D3
2
D6
D7
D2
3
D
D
D
D
D
D
28 Data Channels and Clock-In Low-Voltage
TTL
GND
D1
4
GND
D8
5
D0
6
4 Data Channels and Clock-Out
Low-Voltage Differential
D9
D27
LVDSGND
Y0M
Y0P
Y1M
7
D10
8
Operates From a Single 3.3-V Supply With
250 mW (Typ)
V
9
CC
D11
D12
10
11
ESD Protection Exceeds 6 kV
5-V Tolerant Data Inputs
45 Y1P
D13 12
GND 13
D14 14
Selectable Rising or Falling Edge-Triggered
Inputs
44 LVDSV
CC
43 LVDSGND
15
16
17
18
19
20
21
22
23
24
25
26
27
28
42
41
40
39
38
37
36
35
34
33
32
31
30
29
D15
D16
Y2M
D
Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
Y2P
CLKSEL
D17
CLKOUTM
CLKOUTP
Y3M
D
Consumes Less Than 1 mW When Disabled
D
Wide Phase-Lock Input Frequency
Range . . . 31 MHz to 68 MHz
D18
D19
Y3P
D
D
D
No External Components Required for PLL
GND
D20
LVDSGND
PLLGND
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
D21
PLLV
CC
Improved Replacement for the DS90C581
D22
PLLGND
SHTDN
CLKIN
D26
D23
description
V
CC
D24
D25
The SN75LVDS83 FlatLink transmitter contains
four 7-bit parallel-load serial-out shift registers, a
GND
7× clock synthesizer, and five low-voltage
differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of
single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over five balanced-pair conductors
for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit
links with the SN75LVDS86 receiver.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL)
terminal. The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in
7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS
output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN75LVDS83 requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The
only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock
and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN clears all
internal registers to a low level.
The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0_C to 70_C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink is a registered trademark of Texas Instruments.
ꢖꢑ ꢗ ꢆꢘ ꢙ ꢐꢔ ꢗ ꢁ ꢆ ꢒꢐꢒ ꢍꢎ ꢚ ꢛꢜ ꢝꢋ ꢌꢍꢛ ꢎ ꢍꢞ ꢟꢠ ꢜ ꢜ ꢡꢎꢌ ꢋꢞ ꢛꢚ ꢢꢠꢣ ꢊꢍꢟ ꢋꢌ ꢍꢛꢎ ꢤꢋ ꢌꢡ ꢥ
ꢖꢜ ꢛ ꢤꢠꢟ ꢌ ꢞ ꢟ ꢛꢎ ꢚꢛ ꢜ ꢝ ꢌ ꢛ ꢞ ꢢꢡ ꢟ ꢍꢚ ꢍꢟꢋ ꢌꢍ ꢛꢎꢞ ꢢꢡ ꢜ ꢌꢦ ꢡ ꢌꢡ ꢜ ꢝꢞ ꢛꢚ ꢐꢡꢧ ꢋꢞ ꢔꢎꢞ ꢌꢜ ꢠꢝ ꢡꢎꢌ ꢞ
ꢞ ꢌ ꢋ ꢎꢤ ꢋ ꢜꢤ ꢨ ꢋ ꢜꢜ ꢋ ꢎ ꢌꢩꢥ ꢖꢜ ꢛ ꢤꢠꢟ ꢌꢍꢛꢎ ꢢꢜ ꢛꢟ ꢡꢞ ꢞꢍ ꢎꢪ ꢤꢛꢡ ꢞ ꢎꢛꢌ ꢎꢡ ꢟꢡ ꢞꢞ ꢋꢜ ꢍꢊ ꢩ ꢍꢎꢟ ꢊꢠꢤ ꢡ
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Copyright 1997 − 2009, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Not Recommended for New Designs
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SLLS271I − MARCH 1997 − REVISED MAY 2009
functional block diagram
Parallel-Load 7-Bit
Shift Register
7
Y0P
Y0M
D0, D1, D2, D3,
D4, D6, D7
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
7
7
D8, D9, D12, D13,
D14, D15, D18
Y1P
Y1M
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
D19, D20, D21, D22,
D24, D25, D26
Y2P
Y2M
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
D27, D5, D10, D11,
D16, D17, D23
Y3P
Y3M
A,B, ...G
SHIFT/LOAD
CLK
Control Logic
SHTDN
7× Clock/PLL
7×CLK
CLKOUTP
CLKOUTM
CLK
CLKIN
CLKINH
RISING/FALLING EDGE
CLKSEL
2
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Not Recommended for New Designs
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SLLS271I − MARCH 1997 − REVISED MAY 2009
D0
CLKIN
or
CLKIN
CLKOUT
Next
Cycle
Previous Cycle
Current Cycle
D0−1
D8−1
D7
D6
D4
D3
D2
D1
D9
D0
D8
D7+1
Y0
Y1
D18
D15
D14
D13
D12
D18+1
D19−1
D27−1
D26
D23
D25
D17
D24
D16
D22
D11
D21
D10
D20
D5
D19
D27
D26+1
D23+1
Y2
Y3
Figure 1. SN75LVDS83 Load and Shift Timing Sequences
equivalent input and output schematic diagrams
V
CC
V
CC
5 Ω
YnP or YnM
10 kΩ
Dn or
SHTDN
50 Ω
7 V
7 V
300 kΩ
INPUT
OUTPUT
3
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Not Recommended for New Designs
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SLLS271I − MARCH 1997 − REVISED MAY 2009
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V
CC
Output voltage range, V (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input voltage range, V (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V
I
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
DISSIPATION RATING TABLE
≤ 25°C DERATING FACTOR
‡
T
T = 70°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
DGG
1377 mW
11.0 mW/°C
822 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board mounted and
with no air flow.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
CC
3
2
3.3
3.6
High-level input voltage, V
IH
V
Low-level input voltage, V
IL
0.8
132
70
V
Differential load impedance, Z
90
0
Ω
L
Operating free-air temperature, T
°C
A
timing requirements
MIN NOM
MAX
UNIT
ns
t
t
t
t
t
Cycle time, input clock
14.7
32.3
c
Pulse duration, high-level input clock
0.4t
0.6t
c
ns
w
t
c
Transition time, input signal
5
ns
Setup time, data, D0 − D27 valid before CLKIN↑ or CLKIN↓ (see Figure 2)
Hold time, data, D0 − D27 valid after CLKIN↑ or CLKIN↓ (see Figure 2)
3
ns
su
h
1.5
ns
4
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SLLS271I − MARCH 1997 − REVISED MAY 2009
electrical characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
Input threshold voltage
1.4
IT
|V
|
Differential steady-state output voltage magnitude
247
454
50
mV
OD
R
= 100 Ω, See Figure 3
Change in the steady-state differential output
voltage magnitude between opposite binary states
L
∆|V
|
mV
OD
V
V
Steady-state common-mode output voltage
Peak-to-peak common-mode output voltage
High-level input current
1.125
1.375
150
25
V
OC(SS)
See Figure 3
mV
µA
µA
mA
mA
µA
µA
OC(PP)
I
I
V
V
V
V
V
= V
= 0
IH
IH
CC
Low-level input current
10
IL
IL
= 0
24
O(Yn)
I
Short-circuit output current
OS
OZ
= 0
OD
= 0 to V
12
I
High-impedance state output current
10
O
CC
Disabled,
All inputs at GND
= 100 Ω,
280
Enabled,
R
L
Gray-scale pattern (see Figure 4),
= 3.3 V, = 15.38 ns
72
90
mA
V
t
c
I
Quiescent supply current
Input capacitance
CC
Enabled,
Worst-case pattern (see Figure 5),
CC
R
= 100 Ω,
L
85
3
110
mA
pF
t = 15.38 ns
c
C
I
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
5
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Not Recommended for New Designs
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SLLS271I − MARCH 1997 − REVISED MAY 2009
switching characteristics over recommended operating conditions (unless otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
t
t
Delay time, CLKOUT↑ to serial bit position 0
−0.2
0
0.2
ns
d0
1
7
1
7
Delay time, CLKOUT↑ to serial bit position 1
Delay time, CLKOUT↑ to serial bit position 2
Delay time, CLKOUT↑ to serial bit position 3
Delay time, CLKOUT↑ to serial bit position 4
ns
ns
ns
ns
t
t
t
t
* 0.2
t
t
t
t
t
) 0.2
) 0.2
) 0.2
) 0.2
) 0.2
d1
c
c
c
c
c
c
c
c
c
2
7
2
7
t
d2
t
d3
t
d4
* 0.2
* 0.2
* 0.2
3
7
3
7
t = 15.38 ns ( 0.2%),
|Input clock jitter| < 50 ps , See Figure 6
c
‡
4
7
4
7
5
7
5
7
t
d5
Delay time, CLKOUT↑ to serial bit position 5
ns
t
t
* 0.2
c
c
6
7
6
7
t
t
Delay time, CLKOUT↑ to serial bit position 6
ns
ns
* 0.2
t
) 0.2
d6
c
n
7
−0.2
0.2
Output skew,
t
*
t
c
sk(o)
n
t = 18.51 ns ( 0.2%),
|Input clock jitter| < 50 ps , See Figure 6
c
t
Delay time, CLKIN↓ to CLKOUT↑
3.75
5.6
7.75
ns
ps
ps
d7
‡
t = 15.38 0.75 sin (2π500E3t) + 0.05 ns,
c
70
See Figure 7
§
∆t
Cycle time, output clock jitter
c(o)
t = 15.38 0.75 sin (2π3E6t) + 0.05 ns,
c
187
See Figure 7
4
7
t
t
Pulse duration, high-level output clock
ns
ps
c
w
t
t
Transition time, differential output (t or t )
See Figure 3
See Figure 8
260
700
1
1500
r
f
Enable time, SHTDN↑ to phase lock (Yn
valid)
t
en
ms
Disable time, SHTDN↓ to off state
(CLKOUT low)
t
See Figure 9
250
ns
dis
†
‡
§
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
|Input clock jitter| is the magnitude of the change in the input clock period.
Output clock jitter is the change in the output clock period from one cycle to the next cycle observed over 15000 cycles.
6
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SLLS271I − MARCH 1997 − REVISED MAY 2009
PARAMETER MEASUREMENT INFORMATION
t
su
t
h
Dn
CLKSEL LOW
CLKSEL HIGH
CLKIN
NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns.
Figure 2. Setup and Hold Time Waveforms
49.9 Ω 1% (2 Places)
YP
V
OD
V
OC
YM
C
= 10 pF Max
L
(2 Places)
NOTE A: The lumped instrumentation capacitance for any
single-ended voltage measurement is less than or equal
to 10 pF. When making measurements at YP or YM, the
complementary output is similarly loaded.
(a) SCHEMATIC
100%
80%
V
OD(H)
0 V
V
OD(L)
20%
0%
t
f
t
r
V
OC(PP)
V
V
OC(SS)
OC(SS)
0 V
(b) WAVEFORMS
Figure 3. Test Load and Voltage Waveforms for LVDS Outputs
7
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SLLS271I − MARCH 1997 − REVISED MAY 2009
PARAMETER MEASUREMENT INFORMATION
CLKIN
D0, 8, 16
D1, 9, 17
D2, 10, 18
D3, 11, 19
D4−7, 12−15, 20−23
D24−27
NOTE A: The 16-grayscale test-pattern test device power consumption for a typical display pattern. Pattern with CLKSEL low shown.
Figure 4. 16-Grayscale Test-Pattern Waveforms
t
c
CLKIN
Even Dn
Odd Dn
NOTE A: The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Pattern with
CLKSEL low shown.
Figure 5. Worst-Case Test-Pattern Waveforms
8
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SLLS271I − MARCH 1997 − REVISED MAY 2009
PARAMETER MEASUREMENT INFORMATION
t
d7
CLKIN
(see Note A)
CLKIN
(see Note B)
CLKOUT
t
d0
Yn
t
d1
t
d2
t
d3
t
d4
t
d5
t
d6
≈ 2.5 V
1.4 V
V
OD(H)
CLKOUT
CLKIN
or
0.00 V
Yn
≈ 0.5 V
V
OD(L)
t
d7
t
− t
d0 d6
NOTES: A. This wave form is valid when CLKSEL is low.
B. This wave form is valid when CLKSEL is high.
Figure 6. SN75LVDS83 Timing Waveforms
9
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SLLS271I − MARCH 1997 − REVISED MAY 2009
PARAMETER MEASUREMENT INFORMATION
Device
Under
Test
+
Reference
VCO
∑
+
Modulation
V(t) = A sin (2 π f
t)
(mod)
HP8656B
Signal Generator
0.1 MHz − 990 MHz
HP8665A
Synthesized Signal
Generator
Device Under Test
DTS2070C
Digital Time Scope
0.1 MHz − 4200 MHz
OUTPUT
CLKIN
CLKOUT
Input
RF Output
Modulation Input
Figure 7. Output Clock Jitter Testing
CLKIN
Dn
t
en
SHTDN
Yn
Invalid
Valid
Figure 8. Enable Time Waveforms
CLKIN
t
dis
SHTDN
CLKOUT
Figure 9. Disable Time Waveforms
10
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SLLS271I − MARCH 1997 − REVISED MAY 2009
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
vs
CLOCK FREQUENCY
80
V
CC
= 3.6 V
70
60
50
V
CC
= 3.3 V
V
CC
= 3 V
40
30
Grayscale Data Pattern
R
= 100 Ω
= 25°C
L
T
A
30
40
50
60
70
f
− Clock Frequency − MHz
clk
Figure 10
ZERO-TO-PEAK OUTPUT JITTER
vs
MODULATION FREQUENCY
200
180
160
140
120
100
80
60
40
Input jitter = 750 sin (6.28 f
t) ps
(mod)
V
T
A
= 3.3 V
= 25°C
20
0
CC
0
0.5
1
1.5
2
2.5
3
f
− Modulation Frequency − MHz
(mod)
Figure 11
11
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SLLS271I − MARCH 1997 − REVISED MAY 2009
APPLICATION INFORMATION
Host
Cable
Flat Panel Display
Graphic Controller
SN75LVDS83
SN75LVDS82
12-BIT
RED0
RED1
RED2
RED3
RSVD
RSVD
NA
18-BIT
RED0
RED1
RED2
RED3
RED4
RED5
NA
24-BIT
RED0
RED1
RED2
RED3
RED4
RED5
RED6
RED7
48
9
51
52
54
55
56
3
D0
Y0M
A0M
D1
100 Ω
100 Ω
100 Ω
100 Ω
D2
47
46
10
11
D3
Y0P
Y1M
A0P
A1M
D4
D6
50
2
D27
D5
NA
NA
4
GREEN0 GREEN0 GREEN0
GREEN1 GREEN1 GREEN1
GREEN2 GREEN2 GREEN2
GREEN3 GREEN3 GREEN3
D7
6
45
42
12
15
D8
Y1P
Y2M
A1P
A2M
7
D9
11
12
14
8
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
CLKSEL
RSVD
RSVD
NA
GREEN4 GREEN4
GREEN5 GREEN5
NA
GREEN6
GREEN7
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
BLUE6
BLUE7
10
15
19
20
22
23
24
16
18
27
28
30
25
31
17
41
38
16
19
NA
NA
Y2P
Y3M
A2P
A3M
BLUE0
BLUE1
BLUE2
BLUE3
RSVD
RSVD
NA
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
NA
37
20
Y3P
A3P
NA
NA
H_SYNC H_SYNC H_SYNC
V_SYNC V_SYNC V_SYNC
ENABLE ENABLE ENABLE
40
39
17
18
CLKOUTM
CLKOUTP
CLKINM
CLKINP
NA
NA
RSVD
100 Ω
CLOCK
CLOCK
CLOCK
See Note A
NOTES: A. Connect this terminal to V
CC
for triggering to the rising edge of the input clock and to GND for the falling edge.
B. The five 100-Ω terminating resistors are recommended to be 0603 types.
Figure 12. 24-Bit Color Host To 24-Bit LCD Panel Display Application
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Not Recommended for New Designs
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢀ ꢇꢈ
ꢐ ꢑꢒꢁ ꢀꢓ ꢔ ꢐꢐ ꢕꢑ
ꢉ
ꢊ
ꢋ
ꢌ
ꢄ
ꢍ
ꢎ
ꢏ
SLLS271I − MARCH 1997 − REVISED MAY 2009
APPLICATION INFORMATION
Host
Cable
Flat Panel Display
SN75LVDS86
Graphic Controller
SN75LVDS83
12-BIT
18-BIT
RED0
RED1
RED2
RED3
RED4
RED5
NA
24-BIT
48
8
51
52
54
55
56
3
RED0
RED1
RED2
RED3
RSVD
RSVD
NA
RED0
RED1
RED2
RED3
RED4
RED5
RED6
RED7
D0
Y0M
A0M
D1
100 Ω
D2
47
46
9
D3
Y0P
Y1M
A0P
D4
D6
10
50
2
D27
D5
A1M
NA
NA
4
100 Ω
GREEN0 GREEN0 GREEN0
GREEN1 GREEN1 GREEN1
GREEN2 GREEN2 GREEN2
GREEN3 GREEN3 GREEN3
D7
6
45
42
11
D8
Y1P
Y2M
A1P
7
D9
11
12
14
8
D12
D13
D14
D10
D11
D15
D18
D19
D20
D21
D22
D16
D17
D24
D25
D26
D23
CLKIN
CLKSEL
14
RSVD
RSVD
NA
GREEN4 GREEN4
GREEN5 GREEN5
A2M
100 Ω
NA
GREEN6
GREEN7
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
BLUE6
BLUE7
10
15
19
20
22
23
24
16
18
27
28
30
25
31
17
41
38
15
NA
NA
Y2P
Y3M
A2P
BLUE0
BLUE1
BLUE2
BLUE3
RSVD
RSVD
NA
BLUE0
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
NA
37
Y3P
NA
NA
H_SYNC H_SYNC H_SYNC
V_SYNC V_SYNC V_SYNC
ENABLE ENABLE ENABLE
40
39
16
CLKOUTM
CLKOUTP
CLKINM
NA
NA
RSVD
100 Ω
CLOCK
CLOCK
CLOCK
17
See Note A
CLKINP
NOTES: A. Connect this terminal to V
CC
for triggering to the rising edge of the input clock and to GND for the falling edge.
B. The four 100-Ω terminating resistors are recommended to be 0603 types.
Figure 13. 24-Bit Color Host To 18-Bit LCD Panel Display Application
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2013
PACKAGING INFORMATION
Orderable Device
SN75LVDS83DGG
SN75LVDS83DGGG4
SN75LVDS83DGGR
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
NRND
TSSOP
TSSOP
TSSOP
DGG
56
56
56
35
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
SN75LVDS83
NRND
NRND
DGG
DGG
35
Green (RoHS
& no Sb/Br)
0 to 70
SN75LVDS83
SN75LVDS83
2000
Green (RoHS
& no Sb/Br)
0 to 70
SN75LVDS83DGGR-P
SN75LVDS83DGGRG4
NRND
NRND
TSSOP
TSSOP
DGG
DGG
56
56
TBD
Call TI
Call TI
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
SN75LVDS83
SN75LVDS83ZQL
SN75LVDS83ZQLR
NRND
NRND
BGA
MICROSTAR
JUNIOR
ZQL
ZQL
56
52
TBD
Call TI
Call TI
Call TI
Call TI
-10 to 70
BGA
TBD
-10 to 70
MICROSTAR
JUNIOR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN75LVDS83DGGR
TSSOP
DGG
56
2000
330.0
24.4
8.6
15.6
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 56
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
SN75LVDS83DGGR
2000
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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