SNJ54ABT18502HV [TI]
具有 18 位寄存总线收发器的扫描测试设备 | HV | 68 | -55 to 125;
| 型号： | SNJ54ABT18502HV |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 18 位寄存总线收发器的扫描测试设备 | HV | 68 | -55 to 125 驱动 信息通信管理 测试 输出元件 逻辑集成电路 触发器 总线驱动器 总线收发器 |
| 文件： | 总29页 (文件大小：409K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
• Member of the Texas Instruments SCOPE
• SCOPE Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions, Optional INTEST, CLAMP,
and HIGHZ
Family of Testability Products
• Member of the Texas Instruments
Widebus Family
– Parallel-Signature Analysis at Inputs With
Masking Option
– Pseudo-Random Pattern Generation
From Outputs
• Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
• UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
• Two Boundary-Scan Cells per I/O for
• Packaged in 68-Pin Ceramic Quad Flat
Package Using 25-mil Center-to-Center
Spacings
Greater Flexibility
• State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
SN54ABT18502 . . . HV PACKAGE
(TOP VIEW)
9
8
7
6
5
4
3
2 1 68 67 66 65 64 63 62 61
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60 1B4
59 1B5
58 1B6
57 GND
56 1B7
55 1B8
54 1B9
53
V
CC
52 NC
51 2B1
50 2B2
49 2B3
48 2B4
47 GND
46 2B5
45 2B6
44 2B7
V
CC
2A1
2A2
2A3
GND
2A4
2A5
2A6
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC – No internal connection
SCOPE, Widebus, UBT, and EPIC-IIB are trademarks of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
4–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
description
TheSN54ABT18502scantestdevicewith18-bituniversalbustransceiverisamemberoftheTexasInstruments
SCOPE testability integrated circuit family. This family of devices supports IEEE Standard 1149.1-1990
boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is
accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, this device is an 18-bit universal bus transceiver that combines D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. It can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP
in the normal mode does not affect the functional operation of the SCOPE universal bus transceiver.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.
Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the
B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is
similar to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data
output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Additional flexibility is provided in the test mode through the use of two boundary-scan cells (BSCs) for each
I/O pin. This allows independent test data to be captured and forced at either bus (A or B). A PSA/COUNT
instruction also is included to ease the testing of memories and other circuits where a binary count addressing
scheme is useful.
The SN54ABT18502 is characterized for operation over the full military temperature range of –55°C to 125°C.
†
FUNCTION TABLE
(normal mode, each register)
INPUTS
OUTPUT
B
LEAB
CLKAB
A
X
L
OEAB
‡
B
0
L
L
L
L
L
H
L
L
L
↑
L
H
L
L
↑
H
L
H
H
X
X
X
X
H
X
H
Z
†
‡
A-to-B data flow is shown. B-to-A data flow is similar
but uses OEBA, LEBA, and CLKBA.
Output level before the indicated steady-state input
conditions were established.
4–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
functional block diagram
Boundary-Scan Register
5
1LEAB
4
1CLKAB
7
1OEAB
66
1LEBA
67
1CLKBA
65
1OEBA
C1
1D
C1
1D
8
63
1A1
1B1
C1
1D
C1
1D
One of Nine Channels
32
2LEAB
33
2CLKAB
31
2OEAB
39
2LEBA
38
2CLKBA
41
2OEBA
C1
1D
C1
1D
20
51
2A1
2B1
C1
1D
C1
1D
One of Nine Channels
Bypass Register
Boundary-Control
Register
Identification
Register
V
3
CC
TDO
Instruction
Register
34
TDI
V
CC
68
TMS
TCK
TAP
Controller
37
4–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
Terminal Functions
TERMINAL
NAME
DESCRIPTION
GND
Ground
Test clock. One of four pins required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to
TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.
TCK
Test data input. One of four pins required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting data through
the instruction register or selected data register. An internal pullup forces TDI to a high level if left unconnected.
TDI
TDO
TMS
Test data output. One of four pins required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting data
through the instruction register or selected data register.
Test mode select. One of four pins required by IEEE Standard 1149.1-1990. TMS directs the device through its TAP
controller states. An internal pullup forces TMS to a high level if left unconnected.
V
CC
Supply voltage
1A1–1A9,
2A1–2A9
Normal-function A-bus I/O ports. See function table for normal-mode logic.
1B1–1B9,
2B1–2B9
Normal-function B-bus I/O ports. See function table for normal-mode logic.
Normal-function clock inputs. See function table for normal-mode logic.
Normal-function latch enables. See function table for normal-mode logic.
Normal-function output enables. See function table for normal-mode logic.
1CLKAB, 1CLKBA,
2CLKAB, 2CLKBA
1LEAB, 1LEBA,
2LEAB, 2LEBA
1OEAB, 1OEBA,
2OEAB, 2OEBA
4–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Standard
1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, namely TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.
The TAP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK, and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram illustrates the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the TAP controller, and the test registers. As illustrated,
the device contains an 8-bit instruction register and four test-data registers: an 84-bit boundary-scan register,
a 21-bit boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.
Test-Logic-Reset
TMS = H
TMS = L
TMS = H
TMS = H
TMS = H
Run-Test/Idle
Select-DR-Scan
TMS = L
Select-IR-Scan
TMS = L
TMS = L
TMS = H
TMS = H
Capture-DR
TMS = L
Capture-IR
TMS = L
Shift-DR
Shift-IR
TMS = L
TMS = L
TMS = H
TMS = H
TMS = H
Exit1-IR
TMS = H
Exit1-DR
TMS = L
TMS = L
Pause-DR
TMS = H
Pause-IR
TMS = H
Exit2-IR
TMS = L
TMS = L
TMS = L
TMS = L
Exit2-DR
TMS = H
TMS = H
Update-DR
Update-IR
TMS = H
TMS = L
TMS = H
TMS = L
Figure 1. TAP-Controller State Diagram
4–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
state diagram description
TheTAPcontrollerisasynchronousfinitestatemachinethatprovidestestcontrolsignalsthroughoutthedevice.
The state diagram is illustrated in Figure 1 and is in accordance with IEEE Standard 1149.1-1990. The TAP
controller proceeds through its states based on the level of TMS at the rising edge of TCK.
As illustrated, the TAP controller consists of 16 states. There are six stable states (indicated by a looping arrow
in the state diagram) and ten unstable states. A stable state is a state the TAP controller can retain for
consecutive TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the Test-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYPASS instruction. Certain data
registers may also be reset to their power-up values.
The state machine is constructed such that the TAP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. The TMS pin has an internal pullup resistor that forces it high if left
unconnected or if a board defect causes it to be open circuited.
For the SN54ABT18502, the instruction register is reset to the binary value 10000001, which selects the
IDCODE instruction. Bits 83–80 in the boundary-scan register are reset to logic 1, ensuring that these cells,
which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked, the outputs
would be at high impedance state). Reset values of other bits in the boundary-scan register should be
consideredindeterminate. Theboundary-controlregisterisresettothebinaryvalue000000000000000000010,
which selects the PSA test operation with no input masking.
Run-Test/Idle
The TAP controller must pass through the Run-Test/Idle state (from Test-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic may be actively running a test or can be idle.
The test operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the TAP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK upon which the TAP controller exits the Capture-DR
state.
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO and, on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least significant bit of the selected data register.
4–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
Shift-DR (continued)
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the TAP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-DR state.
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register.
On the first falling edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance
state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely. The Pause-DR state suspends and resumes data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, such update occurs
on the falling edge of TCK following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In the
Capture-IR state, the instruction register captures its current status value. This capture operation occurs on the
rising edge of TCK upon which the TAP controller exits the Capture-IR state.
For the SN54ABT18502, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO and,
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK upon which the TAP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register.
On the first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance
state.
Pause-IR
NospecificfunctionisperformedinthestablePause-IRstate, inwhichtheTAPcontrollercanremainindefinitely.
The Pause-IR state suspends and resumes instruction-register scan operations without loss of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK following entry to the Update-IR
state.
4–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
register overview
With the exception of the bypass and device-identification registers, any test register can be thought of as a
serial-shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that
they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,
Capture-DR for data registers), the shift register may be parallel loaded from a source specified by the current
instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted
out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or
Update-DR), the shadow latches are updated from the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
itsnormallogicfunction, ortestmode, inwhichthenormallogicfunctionisinhibitedoraltered), thetestoperation
to be performed, which of the four data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.
Table 4 lists the instructions supported by the SN54ABT18502. The even-parity feature specified for SCOPE
devices is supported in this device. Bit 7 of the instruction opcode is the parity bit. Any instructions that are
defined for SCOPE devices but are not supported by this device default to BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 10000001, which selects the IDCODE instruction. The IR order of scan is illustrated in Figure 2.
Bit 7
Parity
(MSB)
Bit 0
(LSB)
TDI
TDO
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Figure 2. Instruction Register Order of Scan
4–8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
data register description
boundary-scan register
The boundary-scan register (BSR) is 84 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin and two BSCs for each normal-function I/O pin (one for input data and one for output
data). The BSR is used 1) to store test data that is to be applied internally to the inputs of the normal on-chip
logic and/or externally to the device output pins, and/or 2) to capture data that appears internally at the outputs
of the normal on-chip logic and/or externally at the device input pins.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or
in Test-Logic-Reset, BSCs 83–80 are reset to logic 1, ensuring that these cells, which control A-port and B-port
outputs are set to benign values (i.e., if test mode were invoked, the outputs would be at high impedance state).
Rest values of other BSCs should be considered indeterminate.
The BSR order of scan is from TDI through bits 83–0 to TDO. Table 1 shows the BSR bits and their associated
device pin signals.
Table 1. Boundary-Scan-Register Configuration
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
83
82
81
80
79
78
77
76
75
74
73
72
––
––
––
––
––
––
2OEAB
1OEAB
2OEBA
1OEBA
2CLKAB
1CLKAB
2CLKBA
1CLKBA
2LEAB
1LEAB
2LEBA
1LEBA
––
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
2A9-I
2A8-I
2A7-I
2A6-I
2A5-I
2A4-I
2A3-I
2A2-I
2A1-I
1A9-I
1A8-I
1A7-I
1A6-I
1A5-I
1A4-I
1A3-I
1A2-I
1A1-I
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
2A9-O
2A8-O
2A7-O
2A6-O
2A5-O
2A4-O
2A3-O
2A2-O
2A1-O
1A9-O
1A8-O
1A7-O
1A6-O
1A5-O
1A4-O
1A3-O
1A2-O
1A1-O
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
2B9-I
2B8-I
2B7-I
2B6-I
2B5-I
2B4-I
2B3-I
2B2-I
2B1-I
1B9-I
1B8-I
1B7-I
1B6-I
1B5-I
1B4-I
1B3-I
1B2-I
1B1-I
17
16
15
14
13
12
11
10
9
2B9-O
2B8-O
2B7-O
2B6-O
2B5-O
2B4-O
2B3-O
2B2-O
2B1-O
1B9-O
1B8-O
1B7-O
1B6-O
1B5-O
1B4-O
1B3-O
1B2-O
1B1-O
8
7
6
5
––
4
––
3
––
2
––
1
––
0
4–9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
boundary-control register
The boundary-control register (BCR) is 21 bits long. The BCR is used in the context of the RUNT instruction to
implement additional test operations not included in thebasicSCOPE instruction set. Such operations include
PRPG, PSA with input masking, and binary count up (COUNT). Table 5 shows the test operations that are
decoded by the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
resettothebinaryvalue000000000000000000010, whichselectsthePSAtestoperationwithnoinputmasking.
The BCR order of scan is from TDI through bits 20–0 to TDO. Table 2 shows the BCR bits and their associated
test control signals.
Table 2. Boundary-Control-Register Configuration
TEST
CONTROL
SIGNAL
TEST
CONTROL
SIGNAL
TEST
CONTROL
SIGNAL
BCR BIT
NUMBER
BCR BIT
NUMBER
BCR BIT
NUMBER
20
19
18
17
16
15
14
13
12
MASK2.9
MASK2.8
MASK2.7
MASK2.6
MASK2.5
MASK2.4
MASK2.3
MASK2.2
MASK2.1
11
10
9
MASK1.9
MASK1.8
MASK1.7
MASK1.6
MASK1.5
MASK1.4
MASK1.3
MASK1.2
MASK1.1
2
OPCODE2
1
OPCODE1
0
OPCODE0
8
––
––
––
––
––
––
––
––
––
––
––
––
7
6
5
4
3
bypass register
The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
thereby reducing the number of bits per test pattern that must be applied to complete a test operation. During
Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is illustrated in
Figure 3.
TDI
TDO
Bit 0
Figure 3. Bypass Register Order of Scan
4–10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
device-identification register
The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer,
part number, and version of this device.
During Capture-DR, the binary value 00000000000000000110000000101111 (0000602F, hex) is captured in
the IDR to identify this device as Texas Instruments SN54ABT18502. The IDR order of scan is from TDI through
bits 31–0 to TDO. Table 3 shows the IDR bits and their significance.
Table 3. Device-Identification-Register Configuration
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
IDR BIT
NUMBER
IDENTIFICATION
SIGNIFICANCE
†
†
†
†
†
†
†
†
†
†
†
31
30
29
28
––
––
––
––
––
––
––
––
––
––
––
––
VERSION3
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
PARTNUMBER15
PARTNUMBER14
PARTNUMBER13
PARTNUMBER12
PARTNUMBER11
PARTNUMBER10
PARTNUMBER09
PARTNUMBER08
PARTNUMBER07
PARTNUMBER06
PARTNUMBER05
PARTNUMBER04
PARTNUMBER03
PARTNUMBER02
PARTNUMBER01
PARTNUMBER00
11
10
9
MANUFACTURER10
MANUFACTURER09
MANUFACTURER08
MANUFACTURER07
MANUFACTURER06
MANUFACTURER05
MANUFACTURER04
MANUFACTURER03
MANUFACTURER02
MANUFACTURER01
MANUFACTURER00
VERSION2
VERSION1
VERSION0
8
––
––
––
––
––
––
––
––
––
––
––
––
7
6
5
4
3
2
1
†
0
LOGIC1
––
––
––
––
––
––
––
––
†
Note that for TI products, bits 11–0 of the device-identification register always contain the binary value 000000101111
(02F, hex).
4–11
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instruction-register opcode description
The instruction-register opcodes are shown in Table 4. The following descriptions detail the operation of each
instruction.
Table 4. Instruction-Register Opcodes
†
BINARY CODE
BIT 7 → BIT 0
MSB → LSB
SELECTED DATA
REGISTER
SCOPE OPCODE
DESCRIPTION
MODE
00000000
10000001
10000010
00000011
10000100
00000101
00000110
10000111
10001000
00001001
00001010
10001011
00001100
10001101
10001110
00001111
All others
EXTEST
IDCODE
Boundary scan
Identification read
Boundary scan
Device identification
Boundary scan
Boundary scan
Bypass
Test
Normal
Normal
Test
SAMPLE/PRELOAD
INTEST
Sample boundary
Boundary scan
‡
BYPASS
BYPASS
HIGHZ
Bypass scan
Normal
Normal
Modified test
Test
‡
Bypass scan
Bypass
Control boundary to high impedance
Control boundary to 1/0
Bypass scan
Bypass
CLAMP
Bypass
‡
BYPASS
Bypass
Normal
Test
RUNT
Boundary run test
Bypass
READBN
READBT
CELLTST
TOPHIP
SCANCN
SCANCT
BYPASS
Boundary read
Boundary scan
Boundary scan
Boundary scan
Bypass
Normal
Test
Boundary read
Boundary self test
Normal
Test
Boundary toggle outputs
Boundary-control register scan
Boundary-control register scan
Bypass scan
Boundary control
Boundary control
Bypass
Normal
Test
Normal
†
‡
Bit 7 is used to maintain even parity in the 8-bit instruction.
The BYPASS instruction is executed in lieu of a SCOPE instruction that is not supported in the SN54ABT18502.
boundary scan
This instruction conforms to the IEEE Standard 1149.1-1990 EXTEST and INTEST instructions. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. Data scanned into the input
BSCs is applied to the inputs of the normal on-chip logic, while data scanned into the output BSCs is applied
to the device output pins. The device operates in the test mode.
bypass scan
This instruction conforms to the IEEE Standard 1149.1-1990 BYPASS instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in the normal mode.
sample boundary
This instruction conforms to the IEEE Standard 1149.1-1990 SAMPLE/PRELOAD instruction. The BSR is
selected in the scan path. Data appearing at the device input pins is captured in the input BSCs, while data
appearing at the outputs of the normal on-chip logic is captured in the output BSCs. The device operates in the
normal mode.
4–12
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control boundary to high impedance
This instruction conforms to the IEEE Standard 1149.1a-1993 HIGHZ instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device
operates in a modified test mode in which all device I/O pins are placed in the high-impedance state, the device
input pins remain operational, and the normal on-chip logic function is performed.
control boundary to 1/0
This instruction conforms to the IEEE Standard 1149.1a-1993 CLAMP instruction. The bypass register is
selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. Data in the input
BSCs is applied to the inputs of the normal on-chip logic, while data in the output BSCs is applied to the device
output pins. The device operates in the test mode.
boundary-run test
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. The device operates in the test mode. The test operation specified in the BCR is executed during
Run-Test/Idle. The five test operations decoded by the BCR are: sample inputs/toggle outputs (TOPSIP),
PRPG, PSA, simultaneous PSA and PRPG (PSA/PRPG), and simultaneous PSA and binary count up
(PSA/COUNT).
boundary read
The BSR is selected in the scan path. The value in the BSR remains unchanged during Capture-DR. This
instruction is useful for inspecting data after a PSA operation.
boundary self test
The BSR is selected in the scan path. All BSCs capture the inverse of their current values during Capture-DR.
In this way, the contents of the shadow latches can be read out to verify the integrity of both shift-register and
shadow-latch elements of the BSR. The device operates in the normal mode.
boundary toggle outputs
The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during
Capture-DR. Data in the shift-register elements of the selected output BSCs is toggled on each rising edge of
TCK in Run-Test/Idle, updated in the shadow latches, and applied to the associated device output pins on each
falling edge of TCK in Run-Test/Idle. Data in the selected input BSCs remains constant and is applied to the
inputs of the normal on-chip logic. Data appearing at the device input pins is not captured in the input BSCs.
The device operates in the test mode.
boundary-control-register scan
The BCR is selected in the scan path. The value in the BCR remains unchanged during Capture-DR. This
operation must be performed before a boundary-run test operation to specify which test operation is to be
executed.
4–13
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boundary-control-register opcode description
The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 5. The selected test operation is
performed while the RUNT instruction is executed in the Run-Test/Idle state. The following descriptions detail
the operation of each BCR instruction and illustrate the associated PSA and PRPG algorithms.
Table 5. Boundary-Control-Register Opcodes
BINARY CODE
BIT 2 → BIT 0
MSB → LSB
DESCRIPTION
X00
X01
X10
011
111
Sample inputs/toggle outputs (TOPSIP)
Pseudo-random pattern generation/36-bit mode (PRPG)
Parallel-signature analysis/36-bit mode (PSA)
Simultaneous PSA and PRPG/18-bit mode (PSA/PRPG)
Simultaneous PSA and binary count up/18-bit mode (PSA/COUNT)
While the control input BSCs (bits 83–72) are not included in the toggle, PSA, PRPG, or COUNT algorithms,
the output-enable BSCs (bits 83–80 of the BSR) control the drive state (active or high impedance) of the
selected device output pins. These BCR instructions are valid only when both bytes of the device are operating
in one direction of data flow (that is, 1OEAB ≠ 1OEBA and 2OEAB ≠ 2OEBA) and in the same direction of data
flow (that is, 1OEAB = 2OEAB and 1OEBA = 2OEBA). Otherwise, the bypass instruction is operated.
PSA input masking
Bits 20–3 of the BCR are used to specify device input pins to be masked from PSA operations. Bit 20 selects
masking for device input pin 2A9 during A-to-B data flow or for device input pin 2B9 during B-to-A data flow. Bit
3 selects masking for device input pins 1A1 or 1B1 during A-to-B or B-to-A data flow, respectively. Bits
intermediate to 20 and 3 mask corresponding device input pins in order from most significant to least significant,
as indicated in Table 2. When the mask bit that corresponds to a particular device input has a logic 1 value, the
device input pin is masked from any PSA operation, meaning that the state of the device input pin is ignored
and has no effect on the generated signature. Otherwise, when a mask bit has a logic 0 value, the corresponding
device input is not masked from the PSA operation.
sample inputs/toggle outputs (TOPSIP)
Data appearing at the selected device input pins is captured in the shift-register elements of the selected BSCs
on each rising edge of TCK. This data is updated in the shadow latches of the selected input BSCs and applied
to the inputs of the normal on-chip logic. Data in the shift-register elements of the selected output BSCs is
toggled on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output
pins on each falling edge of TCK.
4–14
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pseudo-random pattern generation (PRPG)
A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge
of TCK, updated in the shadow latches, and applied to the associated device output pins on each falling edge
of TCK. This data also is updated in the shadow latches of the selected input BSCs and applied to the inputs
of the normal on-chip logic. Figures 4 and 5 illustrate the 36-bit linear-feedback shift-register algorithms through
which the patterns are generated. An initial seed value should be scanned into the BSR before performing this
operation. A seed value of all zeroes does not produce additional patterns.
2A9-I
2A8-I
2A7-I
2A6-I
2A5-I
2A4-I
2A3-I
2A2-I
2A1-I
1A9-I
1A8-I
1A7-I
1A6-I
1A5-I
1A4-I
1A3-I
1A2-I
1A1-I
2B9-O
1B9-O
2B8-O
1B8-O
2B7-O
1B7-O
2B6-O
1B6-O
2B5-O
1B5-O
2B4-O
1B4-O
2B3-O
1B3-O
2B2-O
1B2-O
2B1-O
1B1-O
=
Figure 4. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)
4–15
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2B9-I
2B8-I
2B7-I
2B6-I
1B6-I
2B5-I
1B5-I
2B4-I
1B4-I
2B3-I
1B3-I
2B2-I
1B2-I
2B1-I
1B1-I
1B9-I
1B8-I
1B7-I
2A9-O
1A9-O
2A8-O
1A8-O
2A7-O
1A7-O
2A6-O
1A6-O
2A5-O
1A5-O
2A4-O
1A4-O
2A3-O
1A3-O
2A2-O
1A2-O
2A1-O
1A1-O
=
Figure 5. 36-Bit PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)
4–16
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parallel-signature analysis (PSA)
Data appearing at the selected device input pins is compressed into a 36-bit parallel signature in the
shift-register elements of the selected BSCs on each rising edge of TCK. This data is updated in the shadow
latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. Data in the shadow
latches of the selected output BSCs remains constant and is applied to the device outputs. Figures 6 and 7
illustrate the 36-bit linear-feedback shift-register algorithms through which the signature is generated. An initial
seed value should be scanned into the BSR before performing this operation.
2A9-I
2A8-I
2A7-I
2A6-I
2A5-I
2A4-I
2A3-I
2A2-I
2A1-I
1A9-I
1A8-I
1A7-I
1A6-I
1A5-I
1A4-I
1A3-I
1A2-I
1A1-I
2B9-O
1B9-O
2B8-O
1B8-O
2B7-O
1B7-O
2B6-O
1B6-O
2B5-O
1B5-O
2B4-O
1B4-O
2B3-O
1B3-O
2B2-O
1B2-O
2B1-O
1B1-O
=
=
Figure 6. 36-Bit PSA Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)
4–17
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2B9-I
2B8-I
2B7-I
2B6-I
1B6-I
2B5-I
1B5-I
2B4-I
1B4-I
2B3-I
1B3-I
2B2-I
1B2-I
2B1-I
1B1-I
1B9-I
1B8-I
1B7-I
2A9-O
1A9-O
2A8-O
1A8-O
2A7-O
1A7-O
2A6-O
1A6-O
2A5-O
1A5-O
2A4-O
1A4-O
2A3-O
1A3-O
2A2-O
1A2-O
2A1-O
1A1-O
=
=
Figure 7. 36-Bit PSA Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)
4–18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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simultaneous PSA and PRPG (PSA/PRPG)
Data appearing at the selected device input pins is compressed into an 18-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same
time, an 18-bit pseudo-random pattern is generated in the shift-register elements of the selected output BSCs
on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins
oneachfallingedgeofTCK. Figures8and9illustratethe18-bitlinear-feedbackshift-registeralgorithmsthrough
which the signature and patterns are generated. An initial seed value should be scanned into the BSR before
performing this operation. A seed value of all zeroes does not produce additional patterns.
2A9-I
2A8-I
2A7-I
2A6-I
2A5-I
2A4-I
2A3-I
2A2-I
2A1-I
1A9-I
1A8-I
1A7-I
1A6-I
1A5-I
1A4-I
1A3-I
1A2-I
1A1-I
2B9-O
2B8-O
2B7-O
2B6-O
2B5-O
2B4-O
2B3-O
2B2-O
2B1-O
=
=
1B9-O
1B8-O
1B7-O
1B6-O
1B5-O
1B4-O
1B3-O
1B2-O
1B1-O
Figure 8. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)
4–19
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2B9-I
2B8-I
2B7-I
2B6-I
2B5-I
2B4-I
2B3-I
2B2-I
2B1-I
1B9-I
1B8-I
1B7-I
1B6-I
1B5-I
1B4-I
1B3-I
1B2-I
1B1-I
2A9-O
2A8-O
2A7-O
2A6-O
2A5-O
2A4-O
2A3-O
2A2-O
2A1-O
=
=
1A9-O
1A8-O
1A7-O
1A6-O
1A5-O
1A4-O
1A3-O
1A2-O
1A1-O
Figure 9. 18-Bit PSA/PRPG Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)
4–20
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simultaneous PSA and binary count up (PSA/COUNT)
Data appearing at the selected device input pins is compressed into an 18-bit parallel signature in the
shift-register elements of the selected input BSCs on each rising edge of TCK. This data is updated in the
shadow latches of the selected input BSCs and applied to the inputs of the normal on-chip logic. At the same
time, an 18-bit binary count-up pattern is generated in the shift-register elements of the selected output BSCs
on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output pins
on each falling edge of TCK. Figures 10 and 11 illustrate the 18-bit linear-feedback shift-register algorithms
through which the signature is generated. An initial seed value should be scanned into the BSR before
performing this operation.
2A9-I
2A8-I
2A7-I
2A6-I
2A5-I
2A4-I
2A3-I
2A2-I
2A1-I
1A9-I
1A8-I
1A7-I
1A6-I
1A5-I
1A4-I
1A3-I
1A2-I
1A1-I
MSB
2B9-O
2B8-O
2B7-O
2B6-O
2B5-O
2B4-O
2B3-O
2B2-O
2B1-O
LSB
=
=
1B9-O
1B8-O
1B7-O
1B6-O
1B5-O
1B4-O
1B3-O
1B2-O
1B1-O
Figure 10. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 0, 1OEBA = 2OEBA = 1)
4–21
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2B9-I
2B8-I
2B7-I
2B6-I
2B5-I
2B4-I
2B3-I
2B2-I
2B1-I
1B9-I
1B8-I
1B7-I
1B6-I
1B5-I
1B4-I
1B3-I
1B2-I
1B1-I
MSB
2A9-O
2A8-O
2A7-O
2A6-O
2A5-O
2A4-O
2A3-O
2A2-O
2A1-O
LSB
=
=
1A9-O
1A8-O
1A7-O
1A6-O
1A5-O
1A4-O
1A3-O
1A2-O
1A1-O
Figure 11. 18-Bit PSA/COUNT Configuration (1OEAB = 2OEAB = 1, 1OEBA = 2OEBA = 0)
4–22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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timing description
All test operations of the SN54ABT18502 are synchronous to the TCK signal. Data on the TDI, TMS, and
normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function
output pins on the falling edge of TCK. The TAP controller is advanced through its states (as illustrated in
Figure 1) by changing the value of TMS on the falling edge of TCK and then applying a rising edge to TCK.
A simple timing example is illustrated in Figure 12. In this example, the TAP controller begins in the
Test-Logic-Reset state and is advanced through its states as necessary to perform one instruction-register scan
and one data-register scan. While in the Shift-IR and Shift-DR states, TDI is used to input serial data, and TDO
is used to output serial data. The TAP controller is then returned to the Test-Logic-Reset state. Table 6 explains
the operation of the test circuitry during each TCK cycle.
Table 6. Explanation of Timing Example
TCK
CYCLE(S)
TAP STATE
AFTER TCK
DESCRIPTION
TMS is changed to a logic 0 value on the falling edge of TCK to begin advancing the TAP controller toward
the desired state.
1
Test-Logic-Reset
2
3
4
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
The IR captures the 8-bit binary value 10000001 on the rising edge of TCK as the TAP controller exits the
Capture-IR state.
5
6
Capture-IR
Shift-IR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on
the rising edge of TCK as the TAP controller advances to the next state.
One bit is shifted into the IR on each TCK rising edge. With TDI held at a logic 1 value, the 8-bit binary value
11111111 is serially scanned into the IR. At the same time, the 8-bit binary value 10000001 is serially scanned
out of the IR via TDO. In TCK cycle 13 TMS is changed to a logic 1 value to end the IR scan on the next TCK
cycle. The last bit of the instruction is shifted as the TAP controller advances from Shift-IR to Exit1-IR.
7–13
Shift-IR
14
15
16
Exit1-IR
Update-IR
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
The IR is updated with the new instruction (BYPASS) on the falling edge of TCK.
Select-DR-Scan
The bypass register captures a logic 0 value on the rising edge of TCK as the TAP controller exits the
Capture-DR state.
17
18
Capture-DR
Shift-DR
TDO becomes active and TDI is made valid on the falling edge of TCK. The first bit is shifted into the TAP on
the rising edge of TCK as the TAP controller advances to the next state.
19–20
21
Shift-DR
Exit1-DR
The binary value 101 is shifted in via TDI, while the binary value 010 is shifted out via TDO.
TDO becomes inactive (goes to the high-impedance state) on the falling edge of TCK.
In general, the selected data register is updated with the new data on the falling edge of TCK.
22
Update-DR
23
Select-DR-Scan
Select-IR-Scan
24
25
Test-Logic-Reset Test operation completed
4–23
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1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TCK
TMS
TDI
TDO
TAP
Controller
State
3-State (TDO) or Don’t Care (TDI)
Figure 12. Timing Example
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Input voltage range, V (I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
I
Voltage range applied to any output in the high state or power-off state, V
. . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT18502 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
CC
Continuous current through V
Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 mA
Maximum power dissipation at T = 55°C (in still air) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885 mW
A
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings can be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions (see Note 2)
MIN
4.5
2
MAX
UNIT
V
V
V
V
V
Supply voltage
5.5
CC
High-level input voltage
Low-level input voltage
Input voltage
V
IH
0.8
V
IL
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
48
mA
mA
ns/V
°C
OH
OL
∆t/∆v
10
T
–55
125
A
NOTE 2: Unused or floating pins (input or I/O) must be held high or low.
4–24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
A
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
†
MIN TYP
MAX
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
CC
CC
I
I
I
I
I
I
I
= – 3 mA
= – 3 mA
= – 24 mA
= – 32 mA
= 48 mA
2.5
3
2.5
3
OH
OH
OH
OH
OL
OL
V
OH
V
= 4.5 V,
= 4.5 V,
2
2
2*
0.55
0.55*
±1
0.55
V
OL
V
= 4.5 V
= 5.5 V,
V
CC
CC
= 64 mA
CLK,LE,OE,TCK
A or B ports
TDI, TMS
±1
±100
10
I
I
V
V = V
or GND
µA
I
CC
CC
±100
10
I
I
I
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 0 to 2 V,
= 2 V to 0,
= 0,
V = V
I
µA
µA
µA
µA
µA
µA
µA
µA
mA
IH
V = GND
I
TDI, TMS
–150
50
–150
50
IL
‡
V
O
V
O
V
O
V
O
= 2.7 V
OZH
‡
= 0.5 V
–50
±50
±50
±100
50
–50
±50
±50
±450
50
OZL
= 2.7 V or 0.5 V
= 2.7 V or 0.5 V
OE = 0.8 V
OE = 0.8 V
OZPU
OZPD
off
V or V ≤ 4.5 V
I
O
= 5.5 V,
= 5.5 V,
V
= 5.5 V
Outputs high
CEX
O
O
§
V
= 2.5 V
–50
–110
3.5
33
–200
5.5
–50
–200
5.5
O
Outputs high
Outputs low
V
I
= 5.5 V,
= 0,
CC
O
I
A or B ports
38
38
mA
CC
V = V
I
or GND
CC
Outputs disabled
2.9
5
5
V
= 5.5 V,
One input at 3.4 V,
or GND
CC
Other inputs at V
¶
50
50
µA
∆I
CC
CC
V = 2.5 V or 0.5 V
C
C
C
Control inputs
A or B ports
TDO
3
10
8
pF
pF
pF
i
I
V
= 2.5 V or 0.5 V
= 2.5 V or 0.5 V
io
o
O
O
V
* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
†
‡
§
¶
All typical values are at V
= 5 V.
CC
and I
The parameters I
include the input leakage current.
OZL
OZH
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
4–25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 13)
MIN
0
MAX
UNIT
f
t
Clock frequency
Pulse duration
CLKAB or CLKBA
100
MHz
clock
CLKAB or CLKBA high or low
LEAB or LEBA high
3.5
3.5
4
ns
ns
ns
w
A before CLKAB↑ or B before CLKBA↑
t
t
Setup time
Hold time
CLK high
CLK low
3.5
2
su
A before LEAB↓ or B before LEBA↓
A after CLKAB↑ or B after CLKBA↑
A after LEAB↓ or B after LEBA↓
0
h
2
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 13)123
MIN
0
MAX
UNIT
MHz
ns
f
t
Clock frequency
Pulse duration
TCK
50
clock
TCK high or low
8
w
A, B, CLK, LE, or OE before TCK↑
TDI before TCK↑
4.5
7.5
3
t
Setup time
Hold time
ns
ns
su
h
TMS before TCK↑
A, B, CLK, LE, or OE after TCK↑
TDI after TCK↑
0.5
0.5
0.5
50
1
t
TMS after TCK↑
t
t
Delay time
Rise time
Power up to TCK↑
ns
d
V
CC
power up
µs
r
4–26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (normal mode) (see Figure 13)
V
T
= 5 V,
= 25°C
CC
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
100
2
TYP
130
3.8
3.8
4.7
4.7
4.9
4.9
4.9
5.6
6.1
4.8
MAX
MIN
100
2
MAX
f
t
t
t
t
t
t
t
t
t
t
CLKAB or CLKBA
A or B
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
5.6
6.6
6.7
5.7
7.4
6.5
7.3
7.2
8.8
6.5
6.5
7.2
8.2
7.1
8.5
7.8
8.5
8.3
10.6
7.4
B or A
B or A
B or A
B or A
B or A
2
2
2.5
2.5
2.5
2.5
2
2.5
2.5
2.5
2.5
2
CLKAB or CLKBA
LEAB or LEBA
ns
ns
ns
ns
OEAB or OEBA
OEAB or OEBA
2.5
3
2.5
3
2.5
2.5
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (test mode) (see Figure 13)123
V
T
= 5 V,
= 25°C
CC
A
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
50
2.5
2.5
2
TYP
90
MAX
MIN
50
2.5
2.5
2
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
TCK
MHz
ns
max
PLH
PHL
PLH
PHL
PZH
PZL
PZH
PZL
PHZ
PLZ
PHZ
PLZ
9.1
9.1
3.8
3.8
9.5
10.1
4.6
5.2
11.6
11.1
5.3
5.2
12.4
11.8
6.1
16.9
14.6
7
TCK↓
A or B
TDO
TCK↓
TCK↓
TCK↓
TCK↓
TCK↓
ns
ns
ns
ns
ns
2
6.3
2
7.6
17
4.5
5
13.5
13.2
7.9
4.5
5
A or B
TDO
15.8
8.2
8.9
18.5
18.5
10.7
8
2.5
3
2.5
3
7.8
4
15.3
13.6
9.2
4
A or B
TDO
3.5
3
3.5
3
3
6.8
3
4–27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT18502
SCAN TEST DEVICE WITH
18-BIT REGISTERED BUS TRANSCEIVER
SCBS109C – AUGUST 1992 – REVISED AUGUST 1994
PARAMETER MEASUREMENT INFORMATION
7 V
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
/t
(see Note A)
Open
PHZ PZH
LOAD CIRCUIT FOR OUTPUTS
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Input
(see Note B)
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note C)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at Open
(see Note C)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 13. Load Circuit and Voltage Waveforms
4–28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
SNJ54ABT18646HVR
ABT SERIES, DUAL 9-BIT BOUNDARY SCAN REG TRANSCEIVER, TRUE OUTPUT, CQFP68, CERAMIC, QFP-68
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