TAS5112DFDRG4 [TI]

Digital Amplifier Stereo Power Stage 56-HTSSOP 0 to 70;


型号：	TAS5112DFDRG4
厂家：	TEXAS INSTRUMENTS
描述：	Digital Amplifier Stereo Power Stage 56-HTSSOP 0 to 70 放大器光电二极管商用集成电路
文件：	总22页 (文件大小：806K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ꢀꢁ ꢂꢃ ꢄꢄꢅ

SLES048C − JULY 2003 − REVISED MARCH 2004

www.ti.com

ꢆ

ꢇ

ꢈ

ꢇ

ꢀ

ꢁ

ꢉ

ꢁ

ꢊ

ꢋ

ꢉ

ꢇ

ꢌ

ꢇ

ꢍ

ꢎ

ꢋ

ꢏ

ꢐ

ꢍ

ꢎ

ꢂ

ꢀ

ꢁ

ꢈ

ꢍ

FEATURES

APPLICATIONS

DVD Receiver

Home Theatre

Mini/Micro Component Systems

Internet Music Appliance

50 W per Channel (BTL) Into 6 Ω (Stereo)

95-dB Dynamic Range With TAS5026

Less Than 0.1% THD+N (1 W RMS Into 6 Ω)

Less Than 0.2% THD+N (50 W RMS into 6 Ω)

DESCRIPTION

Power Efficiency Typically 90% Into 6-Ω Load

The TAS5112 is a high-performance, integrated stereo

digital amplifier power stage designed to drive 6-Ω

speakers at up to 50 W per channel. The device

incorporates TI’s PurePath Digitalt technology and is

used with a digital audio PWM processor (TAS50XX) and

a simple passive demodulation filter to deliver high-quality,

high-efficiency, true-digital audio amplification.

Self-Protecting Design (Undervoltage,

Overtemperature and Short Conditions) With

Error Reporting

Internal Gate Drive Supply Voltage Regulator

EMI Compliant When Used With

Recommended System Design

The efficiency of this digital amplifier is typically 90%,

reducing the size of both the power supplies and heatsinks

needed. Overcurrent protection, overtemperature

protection, and undervoltage protection are built into the

TAS5112, safeguarding the device and speakers against

fault conditions that could damage the system.

THD + NOISE vs OUTPUT POWER

THD + NOISE vs FREQUENCY

= 6 Ω

= 75°C

= 6 Ω

= 75°C

= 50 W

0.1

= 10 W

0.1

= 1 W

0.01

0.001

100m

100

f − Frequency − Hz

10k 20k

− Output Power − W

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

PurePath Digital and PowerPAD are trademarks of Texas Instruments.

Other trademarks are the property of their respective owners.

ꢋꢎ ꢏ ꢆꢑ ꢒ ꢀꢇ ꢏꢓ ꢆ ꢁꢀꢁ ꢔꢕ ꢖꢗ ꢘ ꢙꢚ ꢛꢔꢗꢕ ꢔꢜ ꢝꢞ ꢘ ꢘ ꢟꢕꢛ ꢚꢜ ꢗꢖ ꢠꢞꢡ ꢢꢔꢝ ꢚꢛꢔ ꢗꢕ ꢣꢚ ꢛꢟꢤ ꢋꢘ ꢗꢣꢞ ꢝꢛꢜ

ꢝ ꢗꢕ ꢖꢗꢘ ꢙ ꢛꢗ ꢜ ꢠꢟ ꢝ ꢔ ꢖꢔ ꢝ ꢚ ꢛꢔ ꢗꢕꢜ ꢠ ꢟꢘ ꢛꢥꢟ ꢛꢟ ꢘ ꢙꢜ ꢗꢖ ꢀꢟꢦ ꢚꢜ ꢇꢕꢜ ꢛꢘ ꢞꢙ ꢟꢕꢛ ꢜ ꢜꢛ ꢚꢕꢣ ꢚꢘ ꢣ ꢧ ꢚꢘ ꢘ ꢚ ꢕꢛꢨꢤ

ꢋꢘ ꢗ ꢣꢞꢝ ꢛ ꢔꢗ ꢕ ꢠꢘ ꢗ ꢝ ꢟ ꢜ ꢜ ꢔꢕ ꢩ ꢣꢗ ꢟ ꢜ ꢕꢗꢛ ꢕꢟ ꢝꢟ ꢜꢜ ꢚꢘ ꢔꢢ ꢨ ꢔꢕꢝ ꢢꢞꢣ ꢟ ꢛꢟ ꢜꢛꢔ ꢕꢩ ꢗꢖ ꢚꢢ ꢢ ꢠꢚ ꢘ ꢚꢙ ꢟꢛꢟ ꢘ ꢜꢤ

ꢀ

ꢁ

ꢂ

ꢃ

ꢄꢄ

ꢅ

www.ti.com

SLES048C − JULY 2003 − REVISED MARCH 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

GENERAL INFORMATION

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

Terminal Assignment

TAS5112

DVDD TO DGND

UNITS

–0.3 V to 4.2 V

33.5 V

48 V

The TAS5112 is offered in a thermally enhanced 56-pin

TSSOP DFD (thermal pad is on the top), shown as follows.

GVDD TO GND

DFD PACKAGE

(TOP VIEW)

PVDD_X TO GND (dc voltage)

PVDD_X TO GND (spike voltage

OUT_X TO GND (dc voltage)

(2)

)

33.5 V

48 V

GND

GVDD

(2)

OUT_X TO GND (spike voltage

BST_X TO GND (dc voltage)

BST_X TO GND (spike voltage

GREG

BST_D

PVDD_D

OUT_D

GND

48 V

OTW

(2)

)

53 V

SD_CD

SD_AB

PWM_DP

PWM_DM

RESET_CD

PWM_CM

PWM_CP

DREG_RTN

(3)

GREG TO GND

14.2 V

PWM_XP, RESET, M1, M2, M3, SD,

OTW

–0.3 V to DVDD + 0.3 V

Maximum operating junction

GND

–40°C to 150°C

–40°C to 125°C

temperature, T

OUT_C

PVDD_C

BST_C

BST_B

PVDD_B

OUT_B

GND

Storage temperature

(1)

Stresses beyond those listed under “absolute maximum ratings”

may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any

other conditions beyond those indicated under “recommended

operating conditions” is not implied. Exposure to absolute-

maximum-ratedconditions for extended periods may affect device

reliability.

DREG

PWM_BP

PWM_BM

RESET_AB

PWM_AM

PWM_AP

GND

(2)

(3)

The duration of voltage spike should be less than 100 ns.

GREG is treated as an input when the GREG pin is overdriven by

GVDD of 12 V.

GND

ORDERING INFORMATION

OUT_A

PVDD_A

BST_A

GVDD

PACKAGE

DESCRIPTION

DGND

GND

DVDD

GREG

GND

0°C to 70°C

TAS5112DFD

56-pin small TSSOP

(1)

For the most current specification and package information, refer to

our Web site at www.ti.com.

PACKAGE DISSIPATION RATINGS

GND

θJC

θJA

PACKAGE

(°C/W)

56-pin DAD TSSOP

1.14

See Note 1

(1)

The TAS5112 package is thermally enhanced for conductive

cooling using an exposed metal pad area. It is impractical to use the

device with the pad exposed to ambient air as the only heat sinking

of the device.

For this reason, R

thermaltreatment, is provided in theApplication Information section

a system parameter that characterizes the

θJA,

of the data sheet. An example and discussion of typical system

θJA

values are provided in the Thermal Information section. This

example provides additional information regarding the power

dissipationratings. This example should be used as a reference to

calculate the heat dissipation ratings for a specific application. TI

application engineering provides technical support to design

heatsinks if needed.

www.ti.com

ꢀꢁ ꢂꢃ ꢄꢄꢅ

SLES048C − JULY 2003 − REVISED MARCH 2004

Terminal Functions

TERMINAL

NAME

BST_A

(1)

FUNCTION

DESCRIPTION

NO.

High-side bootstrap supply (BST), external capacitor to OUT_A required

High-side bootstrap supply (BST), external capacitor to OUT_B required

HS bootstrap supply (BST), external capacitor to OUT_C required

HS bootstrap supply (BST), external capacitor to OUT_D required

Digital I/O reference ground

BST_B

BST_C

BST_D

DGND

DREG

Digital supply voltage regulator decoupling pin, capacitor connected to GND

Digital supply voltage regulator decoupling return pin

I/O reference supply input (3.3 V)

DREG_RTN

DVDD

GND

1, 2, 22, 24,

27, 28, 29, 36,

37, 48, 49, 56

Power ground

GREG

3, 26

30, 55

Gate drive voltage regulator decoupling pin, capacitor to REG_GND

Voltage supply to on-chip gate drive and digital supply voltage regulators

Mode selection pin

GVDD

M1 (TST0)

Mode selection pin

OTW

Overtemperature warning output, open drain with internal pullup resistor

Output, half-bridge A

OUT_A

34, 35

38, 39

46, 47

50, 51

32, 33

40, 41

44, 45

52, 53

OUT_B

Output, half-bridge B

OUT_C

Output, half-bridge C

OUT_D

Output, half-bridge D

PVDD_A

PVDD_B

PVDD_C

PVDD_D

PWM_AM

PWM_AP

PWM_BM

PWM_BP

PWM_CM

PWM_CP

PWM_DM

PWM_DP

RESET_AB

RESET_CD

SD_AB

Power supply input for half-bridge A

Power supply input for half-bridge B

Power supply input for half-bridge C

Power supply input for half-bridge D

Input signal (negative), half-bridge A

Input signal (positive), half-bridge A

Input signal (negative), half-bridge B

Input signal (positive), half-bridge B

Input signal (negative), half-bridge C

Input signal (positive), half-bridge C

Input signal (negative), half-bridge D

Input signal (positive), half-bridge D

Reset signal, active low

Shutdown signal for half-bridges A and B, active-low

Shutdown signal for half-bridges C and D, active-low

SD_CD

(1)

I = input, O = Output, P = Power

ꢀꢁ

ꢂ

ꢃ

ꢄꢄ

ꢅ

www.ti.com

SLES048C − JULY 2003 − REVISED MARCH 2004

FUNCTIONAL BLOCK DIAGRAM

BST_A

GREG

PVDD_A

Gate

Drive

OUT_A

GND

PWM_AP

PWM

Timing

Control

Receiver

Gate

Drive

Protection A

BST_B

RESET

GREG

PVDD_B

Protection B

Gate

Drive

PWM_BP

OUT_B

GND

PWM

Receiver

Timing

Control

Gate

Drive

To Protection

Blocks

DREG

GVDD

OTW

GREG

Protection

UVP

GREG

DREG

GREG

DREG_RTN

This diagram shows one channel.

www.ti.com

ꢀꢁ ꢂꢃ ꢄꢄꢅ

SLES048C − JULY 2003 − REVISED MARCH 2004

RECOMMENDED OPERATING CONDITIONS

MIN

TYP

MAX

UNIT

(1)

DVDD

GVDD

Digital supply

Relative to DGND

Relative to GND

3.3

3.6

Supply for internal gate drive and logic

regulators

29.5

30.5

PVDD_x Half-bridge supply

Junction temperature

It is recommended for DVDD to be connected to DREG via a 100-Ω resistor.

Relative to GND, R = 6 Ω to 8 Ω

30.5

125

(1)

ELECTRICAL CHARACTERISTICS

PVDD_X = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, R = 6 Ω, 8X f = 384 kHz, unless otherwise noted

TYPICAL

OVER TEMPERATURE

SYMBOL

PARAMETER

TEST CONDITIONS

75°C

T =40°C

TO 85°C

MIN/TYP/

MAX

Case

T =25°C

UNITS

AC PERFORMANCE, BTL Mode, 1 kHz

= 8 Ω, THD = 0.2%,

Typ

AES17 filter, 1 kHz

= 8 Ω, THD = 10%, AES17

filter, 1 kHz

Output power

= 6 Ω, THD = 0.2%,

AES17 filter, 1 kHz

= 6 Ω, THD = 10%, AES17

filter, 1 kHz

Po = 1 W/ channel, R = 6 Ω,

AES17 filter

0.03%

0.04%

0.2%

Po = 10 W/channel, R = 6 Ω,

AES17 filter

Total harmonic distortion

+ noise

THD+N

Po = 50 W/channel, R = 6 Ω,

AES17 filter

Output integrated voltage A-weighted, mute, R = 6 Ω,,

260

µV

Max

Typ

noise

20 Hz to 20 kHz, AES17 filter

SNR

Signal-to-noise ratio

A-weighted, AES17 filter

f = 1 kHz, A-weighted,

AES17 filter

Dynamic range

INTERNAL VOLTAGE REGULATOR

= 1 mA,

DREG

GREG

IVGDD

IDVDD

Voltage regulator

3.1

Typ

PVDD = 18 V−30.5 V

= 1.2 mA,

13.4

PVDD = 18 V−30.5 V

f = 384 kHz, no load, 50%

GVDD supply current,

operating

Max

duty cycle

DVDD supply current,

operating

= 384 kHz, no load

OUTPUT STAGE MOSFETs

Forward on-resistance,

low side

T = 25°C

155

mΩ

Typ

on,LS

on,HS

Forward on-resistance,

high side

T = 25°C

ꢀꢁ

ꢂ

ꢃ

ꢄꢄ

ꢅ

www.ti.com

SLES048C − JULY 2003 − REVISED MARCH 2004

ELECTRICAL CHARACTERISTICS

PVDD_x = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, R = 6 Ω, 8X f = 384 kHz, unless otherwise noted

TYPICAL

OVER TEMPERATURE

SYMBOL

PARAMETER

TEST CONDITIONS

T =40°C

TO 85°C

MIN/TYP/

MAX

Case

75°C

T =25°C

UNITS

INPUT/OUTPUT PROTECTION

Set the DUT in normal

operation mode with all the

protections enabled. Sweep

GVDD up and down. Monitor

SD output. Record the

GREG reading when SD is

triggered.

6.9

7.9

Min

Undervoltage protection

limit, GVDD

7.4

uvp,G

Max

Typ

Overtemperature warning,

junction temperature

OTW

125

°C

Overtemperature error,

junction temperature

OTE

150

5.8

°C

Typ

Overcurrent protection

See Note 1.

STATIC DIGITAL SPECIFICATION

PWM_AP, PWM_BP, M1,

M2, M3, SD, OTW

DVDD

0.8

Min

Max

Min

High-level input voltage

Low-level input voltage

−10

µA

Leakage

Input leakage current

Max

OTW/SHUTDOWN (SD)

Internally pull up R from

22.5

0.4

kΩ

Min

OTW/SD to DVDD

Low-level output voltage

= 4 mA

Max

(1)

To optimize device performance and prevent overcurrent (OC) protection tripping, the demodulation filter must be designed with special care. See

DemodulationFilter Design in the Application Information section of the data sheet and consider the recommended inductors and capacitors for

optimalperformance. It is also important to consider PCB design and layout for optimum performance of the TAS5112. It is recommended to follow

the TAS5112F2EVM (S/N 112) design and layout guidelines for best performance.

www.ti.com

ꢀꢁ ꢂꢃ ꢄꢄꢅ

SLES048C − JULY 2003 − REVISED MARCH 2004

SYSTEM CONFIGURATION USED FOR CHARACTERIZATION

Gate-Drive

Power Supply

External Power Supply

H-Bridge

Power Supply

TAS5112DFD

GND

GVDD

1 µF

GND

1.5 Ω

100 nF

GREG

BST_D

PVDD_D

OUT_D

GND

33 nF

PCB

OTW

SD_CD

SD_AB

PWM_DP

PWM_DM

RESET_CD

PWM_CM

PWM_CP

DREG_RTN

100 nF

ERR_RCVY

PWM_AP_1

PWM_AM_1

VALID_1

10 µH

4.7 kΩ

1.5 Ω

{

470 nF

100 nF

GND

1.5 Ω

10 µH

OUT_C

{

100 nF

PVDD_C

BST_C

100 nF

PWM PROCESSOR

TAS5026

PCB

33 nF

1000 µF

1.5 Ω

BST_B

PVDD_B

OUT_B

GND

33 nF

PCB

DREG

PWM_BP

PWM_AP_2

PWM_AM_2

VALID_2

100 nF

PWM_BM

RESET_AB

PWM_AM

PWM_AP

GND

10 µH

4.7 kΩ

1.5 Ω

{

470 nF

100 nF

GND

OUT_A

PVDD_A

BST_A

GVDD

1.5 Ω

100 Ω

10 µH

DGND

{

100 nF

GND

DVDD

GREG

GND

PCB

33 nF

1000 µF

1 µF

1.5 Ω

100 nF

GND

{

: TRACK IN THE PCB (1,0 mm wide and 50 mm long)

Voltage Suppressor Diode: 1SMA33CAT

PCB

ꢀꢁ

ꢂ

ꢃ

ꢄꢄ

ꢅ

www.ti.com

SLES048C − JULY 2003 − REVISED MARCH 2004

TYPICAL CHARACTERISTICS AND SYSTEM PERFORMANCE

OF TAS5112 EVM WITH TAS5026 PWM PROCESSOR

TOTAL HARMONIC DISTORTION + NOISE

NOISE AMPLITUDE

FREQUENCY

−20

= 6 Ω

= 75°C

= 6 Ω

FFT = −60 dB

= 75°C

TAS5026 Front End Device

= 50 W

−40

0.1

−60

= 10 W

−80

= 1 W

−100

−120

−140

−160

0.01

0.001

10 12 14 16 18 20 22

100

10k 20k

f − Frequency − Hz

f − Frequency − kHz

Figure 1

Figure 2

TOTAL HARMONIC DISTORTION + NOISE

OUTPUT POWER

H-BRIDGE VOLTAGE

= 6 Ω

= 75°C

= 6 Ω

= 8 Ω

0.1

0.01

100m

100

− Output Power − W

VDD − Supply Voltage − V

Figure 3

Figure 4

www.ti.com

ꢀꢁ ꢂꢃ ꢄꢄꢅ

SLES048C − JULY 2003 − REVISED MARCH 2004

SYSTEM OUTPUT STAGE EFFICIENCY

POWER LOSS

OUTPUT POWER

100

f = 1 kHz

= 6 Ω

= 75°C

f = 1 kHz

= 6 Ω

= 75°C

10 15 20 25 30 35 40 45 50 55 60 65

− Output Power − W

Figure 5

Figure 6

OUTPUT POWER

AMPLITUDE

CASE TEMPERATURE

FREQUENCY

3.0

2.5

PVDD = 29.5 V

= 6 Ω

2.0

1.5

1.0

= 6 Ω

0.5

0.0

Channel 1

−0.5

−1.0

−1.5

−2.0

−2.5

−3.0

Channel 2

= 8 Ω

100

120

140

100

10k

50k

− Case Temperature − °C

f − Frequency − Hz

Figure 7

Figure 8

ꢀꢁ

ꢂ

ꢃ

ꢄꢄ

ꢅ

www.ti.com

SLES048C − JULY 2003 − REVISED MARCH 2004

ON-STATE RESISTANCE

JUNCTION TEMPERATURE

200

190

180

170

160

150

140

130

120

10 20 30 40 50 60 70 80 90 100

− Junction Temperature − °C

Figure 9

www.ti.com

ꢀꢁ ꢂꢃ ꢄꢄꢅ

SLES048C − JULY 2003 − REVISED MARCH 2004

This precharges the bootstrap supply capacitors and

discharges the output filter capacitor (see the Typical

TAS5112 Application Configuration section).

THEORY OF OPERATION

POWER SUPPLIES

After GVDD has been applied, it takes approximately 800

µs to fully charge the BST capacitor. Within this time,

RESET must be kept low. After approximately 1 ms, the

back-end bootstrap capacitor is charged.

The power device only requires two supply voltages,

GVDD and PVDD_X.

GVDD is the gate drive supply for the device, regulated

internally down to approximately 12 V, and decoupled with

regards to board GND on the GREG pins through an

external capacitor. GREG powers both the low side and

high side via a bootstrap step-up conversion. The

bootstrap supply is charged after the first low-side turn-on

pulse. Internal digital core voltage DREG is also derived

from GVDD and regulated down by internal circuitry to

3.3 V.

RESET can now be released if the modulator is powered

up and streaming valid PWM signals to the back-end

PWM_xP. Valid means a switching PWM signal which

complies with the frequency and duty cycle ranges stated

in the Recommended Operating Conditions.

A constant HIGH dc level on the PWM_xP is not permitted,

because it would force the high-side MOSFET ON until it

eventually ran out of BST capacitor energy and might

damage the device.

The gate-driver regulator can be bypassed for reducing

idle loss in the device by shorting GREG to GVDD and

directly feeding in 12.0 V. This can be useful in an

application where thermal conduction of heat from the

device is difficult.

An unknown state of the PWM output signals from the

modulator is illegal and should be avoided, which in

practice means that the PWM processor must be powered

up and initialized before RESET is de-asserted HIGH to

the back end.

PVDD_X is the H-bridge power supply pin. Two power pins

exists for each half-bridge to handle the current density. It

is important that the circuitry recommendations around

the PVDD_X pins are followed carefully both topology-

and layout-wise. For topology recommendations, see the

Typical System Configuration section. Following these

recommendations is important for parameters like EMI,

reliability, and performance.

POWERING DOWN

For power down of the back end, an opposite approach is

necessary. The RESET must be asserted LOW before the

valid PWM signal is removed.

When PWM processors are used with TI PurePath Digital

amplifiers, the correct timing control of RESET and

PWM_xP is performed by the modulator.

POWERING UP

PRECAUTION

> 1 ms

The TAS5112 must always start up in the high-impedance

(Hi-Z) state. In this state, the bootstrap (BST) capacitor is

precharged by a resistor on each PWM output node to

ground. See the system configuration. This ensures that

the back end is ready for receiving PWM pulses, indicating

either HIGH- or LOW-side turnon after RESET is

de-asserted to the back end.

RESET

GVDD

With the following pulldown resistor and BST capacitor

size, the charge time is:

PVDD_x

C = 33 nF, R = 4.7 kΩ

R × C × 5 = 775.5 µs

After GVDD has been applied, it takes approximately 800

µs to fully charge the BST capacitor. During this time,

RESET must be kept low. After approximately 1 ms the

back end BST is charged and ready. RESET can now be

released if the PWM modulator is ready and is streaming

valid PWM signals to the back end. Valid PWM signals are

switching PWM signals with a frequency between

350−400 kHz. A constant HIGH level on the PWM+ would

force the high-side MOSFET ON until it eventually ran out

of BST capacitor energy. Putting the device in this

condition should be avoided.

PWM_xP

NOTE: PVDD should not be powered up before GVDD.

During power up when RESET is asserted LOW, all

MOSFETs are turned off and the two internal half-bridges

are in the high-impedance state (Hi-Z). The bootstrap

capacitors supplying high-side gate drive are not charged

at this point. To comply with the click and pop scheme and

use of non-TI modulators it is recommended to use a 4-kΩ

pulldown resistor on each PWM output node to ground.

ꢀꢁ

ꢂ

ꢃ

ꢄꢄ

ꢅ

www.ti.com

SLES048C − JULY 2003 − REVISED MARCH 2004

In practice this means that the DVDD-to-PWM processor

(front-end) should be stable and initialization should be

completed before RESET is de-asserted to the back end.

The device can be recovered by toggling RESET low and

then high, after all errors are cleared.

Overcurrent (OC) Protection

The device has individual forward current protection on

both high-side and low-side power stage FETs. The OC

protection works only with the demodulation filter present

at the output. See Demodulation Filter Design in the

Application Information section of the data sheet for design

constraints.

CONTROL I/O

Shutdown Pin: SD

The SD pin functions as an output pin and is intended for

protection-mode signaling to, for example, a controller or

other front-end device. The pin is open-drain with an

internal pullup resistor to DVDD.

Overtemperature (OT) Protection

The logic output is, as shown in the following table, a

combination of the device state and RESET input:

A dual temperature protection system asserts a warning

signal when the device junction temperature exceeds

125°C. The OT protection circuit is shared by all

half-bridges.

RESET

DESCRIPTION

Not used

Device in protection mode, i.e., UVP and/or OC

and/or OT error

Undervoltage (UV) Protection

(1)

Device set high-impedance (Hi-Z), SD forced high

Normal operation

Undervoltage lockout occurs when GVDD is insufficient

for proper device operation. The UV protection system

protects the device under power-up and power-down

situations. The UV protection circuits are shared by all

half-bridges.

(1)

SD is pulled high when RESET is asserted low independent of chip

state (i.e., protection mode). This is desirable to maintain

compatibilitywith some TI PWM front ends.

Temperature Warning Pin: OTW

Reset Function

The OTW pin gives a temperature warning signal when

temperature exceeds the set limit. The pin is of the

open-drain type with an internal pullup resistor to DVDD.

The function of the reset input is twofold:

Reset is used for re-enabling operation after a

latching error event.

OTW

DESCRIPTION

Junction temperature higher than 125°C

Junction temperature lower than 125°C

Reset is used for disabling output stage

switching (mute function).

Overall Reporting

The error latch is cleared on the falling edge of reset and

normal operation is resumed when reset goes high.

The SD pin, together with the OTW pin, gives chip state

information as described in Table 1.

Table 1. Error Signal Decoding

PROTECTION MODE

OTW

DESCRIPTION

Overtemperatureerror (OTE)

Autorecovery (AR) After Errors (PMODE0)

Overtemperature warning (OTW)

Overcurrent (OC) or undervoltage (UVP) error

Normal operation, no errors/warnings

In autorecovery mode (PMODE0) the TAS5112 is

self-supported in handling of error situations. All protection

systems are active, setting the output stage in the

high-impedance state to protect the output stage and

connected equipment. However, after a short time the

device autorecovers, i.e., operation is automatically

resumed provided that the system is fully operational.

Chip Protection

The TAS5112 protection function is implemented in a

closed loop with, for example, a system controller and TI

PWM processor. The TAS5112 contains three individual

systems protecting the device against error conditions. All

of the error events covered result in the output stage being

set in a high-impedance state (Hi-Z) for maximum

protection of the device and connected equipment.

The autorecovery timing is set by counting PWM input

cycles, i.e., the timing is relative to the switching frequency.

The AR system is common to both half-bridges.

www.ti.com

ꢀꢁ ꢂꢃ ꢄꢄꢅ

SLES048C − JULY 2003 − REVISED MARCH 2004

Timing and Function

Table 3. Output Mode Selection

The function of the autorecovery circuit is as follows:

OUTPUT MODE

Bridge-tied load output stage (BTL)

Reserved

1. An error event occurs and sets the

protection latch (output stage goes Hi-Z).

2. The counter is started.

APPLICATION INFORMATION

3. After n/2 cycles, the protection latch is

cleared but the output stage remains Hi-Z

(identical to pulling RESET low).

DEMODULATION FILTER DESIGN

4. After n cycles, operation is resumed

(identical to pulling RESET high) (n = 512).

The PurePath Digital amplifier outputs are driven by

heavy-duty DMOS transistors in an H-bridge

configuration. These transistors are either off or fully on,

which reduces the DMOS transistor on-state resistance,

R(DMOSon), and the power dissipated in the device,

thereby increasing efficiency.

Error

Protection

Latch

The result is a square-wave output signal with a duty cycle

that is proportional to the amplitude of the audio signal. It

is recommended that a second-order LC filter be used to

recover the audio signal. For this application, EMI is

considered important; therefore, the selected filter is the

full-output type shown in Figure 11.

Shutdown

Autorecovery

PWM

TAS51xx

Counter

Output A

(Load)

AR-RESET

C1A

C1B

Figure 10. Autorecovery Function

Latching Shutdown on All Errors (PMODE1)

In latching shutdown mode, all error situations result in a

power down (output stage Hi-Z). Re-enabling can be done

by toggling the RESET pin.

Output B

All Protection Systems Disabled (PMODE2)

Figure 11. Demodulation Filter

In PMODE2, all protection systems are disabled. This

mode is purely intended for testing and characterization

purposes and thus not recommended for normal device

operation.

The main purpose of the output filter is to attenuate the

high-frequency switching component of the PurePath

Digital amplifier while preserving the signals in the audio

band.

MODE Pins Selection

Design of the demodulation filter affects the performance

of the power amplifier significantly. As a result, to ensure

proper operation of the overcurrent (OC) protection circuit

and meet the device THD+N specifications, the selection

of the inductors used in the output filter must be considered

according to the following. The rule is that the inductance

should remain stable within the range of peak current seen

at maximum output power and deliver at least 5 µH of

inductance at 15 A.

The protection mode is selected by shorting M1/M2 to

DREG or DGND according to Table 2.

Table 2. Protection Mode Selection

M1 M2

PROTECTION MODE

Autorecovery after errors (PMODE 0)

Latching shutdown on all errors (PMODE 1)

All protection systems disabled (PMODE 2)

Reserved

If this rule is observed, the TAS5112 does not have

distortion issues due to the output inductors and

overcurrent conditions do not occur due to inductor

saturation in the output filter.

The output configuration mode is selected by shorting the

M3 pin to DREG or DGND according to Table 3.

ꢀꢁ

ꢂ

ꢃ

ꢄꢄ

ꢅ

www.ti.com

SLES048C − JULY 2003 − REVISED MARCH 2004

Another parameter to be considered is the idle current loss

in the inductor. This can be measured or specified as

inductor dissipation (D). The target specification for

dissipation is less than 0.05.

THERMAL INFORMATION

The thermally augmented package provided with the

TAS5112 is designed to be interfaced directly to heatsinks

using a thermal interface compound (for example,

Wakefield Engineering type 126 thermal grease.) The

heatsink then absorbs heat from the ICs and couples it to

the local air. If the heatsink is carefully designed, this

process can reach equilibrium and heat can be continually

removed from the ICs. Because of the efficiency of the

TAS5112, heatsinks can be smaller than those required for

linear amplifiers of equivalent performance.

In general, 10-µH inductors suffice for most applications.

The frequency response of the amplifier is slightly altered

by the change in output load resistance; however, unless

tight control of frequency response is necessary (better

than 0.5 dB), it is not necessary to deviate from 10 µH.

The graphs in Figure 12 display the inductance vs current

characteristics of two inductors that are recommended for

use with the TAS5112.

is a system thermal resistance from junction to

ambient air. As such, it is a system parameter with roughly

the following components:

(the thermal resistance from junction to

case, or in this case the metal pad)

Thermal grease thermal resistance

Heatsink thermal resistance

INDUCTANCE

CURRENT

has been provided in the General Information

section.

DFB1310A

The thermal grease thermal resistance can be calculated

from the exposed pad area and the thermal grease

manufacturer’s area thermal resistance (expressed in

°C-in /W). The area thermal resistance of the example

DASL983XX−1023

thermal grease with a 0.002-inch thick layer is about 0.1

°C-in /W. The approximate exposed pad area is as

follows:

56-pin HTSSOP

0.045 in

Dividing the example thermal grease area resistance by

the surface area gives the actual resistance through the

thermal grease for both ICs inside the package:

56-pin HTSSOP

2.27 °C/W

I − Current − A

The thermal resistance of thermal pads is generally

considerably higher than a thin thermal grease layer.

Thermal tape has an even higher thermal resistance.

Neither pads nor tape should be used with either of these

two packages. A thin layer of thermal grease with careful

clamping of the heatsink is recommended. It may be

difficult to achieve a layer 0.001-inch thick or less, so the

modeling below is done with a 0.002-inch thick layer,

which may be more representative of production thermal

grease thickness.

Figure 12. Inductance Saturation

The selection of the capacitor that is placed across the

output of each inductor (C2 in Figure 11) is simple. To

complete the output filter, use a 0.47-µF capacitor with a

voltage rating at least twice the voltage applied to the

output stage (PVDD).

Heatsink thermal resistance is generally predicted by the

heatsink vendor, modeled using a continuous flow

dynamics (CFD) model, or measured.

This capacitor should be a good quality polyester dielectric

such as a Wima MKS2-047ufd/100/10 or equivalent.

Thus, for a single monaural IC, the system R

= R

thermal-grease resistance + heatsink resistance.

In order to minimize the EMI effect of unbalanced ripple

loss in the inductors, 0.1-µF 50-V SMD capacitors (X7R or

better) (C1A and C1B in Figure 11) should be added from

the output of each inductor to ground.

Table 4, Table 5, and Table 6 indicate modeled

parameters for one or two TAS5112 ICs on a single

heatsink. The final junction temperature is set at 110°C in

www.ti.com

ꢀꢁ ꢂꢃ ꢄꢄꢅ

SLES048C − JULY 2003 − REVISED MARCH 2004

all cases. It is assumed that the thermal grease is 0.002

inch thick and that it is similar in performance to Wakefield

Type 126 thermal grease. It is important that the thermal

grease layer is ≤0.002 inches thick and that thermal pads

or tape are not used in the pad-to-heatsink interface due

to the high power density that results in these extreme

power cases.

Table 6. Case 2A (2 × 60 W Unclipped Into 6 Ω,

(1)

Channels in Separate IC Packages)

56-Pin HTSSOP

Ambient temperature

25°C

Power to load (per channel)

Power dissipation per channel

60 W (10% THD)

5.4 W

6.1°C, note 2 ×

channel dissipation

Delta T inside package

Table 4. Case 1 (2 × 50 W Unclipped Into 6 Ω,

22.3°C, note 2 ×

channel dissipation

Delta T through thermal grease

(1)

Both Channels in Same IC)

Required heatsink thermal resistance

Junction temperature

5.3°C/W

56-Pin HTSSOP

110°C

Ambient temperature

Power to load (per channel)

Power dissipation

25°C

System R

θJA

15.9°C/W

85°C

50 W (unclipped)

4.5 W

* power dissipation

θJA

Junction temperature

85°C + 25°C = 110°C

10.2°C, note 2 ×

channel dissipation

(1)

Delta T inside package

In this case, the power is also separated into two packages, but

overdriving causes clipping to 10% THD. In this case, the high

power requires extreme care in attachment of the heatsink to

ensure that the thermal grease layer is ≤ 0.002 inches thick. Note

that this power level should not be attempted with both channels in

a single IC because of the high power density through the thermal

grease layer.

37.1°C, note 2 ×

channel dissipation

Delta T through thermal grease

Required heatsink thermal resistance

Junction temperature

4.2°C/W

110°C

System R

θJA

19°C/W

* power dissipation

85°C

θJA

Junction temperature

85°C + 25°C = 110°C

(1)

This case represents a stereo system with only one package. See

Case 2 and Case 2A if doing a full-power, 2-channel test in a

multichannelsystem.

Table 5. Case 2 (2 × 50 W Unclipped Into 6 Ω,

(1)

Channels in Separate Packages)

Thermal

Pad

8,20 mm

7,20 mm

56-Pin HTSSOP

Ambient temperature

25°C

Power to load (per channel)

Power dissipation

50 W (unclipped)

4.5 W

Delta T inside package

5.1°C

Delta T through thermal grease

Required heatsink thermal resistance

Junction temperature

18.6°C

6.9°C/W

110°C

System R

θJA

19°C/W

* power dissipation

85°C

θJA

Junction temperature

85°C + 25°C = 110°C

3,90 mm

2,98 mm

(1)

In this case, the power is separated into two packages. Note that

this allows a considerably smaller heatsink because twice as much

area is available for heat transfer through the thermal grease. For

this reason, separating the stereo channels into two ICs is

recommended in full-power stereo tests made on multichannel

systems.

ꢀꢁ

ꢂ

ꢃ

ꢄꢄ

ꢅ

www.ti.com

SLES048C − JULY 2003 − REVISED MARCH 2004

CLICK AND POP REDUCTION

REFERENCES

TI modulators feature a pop and click reduction system

that controls the timing when switching starts and stops.

1. TAS5000 Digital Audio PWM Processor data

manual—TI (SLAS270)

Going from nonswitching to switching operation causes a

spectral energy burst to occur within the audio bandwidth,

which is heard in the speaker as an audible click, for

instance, after having asserted RESET LH during a

system start-up.

2. True Digital Audio Amplifier TAS5001 Digital Audio

PWM Processor data sheet—TI (SLES009)

3. True Digital Audio Amplifier TAS5010 Digital Audio

PWM Processor data sheet—TI (SLAS328)

To make this system work properly, the following design

rules must be followed when using the TAS5112 back end:

4. True Digital Audio Amplifier TAS5012 Digital Audio

PWM Processor data sheet—TI (SLES006)

The relative timing between the PWM_AP/M_x

signals and their corresponding VALID_x signal

should not be skewed by inserting delays,

because this increases the audible amplitude

level of the click.

5. TAS5026 Six-Channel Digital Audio PWM

Processor data manual—TI (SLES041)

6. TAS5036A Six-Channel Digital Audio PWM

Processor data manual—TI (SLES061)

The output stage must start switching from a

fully discharged output filter capacitor. Because

the output stage prior to operation is in the

high-impedance state, this is done by having a

passive pulldown resistor on each speaker

output to GND (see Typical System

Configuration).

7. TAS3103 Digital Audio Processor With 3D Effects

data manual—TI (SLES038)

8. Digital Audio Measurements application report—TI

(SLAA114)

9. PowerPAD Thermally Enhanced Package

technical brief—TI (SLMA002)

Other things that can affect the audible click level:

10. System Design Considerations for True Digital

Audio Power Amplifiers application report—TI

(SLAA117)

The spectrum of the click seems to follow the

speaker impedance vs. frequency curve—the

higher the impedance, the higher the click

energy.

Crossover filters used between woofer and

tweeter in a speaker can have high impedance

in the audio band, which should be avoided if

possible.

Another way to look at it is that the speaker impulse

response is a major contributor to how the click energy is

shaped in the audio band and how audible the click will be.

The following mode transitions feature click and pop

reduction.

CLICK AND

POP REDUCED

STATE

(1)

Normal

→

Mute

Yes

(1)

Mute

Normal

Error recovery

(ERRCVY)

(1)

Normal

→

Yes

(1)

Error recovery

→

Normal

Yes

(1)

Normal

Hard Reset

(1)

Normal

Hard Reset

Yes

(1)

Normal = switching

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

TAS5112DFD

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

NRND

HTSSOP

DFD

Green (RoHS

& no Sb/Br)

CU NIPDAU

Call TI

Level-3-260C-168 HR

Call TI

TAS5112

TAS5112DFDG4

TAS5112DFDR

TAS5112DFDRG4

NRND

DFD

Green (RoHS

& no Sb/Br)

0 to 70

TAS5112

2000

Green (RoHS

& no Sb/Br)

0 to 70

TBD

0 to 70

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TAS5112DFDR

HTSSOP

DFD

2000

330.0

24.4

8.6

15.6

1.8

12.0

24.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP DFD 56

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 45.0

TAS5112DFDR

2000

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

Video and Imaging

www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

www.ti-rfid.com

www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TAS5112DFDRG4 [TI]

相关型号：

TAS5112_16

TAS5121

TAS5121A

TAS5121DKD

TAS5121DKDE4

TAS5121DKDR

TAS5121DKDRE4

TAS5121I

TAS5121IDKD

TAS5121IDKDE4

TAS5121IDKDR

TAS5121IDKDRE4