TAS5186DDVR [TI]
6-Channel, 210-W, Digital-Amplifier Power Stage; 6通道， 210 -W ，数字放大器功率级
| 型号： | TAS5186DDVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 6-Channel, 210-W, Digital-Amplifier Power Stage |
| 文件： | 总17页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
TAS5186
www.ti.com
SLES136–MAY 2005
6-Channel, 210-W, Digital-Amplifier Power Stage
The TAS5186 requires only simple passive demodu-
lation filters on its outputs to deliver high-quality,
high-efficiency audio amplification. The efficiency of
the TAS5186 is greater than 90% when driving 6-Ω
satellites and a 3-Ω subwoofer speaker.
FEATURES
•
Total Output Power @ 10% THD+N
– 5×30 W @ 6Ω + 1×60 W @ 3Ω
105-dB SNR (A-Weighted)
•
•
•
< 0.05% THD+N @ 1 W
The TAS5186 has an innovative protection system
integrated on-chip, safeguarding the device against a
wide range of fault conditions that could damage the
system. These safeguards are short-circuit protection,
overload protection, undervoltage protection, and
overtemperature protection. The TAS5186 has a new
proprietary current-limiting circuit that reduces the
possibility of device shutdown during high-level music
transients. A new programmable overcurrent detector
allows the use of lower-cost inductors in the demodu-
lation output filter.
Power Stage Efficiency > 90% Into
Recommended Loads (SE)
•
Integrated Self-Protection Circuits
– Undervoltage
– Overtemperature
– Overload
– Short Circuit
•
Integrated Active-Bias Control to Avoid DC
Pop
TOTAL HARMONIC DISTORTION + NOISE
vs
•
•
Thermally Enhanced 44-pin HTSSOP Package
OUTPUT POWER
EMI-Compliant When Used With
Recommended System Design
20
PVDD = 40 V
10
T
C
= 75°C
APPLICATIONS
•
DVD Receiver
•
Home Theater in a Box
1
DESCRIPTION
6 Ω Satellite
The TAS5186 is a high-performance, six-channel,
digital-amplifier power stage with an improved protec-
tion system. The TAS5186 is capable of driving a
6-Ω, single-ended load up to 30 W per each
0.1
front/satellite channel and
a 3-Ω, single-ended
subwoofer greater than 60 W at 10% THD+N per-
formance.
3 Ω Subwoofer
0.01
A low-cost, high-fidelity audio system can be built
using a TI chipset comprising a modulator (e.g.,
TAS5086) and the TAS5186. This device does not
require power-up sequencing because of the internal
power-on reset.
1
10
70
P
O
– Output Power – W
G012
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD, PurePath Digital are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TAS5186
www.ti.com
SLES136–MAY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
TERMINAL ASSIGNMENT
The TAS5186 is available in a thermally enhanced 44-pin HTSSOP PowerPAD™ package. The heat slug is
located on the top side of the device for convenient thermal coupling to a heatsink.
DDV PACKAGE
(TOP VIEW)
PGND_EF
PWM_F
GVDD_DEF
VDD
BST_F
PVDD_F
OUT_F
PGND_EF
OUT_E
PVDD_E
BST_E
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
PWM_E
PWM_D
RESET
M3
M2
M1
GND
AGND
5
6
7
BST_D
8
PVDD_D
OUT_D
PGND_D
PGND_C
OUT_C
PVDD_C
BST_C
BST_B
PVDD_B
OUT_B
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VREG
OC_ADJ
SD
OTW
PWM_C
PWM_B
PWM_A
GVDD_ABC
BST_BIAS
OUT_BIAS
PGND_AB
OUT_A
PVDD_A
BST_A
P0016-01
2
TAS5186
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SLES136–MAY 2005
GENERAL INFORMATION (continued)
TERMINAL FUNCTIONS
TERMINAL
TYPE(1)
DESCRIPTION
NAME
AGND
NO.
12
23
29
21
30
37
38
44
11
20
3
P
P
P
P
P
P
P
P
P
P
P
I
Analog ground
BST_A
BST_B
BST_BIAS
BST_C
BST_D
BST_E
BST_F
HS bootstrap supply (BST), capacitor to OUT_A required
HS bootstrap supply (BST), external capacitor to OUT_B required
BIAS bootstrap supply, external capacitor to OUT_BIAS required
HS bootstrap supply (BST), external capacitor to OUT_C required
HS bootstrap supply (BST), external capacitor to OUT_D required
HS bootstrap supply (BST), external capacitor to OUT_E required
HS bootstrap supply (BST), external capacitor to OUT_F required
Chip ground
GND
GVDD_ABC
GVDD_DEF
M1
Gate drive voltage supply
Gate drive voltage supply
10
9
Mode selection pin
M2
I
Mode selection pin
M3
8
I
Mode selection pin
OC_ADJ
OTW
14
16
25
27
22
32
35
40
42
26
33
34
1, 41
24
28
31
36
39
43
19
18
17
6
O
O
O
O
O
O
O
O
O
P
P
P
P
P
P
P
P
P
P
I
Overcurrent threshold programming pin, resistor to ground required
Overtemperature warning open-drain output signal, active-low
Output, half-bridge A, satellite
OUT_A
OUT_B
OUT_BIAS
OUT_C
OUT_D
OUT_E
OUT_F
PGND_AB
PGND_C
PGND_D
PGND_EF
PVDD_A
PVDD_B
PVDD_C
PVDD_D
PVDD_E
PVDD_F
PWM_A
PWM_B
PWM_C
PWM_D
PWM_E
PWM_F
RESET
SD
Output, half-bridge B, satellite
BIAS half-bridge output pin
Output, half-bridge C, subwoofer
Output, half-bridge D, satellite
Output, half-bridge E, satellite
Output, half-bridge F, satellite
Power ground
Power ground
Power ground
Power ground
Power-supply input for half-bridge A
Power-supply input for half-bridge B
Power-supply input for half-bridge C
Power-supply input for half-bridge D
Power-supply input for half-bridge E
Power-supply input for half-bridge F
PWM input signal for half-bridge A
PWM input signal for half-bridge B
PWM input signal for half-bridge C
PWM input signal for half-bridge D
PWM input signal for half-bridge E
PWM input signal for half-bridge F
Reset signal (active-low logic)
I
I
I
5
I
2
I
7
I
15
4
O
P
O
Shutdown open-drain output signal, active-low
Power supply for digital voltage regulator
Digital regulator supply filter pin, output
VDD
VREG
13
(1) I = input; O = output; P = power
3
TAS5186
www.ti.com
SLES136–MAY 2005
Table 1. MODE Selection Pins
MODE PINS(1)
MODE
M2
0
M3
0
NAME
DESCRIPTION
2.1 mode
5.1 mode
Reserved
Channels A, B, and C enabled; channels D, E, and F disabled
All channels enabled
0
1
1
0/1
(1) M1 must always be connected to ground. 0 indicates a pin connected to GND; 1 indicates a pin connected to VREG.
PACKAGE HEAT DISSIPATION RATINGS(1)
PARAMETER
TAS5186DDV
R
θJC (°C/W)—1 satellite (sat.) FET only
10.3
5.2
R
θJC (°C/W)—1 subwoofer (sub.) FET only
θJC (°C/W)—1 sat. half-bridge
θJC (°C/W)—1 sub. half-bridge
R
5.2
R
2.6
RθJC (°C/W)—5 sat. half-bridges + 1 sub.
1.74
Typical pad area(2)
34.9 mm2
(1) JC is junction-to-case, CH is case-to-heatsink.
(2)
R
R
θCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The
θCH with this condition is typically 2°C/W for this package.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
TAS5186
VDD to AGND
–0.3 V to 13.2 V
–0.3 V to 13.2 V
–0.3 V to 50 V
–0.3 V to 50 V
–0.3 V to 63.2 V
–0.3 V to 4.2 V
–0.3 V to 0.3 V
–0.3 V to 0.3 V
–0.3 V to 0.3 V
–0.3 V to 4.2 V
–0.3 V to 7 V
0 to 125°C
GVDD_X to AGND
(2)
PVDD_X to PGND_X
(2)
OUT_X to PGND_X
(2)
BST_X to PGND_X
VREG to AGND
PGND_X to GND
PGND_X to AGND
GND to AGND
PWM_X, OC_ADJ, M1, M2, M3 to AGND
RESET, SD, OTW to AGND
Maximum operating junction temperature range (TJ )
Storage temperature
–40°C to 125°C
260°C
Lead temperature – 1,6 mm (1/16 inch) from case for 10 seconds
Minimum PWM pulse duration, low
30 ns
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
4
TAS5186
www.ti.com
SLES136–MAY 2005
TYPICAL SYSTEM DIAGRAM
21
BST_BIAS
33 nF
680 Ω
22
OUT_BIAS
3
20
4
PVDD
12 V
GVDD_DEF
GVDD_ABC
VDD
1 µF
0.1 µF
43
44
42
PVDD_F
BST_F
OUT_F
+
0.47 µF
1 µF
SAT
270 µF
+
10 µF
33 nF
22 µH
330 Ω
0.1 µF
41
1
270 µF
PGND_EF
PGND_EF
1 µF
13
14
12
VREG
0.1 µF
0.1 µF
39
38
40
PVDD_E
BST_E
OUT_E
+
OC_ADJ
AGND
0.47 µF
SAT
15 kΩ
270 µF
33 nF
22 µH
330 Ω
270 µF
10
9
1 µF
M1
0.1 µF
36
37
35
34
M2
PVDD_D
BST_D
+
11
0.47 µF
GND
TAS5186
SAT
270 µF
OUT_D
33 nF
22 µH
330 Ω
PGND_D
270 µF
1 µF
2
5
0.1 µF
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM_F
PWM_E
PWM_D
PWM_C
PWM_B
PWM_A
31
30
32
33
PVDD_C
BST_C
+
0.47 µF
6
SUB
1000 µF
OUT_C
17
18
19
PurePath
Digital
Modulator
TAS5086
33 nF
22 µH
330 Ω
PGND_C
1000 µF
1 µF
0.1 µF
28
29
27
PVDD_B
BST_B
OUT_B
+
7
8
0.47 µF
RESET
M3
VALID2
VALID1
SAT
270 µF
33 nF
330 Ω
22 µH
15
16
26
270 µF
SD
PGND_AB
1 µF
0.1 µF
OTW
24
23
25
PVDD_A
BST_A
OUT_A
+
0.47 µF
SAT
To µP
270 µF
33 nF
22 µH
330 Ω
270 µF
1 µF
S0061-01
PurePath Digital™
5
TAS5186
www.ti.com
SLES136–MAY 2005
FUNCTIONAL BLOCK DIAGRAM
Undervoltage
Protection
OTW
SD
VDD
Internal Pullup
Resistors to VREG
Power On
Reset
VREG
VREG
Protection
M1
M2
M3
and
I/O Logic
AGND
GND
Temperature
Sense
Overload
Protection
RESET
I
OC_ADJ
Sense
GVDD_DEF
BST_F
PVDD_F
OUT_F
PWM
Receiver
Gate
Drive
PWM_F
PWM_E
PWM_D
Control
Control
Control
Timing
Timing
Timing
PGND_EF
BST_E
PVDD_E
OUT_E
PWM
Receiver
Gate
Drive
PGND_EF
BST_D
PVDD_D
OUT_D
PGND_D
PWM
Receiver
Gate
Drive
GVDD_ABC
BST_C
PVDD_C
OUT_C
PGND_C
PWM
Receiver
Gate
Drive
PWM_C
PWM_B
PWM_A
Control
Control
Control
Control
Timing
Timing
Timing
Timing
BST_B
PVDD_B
OUT_B
PWM
Receiver
Gate
Drive
PGND_AB
BST_A
PVDD_A
OUT_A
PWM
Receiver
Gate
Drive
BST_BIAS
OUT_BIAS
B0034-01
Gate
Drive
6
TAS5186
www.ti.com
SLES136–MAY 2005
RECOMMENDED OPERATING CONDITIONS
MIN
0
TYP
MAX UNIT
PVDD_X
GVDD
VDD
Half-bridge supply, SE
DC supply voltage at pin(s)
DC voltage at pin(s)
40
13.2
13.2
V
V
V
Gate drive and guard ring supply voltage
Digital regulator supply
10.8
10.8
12
12
DC supply voltage at pin
Any value of RPU,EXT within
recommended range
VPU
Pullup voltage supply
3
4
5
6
5.5
V
Ω
Resistive load impedance, satellite
channels(1)
Recommended demodulation filter
RL,SAT
RL,SUB
Loutput
Resistive load impedance, subwoofer
channel
Recommended demodulation filter
2.25
5
3
Ω
Minimum output inductance under
short-circuit condition
Demodulation filter inductance
22
µH
Coutput,sat
Coutput,sub
FPWM
Demodulation filter capacitance
Demodulation filter capacitance
PWM frame rate
1
0.47
384
µF
µF
192
432
kHz
(1) Load impedance outside range listed might cause shutdown due to OLP, OTE, or NLP.
AUDIO SPECIFICATION
PVDD_X = 40 V, GVDD = 12 V, audio frequency = 1 kHz, AES17 measurement filter, FPWM = 384 kHz, case temperature =
75°C. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of
97%. All performance is in accordance with the foregoing specifications and recommended operating conditions unless
otherwise specified.
PARAMETER
CONDITIONS
RL = 6 Ω, 10% THD, clipped input signal
RL = 8 Ω, 10% THD, clipped input signal
RL = 6 Ω, 0 dBFS, unclipped input signal
RL = 8 Ω, 0 dBFS, unclipped input signal
RL = 3 Ω, 10% THD, clipped input signal
RL = 4 Ω, 10% THD, clipped input signal
RL = 3 Ω, 0 dBFS, unclipped input signal
RL = 4 Ω, 0 dBFS, unclipped input signal
RL = 6 Ω, PO = 25 W
MIN
TYP
30
MAX
UNIT
25
PO,sat
Power output per satellite channel
W
25
20
60
52
PO,sub
Power output, subwoofer
W
50
40
0.3%
0.03%
0.5%
0.03%
55
Total harmonic distortion + noise,
satellite
RL = 6 Ω, 1 W
THD + N
RL = 3 Ω, PO = 50 W
Total harmonic distortion + noise,
subwoofer
RL = 3 Ω, 1 W
Output integrated noise, satellite
Output integrated noise, subwoofer
System signal-to-noise ratio
Dynamic range(1)
A-weighted
Vn
µV
A-weighted
60
SNR
DNR
A-weighted
105
105
8
dB
dB
W
A-weighted, –60 dBFs input signal
PO = 0 W, all channels running 5.1 mode(2)
PO = 0 W, 2.1 mode
Power dissipation due to idle losses
(IPVDDX)
Pidle
4
W
(1) SNR is calculated relative to 0-dBFS input level.
(2) Actual system idle losses are affected by core losses of output inductors.
7
TAS5186
www.ti.com
SLES136–MAY 2005
ELECTRICAL CHARACTERISTICS
FPWM = 384 kHz, GVDD = 12 V, VDD = 12 V, TC (case temperature) = 25°C, unless otherwise noted. All performance is in
accordance with recommended operating conditions, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
VREG
IVDD
Voltage regulator, only used as reference node
VDD supply current
VDD = 12 V
3
3.3
7
3.6
20
16
22
3
V
Operating, 50% duty cycle
Idle, reset mode
mA
6
50% duty cycle
5
IGVDD_X
IPVDD_X
Gate supply current per half-bridge
Half-bridge idle current
mA
mA
Idle, reset mode
1
50% duty cycle, without output filter or load, 5.1
mode
180
50% duty cycle, without output filter or load, 2.1
mode
100
OUTPUT STAGE MOSFETs
RDSon, LS Sat
RDSon, HS Sat
RDson, LS Sub
RDson, HS Sub
I/O PROTECTION
VUVP, G
Drain-to-source resistance, low side, satellite
TJ = 25°C, includes metallization resistance
TJ = 25°C, includes metallization resistance
TJ = 25°C, includes metallization resistance
TJ = 25°C, includes metallization resistance
210
210
110
110
mΩ
mΩ
mΩ
mΩ
Drain-to-source resistance, high side, satellite
Drain-to-source resistance, low side, subwoofer
Drain-to-source resistance, high side, subwoofer
Undervoltage protection limit GVDD_X
Undervoltage protection hysteresis
Overtemperature warning
10
250
125
V
(1)
VUVP, hyst
mV
°C
OTW(1)
Temperature drop needed below OTW temp. for
OTW to be inactive after the OTW event
(1)
OTWhyst
25
155
25
°C
°C
°C
ms
A
OTE(1)
Overtemperature error
Temperature drop needed below OTE temp. for SD
to be released after the OTE event
(1)
OTEHYST
OLCP
Overload protection counter
1.25
Resistor programmable, high end,
Rocp = 15 kΩ
Overcurrent limit protection, sat.
5
IOC
Resistor programmable, high end,
Rocp = 15 kΩ
Overcurrent limit protection, sub.
8
A
IOCT
Overcurrent response time
210
ns
Rocp
OC programming resistor range
Resistor tolerance = 5%
15
2
kΩ
STATIC DIGITAL SPECIFICATION
VIH
High-level input voltage
PWM_X, M1, M2, M3, RESET
Static condition
V
VIL
Low-level input voltage
Input leakage current
0.8
80
ILEAK
–80
µA
OTW/SHUTDOWN (SD)
Internal pullup resistor to DREG (3.3 V) for SD and
RINT_PU
26
kΩ
OTW
Internal pullup resistor only
External pullup: 4.7-kΩ resistor to 5 V
IO = 4 mA
3
3.3
3.6
5
VOH
High-level output voltage
4.5
V
VOL
Low-level output voltage
Device fanout OTW, SD
0.2
30
0.4
FANOUT
No external pullup
Devices
(1) Specified by design.
8
TAS5186
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SLES136–MAY 2005
TYPICAL CHARACTERISTICS, 5.1 MODE
TOTAL HARMONIC DISTORTION + NOISE
TOTAL HARMONIC DISTORTION + NOISE
vs
vs
OUTPUT POWER
OUTPUT POWER
20
10
20
10
Satellite
PVDD = 40 V
Subwoofer
PVDD = 40 V
T
C
= 75°C
T = 75°C
C
1
1
6 Ω
3 Ω
4 Ω
0.1
0.1
8 Ω
0.01
0.01
1
10
40
1
10
70
P
O
– Output Power – W
P
O
– Output Power – W
G001
G002
Figure 1.
Figure 2.
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
SUPPLY VOLTAGE
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
70
65
60
55
50
45
40
35
30
25
20
15
10
5
Satellite
1 Channel
Subwoofer
1 Channel
T = 75°C
C
T
C
= 75°C
THD+N = 10%
THD+N = 10%
6 Ω
3 Ω
8 Ω
4 Ω
6
4
2
0
0
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
PVDD – Supply Voltage – V
PVDD – Supply Voltage – V
G003
G004
Figure 3.
Figure 4.
9
TAS5186
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SLES136–MAY 2005
TYPICAL CHARACTERISTICS, 5.1 MODE (continued)
OUTPUT POWER
vs
SUPPLY VOLTAGE
OUTPUT POWER
vs
SUPPLY VOLTAGE
55
50
45
40
35
30
25
20
15
10
5
28
Satellite
1 Channel
Subwoofer
1 Channel
T = 75°C
C
26
24
22
20
18
16
14
12
10
8
T
C
= 75°C
Unclipped Input Signal
Unclipped Input Signal
6 Ω
3 Ω
8 Ω
4 Ω
6
4
2
0
0
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
PVDD – Supply Voltage – V
PVDD – Supply Voltage – V
G005
G006
Figure 5.
Figure 6.
SYSTEM EFFICIENCY
vs
TOTAL OUTPUT POWER
SYSTEM POWER LOSS
vs
TOTAL OUTPUT POWER
100
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
5.1 Mode
R
R
= 8 Ω
= 4 Ω
L(SAT)
L(SUB)
PVDD = 40 V
= 25°C
T
C
R
R
= 6 Ω
= 3 Ω
L(SAT)
L(SUB)
R
R
= 6 Ω
= 3 Ω
L(SAT)
L(SUB)
R
R
= 8 Ω
= 4 Ω
L(SAT)
L(SUB)
5.1 Mode
PVDD = 40 V
T
C
= 25°C
0
0
20 40 60 80 100 120 140 160 180 200 220 240
0
20 40 60 80 100 120 140 160 180 200 220 240
P
O
– Total Output Power – W
P
O
– Total Output Power – W
G007
G008
Figure 7.
Figure 8.
10
TAS5186
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SLES136–MAY 2005
TYPICAL CHARACTERISTICS, 5.1 MODE (continued)
OUTPUT POWER
vs
CASE TEMPERATURE
OUTPUT POWER
vs
CASE TEMPERATURE
40
80
70
60
50
40
30
20
10
0
6 Ω
3 Ω
35
30
25
8 Ω
4 Ω
20
15
10
Satellite
1 Channel
Subwoofer
1 Channel
THD+N = 10%
5
0
THD+N = 10%
20 30 40
50 60
70 80
90 100 110
20 30 40 50 60
70 80
90 100 110
T
C
– Case Temperature – °C
T – Case Temperature – °C
C
G009
G010
Figure 9.
Figure 10.
AMPLITUDE
vs
FREQUENCY
0
Satellite
1 Channel
PVDD = 40 V
−10
−20
T
C
= 75°C
−30
−40
−50
−60
−70
−80
−90
−100
−110
−120
−130
−140
−150
0
2
4
6
8
10 12 14 16 18 20 22
f – Frequency – kHz
G011
Figure 11.
11
TAS5186
www.ti.com
SLES136–MAY 2005
THEORY OF OPERATION
decoupled with a 100-nF ceramic capacitor placed as
close as possible to each supply pin on the same
side of the PCB as the TAS5186. It is recommended
to follow the PCB layout of the TAS5186 reference
design. For additional information on the rec-
ommended power supply and required components,
see the application diagrams given in this data sheet.
POWER SUPPLIES
To facilitate system design, the TAS5186 needs only
a
12-V supply in addition to a typical 39-V
power-stage supply. An internal voltage regulator
provides suitable voltage levels for the digital and
low-voltage analog circuitry. Additionally, all circuitry
requiring a floating voltage supply, e.g., the high-side
gate drive, is accommodated by built-in bootstrap
circuitry requiring only a few external capacitors.
The 12-V supply should be powered from
a
low-noise, low-output-impedance voltage regulator.
Likewise, the 39-V power-stage supply is assumed to
have low output impedance and low noise. The
power-supply sequence is not critical due to the
internal power-on-reset circuit. Moreover, the
TAS5186 is fully protected against erroneous
power-stage turnon due to parasitic gate charging.
Thus, voltage-supply ramp rates (dv/dt) are typically
noncritical.
In order to provide outstanding electrical and acoustic
characteristics, the PWM signal path including gate
drive and output stage is designed as identical,
independent half-bridges. For this reason, each
half-bridge has separate bootstrap pins (BST_X) and
power-stage supply pins (PVDD_X). Furthermore, an
additional pin (VDD) is provided as power supply for
all common circuits. Although supplied from the same
12-V source, it is highly recommended to separate
GVDD_X and VDD on the printed-circuit board (PCB)
by RC filters (see application diagram for details).
These RC filters provide the recommended
high-frequency isolation. Special attention should be
paid to placing all decoupling capacitors as close to
their associated pins as possible. In general, induct-
ance between the power-supply pins and decoupling
capacitors must be avoided. (See reference board
documentation for additional information.)
SYSTEM POWER-UP/DOWN SEQUENCE
The TAS5186 does not require a power-up sequence.
The outputs of the H-bridge remain in
a
high-impedance state until the gate-drive supply volt-
age (GVDD_X) and VDD voltage are above the
undervoltage protection (UVP) voltage threshold (see
the Electrical Characteristics section of this data
sheet). Although not specifically required, it is rec-
ommended to hold RESET in a low state while
powering up the device.
When the TAS5186 is being used with TI PWM
modulators such as the TAS5086, no special atten-
tion to the state of RESET is required, provided that
the chipset is configured as recommended.
For a properly functioning bootstrap circuit, a small
ceramic capacitor must be connected from each
bootstrap pin (BST_X) to the power-stage output pin
(OUT_X). When the power-stage output is low, the
bootstrap capacitor is charged through an internal
Powering Down
diode
connected
between
the
gate-drive
power-supply pin (GVDD_X) and the bootstrap pin.
When the power-stage output voltage is high, the
bootstrap capacitor voltage is shifted above the
output voltage potential and thus provides a suitable
voltage supply for the high-side gate driver. In an
application with PWM switching frequencies in the
range 352 kHz to 384 kHz, it is recommended to use
33-nF ceramic capacitors, size 0603 or 0805, for the
bootstrap capacitor. These 33-nF capacitors ensure
sufficient energy storage, even during minimal PWM
duty cycles, to keep the high-side power stage FET
(LDMOS) fully started during all of the remaining part
of the PWM cycle. In an application running at a
reduced switching frequency, generally 250 kHz to
192 kHz, the bootstrap capacitor might need to be
increased in value. Special attention should be paid
to the power-stage power supply; this includes
component selection, PCB placement and routing. As
indicated, each half-bridge has independent
power-stage supply pins (PVDD_X). For optimal elec-
trical performance, EMI compliance, and system re-
liability it is important that each PVDD_X pin is
The TAS5186 does not require a power-down se-
quence. The device remains fully operational as long
as the gate-drive supply (GVDD_X) voltage and VDD
voltage are above the undervoltage protection (UVP)
threshold level (see the Electrical Characteristics
section of this data sheet). Although not specifically
required, it is a good practice to hold RESET low
during power down, thus preventing audible artifacts
including pops and clicks
When the TAS5186 is being used with TI PWM
modulators such as the TAS5086, no special atten-
tion to the state of RESET is required, provided that
the chipset is configured as recommended.
Error Reporting
The SD and OTW pins are both active-low,
open-drain outputs. Their function is for protec-
tion-mode signaling to a PWM controller or other
system-control device.
12
TAS5186
www.ti.com
SLES136–MAY 2005
Any fault resulting in device shutdown is signaled by
the SD pin going low. Likewise, OTW goes low when
the device junction temperature exceeds 125°C (see
the following table).
two protection systems. The first protection system
controls the power stage in order to prevent the
output current from further increasing. I.e., it performs
a current-limiting function rather than prematurely
shutting down during combinations of high-level mu-
sic transients and extreme speaker load-impedance
drops. If the high-current situation persists, i.e., the
power stage is being overloaded, a second protection
system triggers a latching shutdown, resulting in the
power stage being set in the high-impedance (Hi-Z)
state.
SD OTW
DESCRIPTION
0
0
Overtemperature (OTE) or overload (OLP) or
undervoltage (UVP)
0
1
1
0
Overload (OLP) or undervoltage (UVP)
Overtemperature warning. Junction temperature
higher than 125°C, typical
For added flexibility, the OC threshold is
programmable within a limited range using a single
external resistor connected between the OC_ADJ pin
and AGND.
1
1
Normal operation. Junction temperature lower than
125°C, typical
It should be noted that asserting RESET low forces
the SD and OTW signals high independently of faults
being present. It is recommended to monitor the
OTW signal using the system microcontroller and to
respond to an overtemperature warning signal by,
e.g., turning down the volume to prevent further
heating of the device that would result in device
shutdown (OTE). To reduce external component
count, an internal pullup resistor to 3.3 V is provided
on both the SD and OTW outputs. Level compliance
for 5-V logic can be obtained by adding external
pullup resistors to 5 V (see the Electrical Character-
istics section of this data sheet for further specifi-
cations).
OC-Adjust Resistor Values
Maximum Current Before OC
Occurs (A)
(kΩ)
15
18
5 (sat.), 8 (sub.)
4.5 (sat.), 7.5 (sub.)
It should be noted that
a properly functioning
overcurrent detector assumes the presence of a
properly designed demodulation filter at the
power-stage output. Short-circuit protection is not
provided directly at the output pins of the power stage
but only on the speaker terminals (after the demodu-
lation filter). It is required to follow certain guidelines
when selecting the OC threshold and an appropriate
demodulation inductor.
Device Protection System
•
For the lowest-cost bill of materials in terms of
component selection, the OC threshold current
should be limited, considering the power output
requirement and minimum load impedance.
Higher-impedance loads require a lower OC
threshold.
The demodulation filter inductor must retain at
least 5 µH of inductance at twice the OC
threshold setting.
The TAS5186 contains advanced protection circuitry
carefully designed to facilitate system integration and
ease of use, as well as safeguarding the device from
permanent failure due to a wide range of fault
conditions such as short circuit, overload, and
undervoltage. The TAS5186 responds to a fault by
•
immediately setting the power stage in
a
high-impedance state (Hi-Z) and asserting the SD pin
low. In situations other than overload, the device
automatically recovers when the fault condition has
been removed, e.g., the supply voltage has
increasedor the temperature has dropped. For
highest possible reliability, recovering from an over-
load fault requires external reset of the device no
sooner than 1 second after the shutdown (see the
Device Reset section of this data sheet).
Most inductors have decreasing inductance with in-
creasing temperature and increasing current
(saturation). To some degree, an increase in tem-
perature naturally occurs when operating at high
output currents, due to inductor core losses and the
dc resistance of the inductor copper winding. A
thorough analysis of inductor saturation and thermal
properties is strongly recommended.
Setting the OC threshold too low might cause issues
such as lack of output power and/or unexpected
shutdowns due to sensitive overload detection.
OVERCURRENT (OC) PROTECTION WITH
CURRENT LIMITING AND OVERLOAD DE-
TECTION
In general, it is recommended to follow closely the
external component selection and PCB layout as
given in the application section.
The device has independent, fast-reacting current
detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage
FETs. See the following table for OC-adjust resistor
values. The detector outputs are closely monitored by
13
TAS5186
www.ti.com
SLES136–MAY 2005
Overtemperature Protection
ABC can pre-charge the dc-blocking element in the
audio path, i.e., split-cap capacitors or series capaci-
tor, to the desired potential before switching is started
on the PWM outputs. (For recommended configur-
ation, see the typical application schematic included
in this data sheet).
The TAS5186 has a two-level temperature-protection
system that asserts an active-low warning signal
(OTW) when the device junction temperature ex-
ceeds 125°C (typical), and If the device junction
temperature exceeds 155°C (typical), the device is
put into thermal shutdown, resulting in all half-bridge
outputs being set in the high-impedance state (Hi-Z)
and SD being asserted low.
The start-up sequence can be controlled through
sequencing the M3 and RESET pins according to
Table 2 and Table 3.
Table 2. 5.1 Mode—All Output Channels Active
UNDERVOLTAGE PROTECTION (UVP) AND
POWER-ON RESET (POR)
M3 RESET OUT_BIAS OUT_A, OUT_D,
_B, _C _E, _F
COMMENT
The UVP and POR circuits of the TAS5186 fully
protect the device in any power-up/down and
brownout situation. While powering up, the POR
circuit resets the overload circuit (OLP) and ensures
that all circuits are fully operational when the
GVDD_X and VDD supply voltages reach 10 V
(typical). Although GVDD_X and VDD are indepen-
dently monitored, a supply voltage drop below the
UVP threshold on any VDD or GVDD_X pin results in
all half-bridge outputs immediately being set in the
high-impedance (Hi-Z) state and SD being asserted
low. The device automatically resumes operation
when all supply voltages have increased above the
UVP threshold.
0
1
1
0
0
1
Hi-Z
Hi-Z
Hi-Z
All outputs dis-
abled, nothing is
switching.
Active
Hi-Z
Hi-Z
Hi-Z
OUT_BIAS en-
abled, all other
outputs disabled
Active
Active
OUT_BIAS dis-
abled, all other
outputs
switching
Table 3. 2.1 Mode—Only Output Channels A, B,
and C Active
M3 RESET OUT_BIAS OUT_A, OUT_D,
_B, _C _E, _F
COMMENT
DEVICE RESET
0
1
0
0
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
All outputs dis-
abled, nothing is
switching.
When RESET is asserted low, the output FETs in all
half-bridges are forced into a high-impedance (Hi-Z)
state.
Active
Hi-Z
Hi-Z
OUT_BIAS en-
abled, all other
outputs disabled
Asserting the RESET input low removes any fault
information to be signaled on the SD output, i.e., SD
is forced high.
Active
OUT_BIAS dis-
abled, all other
outputs
A rising-edge transition on the RESET input allows
the device to resume operation after an overload
fault.
switching
When the TAS5186 is used with the TAS5086 PWM
modulator, no special attention to start-up sequencing
is required, provided that the chipset is configured as
recommended.
ACTIVE-BIAS CONTROL (ABC)
Audible pop noises are often associated with
single-rail, single-ended power stages at power-up or
at the start of switching. This commonly known
problem has been virtually eliminated by incorpor-
ating a proprietary active-bias control circuitry as part
of the TAS5186 feature set. By the use of only a few
passive external components (typically resistors), the
14
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2005
PACKAGING INFORMATION
Orderable Device
TAS5186DDV
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTSSOP
DDV
44
44
44
44
35 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TAS5186DDVG4
TAS5186DDVR
TAS5186DDVRG4
HTSSOP
HTSSOP
HTSSOP
DDV
DDV
DDV
35 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TAS5186DKD
PREVIEW
PREVIEW
SSOP
SSOP
DKD
DKD
44
44
TBD
TBD
Call TI
Call TI
Call TI
Call TI
TAS5186DKDR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
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dataconverter.ti.com
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www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
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www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
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Copyright 2005, Texas Instruments Incorporated
相关型号：
TAS5342ADDV
100-W stereo, 200-W mono, 0- to 34-V supply, PWM input open loop Class-D audio amplifier 44-HTSSOP 0 to 70
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