TAS5404-Q1 [TI]
具有 I2C 诊断和负载突降保护功能的汽车类 26W、4 通道、6V 至 18V 模拟单端输入 D 类音频放大器;
| 型号： | TAS5404-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C 诊断和负载突降保护功能的汽车类 26W、4 通道、6V 至 18V 模拟单端输入 D 类音频放大器 放大器 音频放大器 |
| 文件： | 总47页 (文件大小：2780K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TAS5404-Q1
SLOS918A –AUGUST 2015–REVISED OCTOBER 2015
TAS5404-Q1: 26-W Analog Single-Ended Input 4-Channel Class-D Amp with Load Dump
Protection and I2C Diagnostics
1 Features
2 Applications
OEM or retail head units where feature densities
and system configurations require high efficiency
in the audio power amplifier.
1
•
•
•
•
TAS5404-Q1 – Single-Ended Input
Four-Channel Class-D Power Amplifier
Four Analog Inputs, Four BTL Power Outputs
Typical Output Power at 10% THD+N
3 Description
–
–
26 W/Ch Into 4 Ω at 14.4 V
45 W/Ch Into 2 Ω at 14.4 V
The TAS5404-Q1 device is a four-channel class-D
audio amplifier designed for use in automotive head
units. The TAS5404-Q1 device provides four
channels at 20 W continuously into 4 Ω at less than
1% THD+N from a 14.4-Vdc supply when used with
the application circuit. The input is configured as an
analog single-ended interface. The patented PWM
topology of the device provides dramatic
improvements in efficiency and audio performance
over traditional linear amplifier solutions. The
improvement in efficiency and audio performance
reduces the power dissipated by the amplifier by a
factor of ten under typical music playback conditions.
The device incorporates all the required functions
required by the OEM application. The built-in load
diagnostic functions for detecting and diagnosing
disconnected speakers help reduce test time during
the manufacturing process.
•
Channels Can Be Paralleled (PBTL) for High-
Current Applications
•
•
THD+N < 0.02%, 1 kHz, 1 W Into 4 Ω
Patented Pop-and-Click-Reduction Technology
–
–
Soft Muting With Gain Ramp Control
Common-Mode Ramping
•
•
•
•
Patented AM Interference Avoidance
Patented Cycle-by-Cycle Current Limit
75dB PSRR
Four-Address I2C Serial Interface for Device
Configuration and Control
•
•
Channel Gains: 12 dB, 20 dB, 26 dB, 32 dB
Load Diagnostic Functions:
Device Information(1)
–
–
–
Output Open and Shorted Load
Output-to-Power and Output-to-Ground Shorts
Patented Tweeter Detection
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TAS5404-Q1
HTQFP (64)
14.00 mm × 14.00 mm
•
Protection and Monitoring Functions:
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
–
–
–
Short-Circuit Protection
Load-Dump Protection to 50 V
Efficiency
Four Channels at 4 Ω Each
Fortuitous Open-Ground and Open-Power
Tolerant
100
90
80
70
60
50
40
30
20
–
Patented Output DC Level Detection While
Music Playing
–
–
–
Overtemperature Protection
Overvoltage and Undervoltage Conditions
Clip Detection
•
64-Pin QFP (PHD) Power Package With Heat
Slug Up
•
•
•
•
Designed for Automotive EMC Requirements
Qualified According to AEC-Q100
TAS5404-Q1 only
10
System Efficiency
0
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
ISO9000:2002 TS16949-Certified
Power per Channel (W)
C001
–40°C to 105°C Ambient Temperature Range
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TAS5404-Q1
SLOS918A –AUGUST 2015–REVISED OCTOBER 2015
www.ti.com
Table of Contents
9.5 Programming........................................................... 24
9.6 Register Maps......................................................... 26
10 Application and Implementation........................ 31
10.1 Application Information.......................................... 31
10.2 Typical Application ................................................ 31
11 Power Supply Recommendations ..................... 34
12 Layout................................................................... 35
12.1 Layout Guidelines ................................................. 35
12.2 Layout Example .................................................... 35
12.3 Thermal Consideration.......................................... 38
1
2
3
4
5
6
7
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings ............................................................ 5
7.3 Recommended Operating Conditions ...................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 7
7.6 Timing Requirements for I2C Interface Signals....... 10
7.7 Typical Characteristics............................................ 11
Parameter Measurement Information ................ 12
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
9.2 Functional Block Diagram ....................................... 13
9.3 Feature Descption................................................... 14
9.4 Device Functional Modes........................................ 20
12.4 Electrical Connection of Heat Slug and Heat
Sink .......................................................................... 38
12.5 EMI Considerations............................................... 38
13 Device and Documentation Support ................. 40
13.1 Device Support...................................................... 40
13.2 Community Resources.......................................... 40
13.3 Trademarks........................................................... 40
13.4 Electrostatic Discharge Caution............................ 40
13.5 Glossary................................................................ 40
8
9
14 Mechanical, Packaging, and Orderable
Information ........................................................... 40
4 Revision History
Changes from Original (August 2015) to Revision A
Page
•
Changed the data sheet from Product Preview to Production Data....................................................................................... 1
2
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SLOS918A –AUGUST 2015–REVISED OCTOBER 2015
5 Device Comparison Table
PART NUMBER
TAS5404-Q1
MINIMUM POWER SUPPLY VOLTAGE
MAXIMUM POWER SUPPLY VOLTAGE
5.6 VDC
6 VDC
18 VDC
24 VDC
TAS5414C-Q1
6 Pin Configuration and Functions
Package
64-Pin QFP
(Top View)
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SLOS918A –AUGUST 2015–REVISED OCTOBER 2015
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Pin Functions
NAME
A_BYP
PIN
TYPE(1)
DESCRIPTION
11
PBY
Bypass pin for the AVDD analog regulator
Reports CLIP, OTW, or both. Also reports tweeter detection during tweeter
mode. Open-drain
CLIP_OTW
6
DO
CP
41
40
42
5
CP
CP
Top of main storage capacitor for charge pump (bottom goes to PVDD)
Bottom of flying capacitor for charge pump
CPC_BOT
CPC_TOP
D_BYP
FAULT
CP
Top of flying capacitor for charge pump
PBY
DO
Bypass pin for DVDD regulator output
1
Global fault output (open drain): UV, OV, OTSD, OCSD, DC
3, 7, 8, 9, 12, 14, 16, 17,
21, 22, 23, 24, 25, 26, 30,
31, 32, 35, 38, 39, 43, 46,
49, 50, 51, 55, 56, 57, 58,
59, 60
GND
GND
Ground
I2C_ADDR
IN1_P
62
AI
AI
I2C address bit
13
Non-inverting analog input for channel 1
Non-inverting analog input for channel 2
Non-inverting analog input for channel 3
Non-inverting analog input for channel 4
Signal return for the four analog channel inputs
Gain ramp control: mute (low), play (high)
Oscillator input from master or output to slave amplifiers
– polarity output for bridge 1
IN2_P
15
AI
IN3_P
19
AI
IN4_P
20
AI
IN_M
18
ARTN
AI
MUTE
2
OSC_SYNC
OUT1_M
OUT1_P
OUT2_M
OUT2_P
OUT3_M
OUT3_P
OUT4_M
OUT4_P
PVDD
61
DI/DO
PO
PO
PO
PO
PO
PO
PO
PO
PWR
AI
48
47
+ polarity output for bridge 1
45
– polarity output for bridge 2
44
+ polarity output for bridge 2
37
– polarity output for bridge 3
36
+ polarity output for bridge 3
34
– polarity output for bridge 4
33
+ polarity output for bridge 4
27, 28, 29, 52, 53, 54
PVDD supply
REXT
10
64
63
4
Precision resistor pin to set analog reference
I2C clock input from system I2C master
I2C data I/O for communication with system I2C master
Active-low STANDBY pin. Standby (low), power up (high)
SCL
DI
SDA
DI/DO
DI
STANDBY
(1) DI = digital input, DO = digital output, AI = analog input, ARTN = analog signal return, PWR = power supply, PBY = power bypass, PO =
power output, GND = ground, CP = charge pump.
4
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SLOS918A –AUGUST 2015–REVISED OCTOBER 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–1
MAX
18
UNIT
V
PVDD
DC supply voltage range
DC supply voltage range
Pulsed supply voltage range
Supply voltage ramp rate
Relative to GND
PVDDMAX
PVDDPULSED
PVDDRAMP
t ≤ 60 s exposure
t ≤ 100 ms exposure
30
V
50
V
15
V/ms
Externally imposed dc supply current per PVDD or GND
pin
IPVDD
±12
A
IPVDD_MAX
IO
Pulsed supply current per PVDD pin (one shot)
Maximum allowed DC current per output pin
Pulsed output current per output pin (single pulse)
Maximum current, all digital and analog input pins(3)
Maximum current on MUTE pin
t < 100 ms
17
±13.5
±17
±1
A
A
(2)
IO_MAX
t < 100 ms
A
IIN_MAX
DC or pulsed
DC or pulsed
mA
mA
mA
IMUTE_MAX
IIN_ODMAX
±20
7
Maximum sink current for open-drain pins
Input voltage range for pin relative to GND (SCL, SDA,
I2C_ADDR pins)
Supply voltage range:
6 V < PVDD < 18 V
VLOGIC
–0.3
–0.3
–0.3
–0.3
6
V
V
V
Supply voltage range:
6 V < PVDD < 18 V
VMUTE
Voltage range for MUTE pin relative to GND
Input voltage range for STANDBY pin
7.5
5.5
Supply voltage range:
6 V < PVDD < 18 V
VSTANDBY
Supply voltage range:
6 V < PVDD < 18 V
VOSC_SYNC
VGND
Input voltage range for OSC_SYNC pin relative to GND
Maximum voltage between GND pins
3.6
±0.3
1.9
V
V
Supply voltage range:
6 V < PVDD < 18 V
VAIN_AC_MAX
Maximum ac-coupled input voltage(3), analog input pins
Vrms
TJ
Maximum operating junction temperature range
Storage temperature
–55
–55
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum- rated conditions for extended periods may affect device reliability.
(2) Pulsed current ratings are maximum survivable currents externally applied to the TAS5404-Q1 device. The TAS5404-Q1 device can
encounter high currents during reverse-battery, fortuitous open-ground, and fortuitous open-supply fault conditions.
(3) See the Application Information section for information on analog input voltage and ac coupling.
7.2 ESD Ratings
VALUE
±2500
±750
UNIT
Human body model (HBM), per AEC Q100-002(1)
Corner pins excluding SCL
V
V(ESD)
Electrostatic discharge
Charged device model (CDM), per AEC
Q100-011 PHD Package
All pins (including SCL) except
CP and CP_Top
±600
±400
V
CP and CP_Top pins
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions(1)
MIN
6
NOM
MAX
UNIT
V
PVDDOP
DC supply voltage range relative to GND
Analog audio input signal level (TAS5414C-Q1)
Ambient temperature
14.4
18
0.25–1(3)
105
(2)
VAIN
AC-coupled input voltage
0
Vrms
°C
TA
–40
(1) The Recommended Operating Conditions table specifies only that the TAS5404-Q1 device is functional in the given range. See the
Electrical Characteristics table for specified performance limits.
(2) Signal input for full unclipped output with gains of 32 dB, 26 dB, 20 dB, and 12 dB
(3) Maximum recommended input voltage is determined by the gain setting.
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Recommended Operating Conditions(1) (continued)
MIN
NOM
MAX
UNIT
An adequate heat sink is required
to keep TJ within specified range.
TJ
Junction temperature
–40
115
°C
RL
Nominal speaker load impedance
2
3
4
Ω
VPU
Pullup voltage supply (for open-drain logic outputs)
3.3 or 5
5.5
50
10
V
Resistor connected between open-
drain logic output and VPU supply
RPU_EXT
RPU_I2C
RI2C_ADD
RREXT
External pullup resistor on open-drain logic outputs
I2C pullup resistance on SDA and SCL pins
10
1
kΩ
kΩ
4.7
20
Total resistance of voltage divider for I2C address
slave 1 or slave 2, connected between D_BYP and
GND pins
10
50
kΩ
External resistance on REXT pin
1% tolerance required
19.8
10
20.2
120
kΩ
CD_BYP
CA_BYP
,
External capacitance on D_BYP and A_BYP pins
nF
COUT
CIN
External capacitance to GND on OUT_X pins
150
680
nF
External capacitance to analog input pin in series
with input signal
0.47
μF
CFLY
CP
Flying capacitor on charge pump
Charge pump capacitor
0.47
0.47
100
1
1
1.5
1.5
μF
μF
nF
pF
50 V required for load dump
CMUTE
MUTE pin capacitor
220
75
1000
COSCSYNC_MAX
Allowed loading capacitance on OSC_SYNC pin
7.4 Thermal Information
THERMAL METRIC(1)
TAS5404-Q1
UNIT
Junction-to-case (heat slug) thermal
resistance
RθJC
1.2
°C/W
This TAS5404-Q1 device is not intended to be used without a heatsink.
Therefore, RθJA is not specified. Refer to the Thermal Consideration
section.
RθJA
Junction-to-ambient thermal resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6
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SLOS918A –AUGUST 2015–REVISED OCTOBER 2015
7.5 Electrical Characteristics
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ,
AES17 filter, default I2C settings, master-mode operation (see Figure 20)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OPERATING CURRENT
IPVDD_IDLE
All four channels in MUTE mode
170
93
2
220
mA
PVDD idle current
IPVDD_Hi-Z
All four channels in Hi-Z mode
IPVDD_STBY
PVDD standby current
STANDBY mode, TJ ≤ 85°C
10
μA
OUTPUT POWER
4 Ω, THD+N ≤ 1%, 1 kHz, Tc = 75°C
4 Ω, THD+N = 10%, 1 kHz, Tc = 75°C
4 Ω, square wave, 1 kHz, Tc = 75°C
2 Ω, THD+N = 1%, 1 kHz, Tc = 75°C
2 Ω, THD+N = 10%, 1 kHz, Tc = 75°C
2 Ω, square wave, 1 kHz, Tc = 75°C
20
26
43
38
45
70
25
40
POUT
Output power per channel
Power efficiency
W
4 channels operating, 20-W output power/ch, L = 10 μH,
TJ ≤ 85°C
EFFP
AUDIO PERFORMANCE
90%
VNOISE
Noise voltage at output
Zero input, and A-weighting
60
85
100
μV
P = 1 W, f = 1 kHz, enhanced crosstalk enabled through
I2C (reg. 0x10)
Channel crosstalk
70
dB
Common-mode rejection ratio (TAS5424C-
Q1)
CMRR5424
f = 1 kHz, 1 Vrms referenced to GND, G = 26 dB
60
60
75
dB
dB
PSRR
Power-supply rejection ratio
PVDD = 14.4 Vdc + 1 Vrms, f = 1 kHz
P = 1 W, f = 1 kHz
75
0.02%
357
THD+N
Total harmonic distortion + noise
0.1%
378
442
530
106
336
392
470
63
Switching frequency selectable for AM interference
avoidance
fS
Switching frequency
417
kHz
500
RAIN
Analog input resistance
Internal shunt resistance on each input pin
85
kΩ
Vrms
V
AC-coupled common-mode input voltage (zero
differential input)
VIN_CM
VCM_INT
Common-mode input voltage
Internal common-mode input bias voltage
1.3
Internal bias applied to IN_M pin
3.3
12
20
26
32
0
11
19
25
31
–1
13
21
27
33
1
Source impedance = 0 Ω, gain measurement taken at 1
W of power per channel
G
Voltage gain (VO/VIN
)
dB
dB
GCH
Channel-to-channel variation
Any gain commanded
PWM OUTPUT STAGE
RDS(on)
FET drain-to-source resistance
Output offset voltage
Not including bond wire resistance, TJ = 25°C
Zero input signal, G = 26 dB
65
90
mΩ
VO_OFFSET
±10
±50
mV
PVDD OVERVOLTAGE (OV) PROTECTION
VOV_SET
PVDD overvoltage shutdown set
PVDD overvoltage shutdown clear
24.6
24.4
26.4
25.9
28.2
27.4
V
V
VOV_CLEAR
PVDD UNDERVOLTAGE (UV) PROTECTION
VUV_SET
PVDD undervoltage shutdown set
PVDD undervoltage shutdown clear
4.9
6.2
5.3
6.6
5.5
6.9
V
V
VUV_CLEAR
AVDD
VA_BYP
A_BYP pin voltage
A_BYP UV voltage
6.5
4.8
5.3
V
V
V
VA_BYP_UV_SET
VA_BYP_UV_CLEAR Recovery voltage A_BYP UV
DVDD
VD_BYP
D_BYP pin voltage
3.3
V
POWER-ON RESET (POR)
I2C active above this voltage
VPOR
PVDD voltage for POR
PVDD recovery hysteresis voltage for POR
4
V
V
VPOR_HY
0.1
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Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ,
AES17 filter, default I2C settings, master-mode operation (see Figure 20)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
REXT
VREXT
Rext pin voltage
1.27
V
CHARGE PUMP (CP)
VCPUV_SET
CP undervoltage
4.8
4.9
V
V
VCPUV_CLEAR
Recovery voltage for CP UV
OVERTEMPERATURE (OT) PROTECTION
TOTW1_CLEAR
96
112
122
128
138
°C
°C
TOTW1_SET
/
106
TOTW2_CLEAR
Junction temperature for overtemperature
warning
TOTW2_SET
/
116
126
136
130
132
142
152
150
148
158
168
170
°C
°C
°C
°C
TOTW3_CLEAR
TOTW3_SET
/
TOTSD_CLEAR
Junction temperature for overtemperature
shutdown
TOTSD
Junction temperature for overtemperature
foldback
TFB
Per channel
CURRENT LIMITING PROTECTION
ILIM
Current limit (load current)
8.5
9.8
A
A
OVERCURRENT (OC) SHUTDOWN PROTECTION
IMAX
Maximum current (peak output current)
Any short to supply, ground, or other channels
TWEETER DETECT
ITH_TW
Load-current threshold for tweeter detect
330
445
2.1
560
mA
A
ILIM_TW
Load-current limit for tweeter detect
STANDBY MODE
VIH
STANDBY input voltage for logic-level high
STANDBY input voltage for logic-level low
STANDBY pin current
2
V
V
VIL
0.7
0.2
ISTBY
0.1
100
μA
MUTE MODE
GMUTE
MUTE pin ≤ 0.5 V for 200 ms or I2C Mute Enabled
Output attenuation
dB
s
DC OFFSET DETECT
VTH_DC_TOL DC offset detect threshold tolerance
25%
DC offset detect step-response time for four
channels
tDCD
5.3
CLIP_OTW REPORT
CLIP_OTW pin output voltage for logic level
VOH_CLIPOTW
2.4
V
V
high (open-drain logic output)
External 47-kΩ pullup resistor to 3 V to 5.5 V
CLIP_OTW pin output voltage for logic level
low (open-drain logic output)
VOL_CLIPOTW
0.5
20
CLIP_OTW signal delay when output
clipping detected
tDELAY_CLIPDET
FAULT REPORT
VOH_FAULT
μs
FAULT pin output voltage for logic-level high
(open-drain logic output)
2.4
External 47-kΩ pullup resistor to 3 V to 5.5 V
V
FAULT pin output voltage for logic-level low
(open-drain logic output)
VOL_FAULT
0.5
8
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Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TCase = 25°C, PVDD = 14.4 V, RL = 4 Ω, fS = 417 kHz, Pout = 1 W/ch, Rext = 20 kΩ,
AES17 filter, default I2C settings, master-mode operation (see Figure 20)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OPEN, SHORT DIAGNOSTICS
Maximum resistance to detect a short from
OUT pin(s) to PVDD or ground
RS2P, RS2G
200
1300
1.5
Ω
Ω
Ω
Minimum load resistance to detect open
circuit
ROPEN_LOAD
RSHORTED_LOAD
Including speaker wires
300
0.5
740
1
Maximum load resistance to detect short
circuit
Including speaker wires
I2C ADDRESS DECODER
Time delay to latch I2C address after POR
tLATCH_I2CADDR
300
0%
μs
Voltage on I2C_ADDR pin for address 0
Voltage on I2C_ADDR pin for address 1
Voltage on I2C_ADDR pin for address 2
Voltage on I2C_ADDR pin for address 3
Connect to GND
0%
25%
55%
85%
15%
45%
35%
65%
100%
External resistors in series between D_BYP and GND as
a voltage divider
VI2C_ADDR
VD_BYP
75%
Connect to D_BYP
100%
I2C
Power-on hold time before I2C
communication
tHOLD_I2C
STANDBY high
1
ms
fSCL
VIH
VIL
SCL clock frequency
400
5.5
1.1
kHz
V
SCL pin input voltage for logic-level high
SCL pin input voltage for logic-level low
2.1
RPU_I2C = 5-kΩ pullup, supply voltage = 3.3 V or 5 V
–0.5
V
I2C read, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VOH
VO
SDA pin output voltage for logic-level high
SDA pin output voltage for logic-level low
SDA pin input voltage for logic-level high
2.4
V
V
V
I2C read, 3-mA sink current
0.4
5.5
I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VIH
2.1
I2C write, RI2C = 5-kΩ pullup,
supply voltage = 3.3 V or 5 V
VIL
SDA pin input voltage for logic-level low
Capacitance for SCL and SDA pins
–0.5
1.1
10
V
C I
pF
OSCILLATOR
OSC_SYNC pin output voltage for logic-
level high
VOH
VOL
VIH
VIL
2.4
2
V
V
V
V
I2C_ADDR pin set to MASTER mode
I2C_ADDR pin set to SLAVE mode
OSC_SYNC pin output voltage for logic-
level low
0.5
0.8
OSC_SYNC pin input voltage for logic-level
high
OSC_SYNC pin input voltage for logic-level
low
I2C_ADDR pin set to MASTER mode, fS = 500 kHz
I2C_ADDR pin set to MASTER mode, fS = 417 kHz
I2C_ADDR pin set to MASTER mode, fS = 357 kHz
3.76
3.13
2.68
4
3.33
2.85
4.24
3.63
3
fOSC_SYNC
OSC_SYNC pin clock frequency
MHz
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7.6 Timing Requirements for I2C Interface Signals
over recommended operating conditions (unless otherwise noted)
MIN NOM
MAX
300
UNIT
ns
tr
Rise time for both SDA and SCL signals
Fall time for both SDA and SCL signals
SCL pulse duration, high
tf
300
ns
tw(H)
tw(L)
tsu(2)
th(2)
tsu(1)
th(1)
tsu(3)
CB
0.6
1.3
0.6
0.6
100
0(1)
0.6
μs
SCL pulse duration, low
μs.
μs
Setup time for START condition
START condition hold time until generation of first clock pulse
Data setup time
μs
ns
Data hold time
ns
Setup time for STOP condition
Load capacitance for each bus line
μs
400
pF
(1) The TAS5404-Q1 device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the
falling edge of SCL.
tw(H)
tw(L)
tr
tf
SCL
tsu1
th1
SDA
T0027-01
Figure 1. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 2. Timing for Start and Stop Conditions
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7.7 Typical Characteristics
10
1
10
1
0.1
0.01
0.1
0.01
0.1
1
10
100
0.1
1
10
100
Power (W)
Power (W)
C004
C005
Figure 3. THD+N vs BTL Output Power at 1 kHz into 4 Ω
Figure 4. THD+N vs PBTL Output Power at 1 kHz into 2 Ω
10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1
0.1
0.01
20
200
2k
Frequency (Hz)
20k
20
200
2k
20k
Frequency (Hz)
C003
C006
Figure 5. THD+N vs Frequency at 1 W into 4 Ω
Figure 6. Crosstalk vs Frequency
100
90
80
70
60
50
40
30
20
10
0
TAS5404-Q1 only
System Efficiency
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Power per Channel (W)
C001
Figure 7. Noise FFT
Figure 8. Efficiency
Four Channels at 4 Ω Each
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Typical Characteristics (continued)
14
12
10
8
6
4
2
0
0
10
20
30
Output Power per Channel
C002
Figure 9. Device Power Dissipation
Four Channels at 4 Ω Each
8 Parameter Measurement Information
The parameters for the TAS5404-Q1 device were measured using the circuit in Figure 20.
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9 Detailed Description
9.1 Overview
The TAS5404-Q1 device is a monolithic, four channel, audio amplifier with special features that are necessary for
OEM automotive audio systems. The design of the TAS5404-Q1 device utilizes efficient, proprietary class-D
technology developed by Texas Instruments. The technology of the TAS5404-Q1 device allows for reduced
power consumption, reduced heat, and reduced peak currents in the electrical system. The TAS5404-Q1 device
realizes an audio sound system design with smaller size and lower weight than class-AB solutions.
The TAS5404-Q1 device has eight core design blocks:
•
•
•
•
•
•
•
•
Preamplifier
PWM
Gate drive
Power FETs
Diagnostics
Protection
Power supply
I2C serial communication bus
9.2 Functional Block Diagram
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9.3 Feature Descption
9.3.1 Preamplifier
The preamplifier is a high-input-impedance, low-noise, low-offset-voltage input stage with adjustable gain. The
high input impedance allows the use of low-cost input capacitors while still achieving extended low-frequency
response. A dedicated, internally regulated supply powers the preamplifier, giving it excellent noise immunity and
channel separation. The preamplifier in the TAS5404-Q1 device also includes:
1. Fast Start Up — The preamplifier will fast charge the input coupling capacitors at start up, which will allow
for a fast turn-on without any pop or click.
2. Mute Pop-and-Click Control — The TAS5404-Q1 device ramps the gain gradually when receiving a mute
or play command. The starting or stopping of switching in a class-D amplifier can cause another form of click
and pop. The TAS5404-Q1 device incorporates a patented method to reduce the pop energy during the
switching startup and shutdown sequence. Fault conditions require a rapid protection response, which do not
have time to ramp the gain down in a pop-free manner. The TAS5404-Q1 device transitions into Hi-Z mode
when encountering an OV, UV, OC, OT, or DC Offset fault. Advanced circuitry will allow for a fast, pop-free
shutdown when the /STANBY pin is pulled low.
3. Gain Control — The gain is set for the four channels in the preamplifier through I2C control registers. The
gain control is outside of the global feedback network of the TAS5404-Q1 device, thus allowing for stability of
the system at all gain settings with properly loaded conditions. A line output gain of 12 dB is provided for
driving external amplifiers.
9.3.2 Pulse-Width Modulator (PWM)
The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. The PWM
is the critical stage that defines the class-D architecture. The modulator is an advanced design with high
bandwidth, low noise, low distortion, excellent stability, and full 0 to 100% modulation capability. The patented
PWM uses soft clipping to for improved audio performance at clipping.
9.3.3 Gate Drive
The gate driver accepts the low-voltage PWM signal and level-shifts it to drive a high-current, full-bridge, power
FET stage. The TAS5404-Q1 device uses proprietary techniques to optimize EMI and audio performance. The
high-side FET power supply is generated by the charge pump circuitry.
9.3.4 Power FETs
The BTL output for each channel comprises four rugged N-channel 30-V 65-mΩ FETs for high efficiency and
maximum power transfer to the load. These FETs are designed to withstand large voltage transients during load
dump.
9.3.5 Load Diagnostics
The TAS5404-Q1 device incorporates load diagnostic circuitry designed to help pinpoint the nature of output
misconnections during installation. These are functions for detecting and determining the status of output
connections. The following diagnostics are supported:
•
•
•
•
•
Short to GND (S2G)
Short to PVDD (S2P)
Short across load (SL)
Open load (OL)
Tweeter detection
Reporting to the system of the presence of any of the short or open conditions occurs through I2C register read.
Determine the tweeter-detect status from the CLIP_OTW pin when properly configured.
1. Output Short and Open Diagnostics — The TAS5404-Q1 device contains circuitry designed to detect
shorts and open conditions on the outputs. Invocation of the load diagnostic function will automatically place
the channel into Hi-Z mode. All pop-free transitions will occur before the load diagostics will start. The test
has four phases and two levels of test during load diagnostics. In the full level, all channels must be in the Hi-
Z state. Testing covers all four phases on each channel on all four channels at the same time. When fewer
than four channels are in Hi-Z, the reduced level of test is the only available option. In the reduced level, the
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Feature Descption (continued)
only tests available are short to PVDD and short to GND. Load diagnostics can occur at anytime during
operation of the TAS5404-Q1 device, by setting the proper bits in the control registers. Performance of the
diagnostics is as shown in Figure 10. Figure 11 shows the impedance ranges for the open-load and shorted-
load diagnostics. The results of the diagnostics are from the diagnostic register through I2C for each channel.
With the default settings and MUTE capacitor, the S2G and S2P phases take approximately 20 ms each, the
OL phase takes approximately 100 ms, and the SL takes approximately 230 ms. In I2C register 0x10, bit D4
can extend the test time for S2P and S2G to 80 ms each. To prevent false S2G and S2P faults, the time
extension is necessary if the output pins have a capacitance higher than 680 nF to ground.
Figure 10. Load Diagnostics Sequence of Events
Figure 11. Open- and Shorted-Load Detection
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Feature Descption (continued)
2. Tweeter Detection — Tweeter detection is an operating mode used to determine the proper connection of a
frequency-dependent load (such as a speaker with a crossover). Tweeter detection is started through I2C,
and individual testing of all four channels is recommended. Tweeter detection uses the average cycle-by-
cycle current limit circuit (see CBC section) to measure the current delivered to the load. The proper
implementation of the diagnostic function depends on the amplitude of a user-supplied test signal and on the
impedance-versus-frequency curve of the acoustic load. The external system must generate a signal to
which the load responds. The frequency and amplitude of the signal must be calibrated by the user to result
in a current draw that is greater than the tweeter detection threshold when the load under test is present, and
less than the detection threshold if the load is unconnected. The current level for the tweeter detection
threshold, as well as the maximum current that can safely be delivered to a load when in tweeter-detection
mode, is in the Electrical Characteristics section of the data sheet. Reporting of the tweeter-detection results
is on the CLIP_OTW pin during the application of the test signal. With tweeter detection activated (indicating
that the tested load is present), pulses on the CLIP_OTW pin begin to toggle. The pulses on the CLIP_OTW
pins report low whenever the current exceeds the detection threshold, and the pin remains low until the
current no longer exceeds the threshold. The minimum low-pulse period is equal to one period of the
switching frequency. Having an input signal that increases the duration of detector activation (for example,
increasing the amplitude of the input signal) increases the amount of time for which the pin reports low.
NOTE
Because tweeter detection is an alternate operating mode, place the channels to be tested
in Play mode (through register 0x0C) after tweeter detection has been activated to
commence the detection process. Additionally, set up the CLIP_OTW pin through register
0x0A to report the results of tweeter detection.
9.3.6 Protection and Monitoring
1. Cycle-By-Cycle Current Limit (CBC) — The CBC current-limiting circuit terminates each PWM pulse to limit
the output current flow to the average current limit (ILIM) threshold. The overall effect on the audio in the case
of a current overload is quite similar to a voltage-clipping event, temporarily limiting power at the peaks of the
musical signal and normal operation continues without disruption on removal of the overload. Premature
shutdown does not occur in this condition. All four channels continue in play mode and pass signal.
2. Overcurrent Shutdown (OCSD) — Under severe short-circuit events, such as a short to PVDD or ground,
the TAS5404-Q1 device uses a peak-current detector, and the affected channel shuts down in 200 μs to 390
μs if the conditions are severe enough. The shutdown speed depends on a number of factors, such as the
impedance of the short circuit, supply voltage, and switching frequency. Only the shorted channels shut
down in such a scenario. The user can restart the affected channel through I2C. An OCSD event activates
the fault pin, and the I2C fault register saves a record of the affected channels. If the supply or ground short
is strong enough to exceed the peak current threshold but not severe enough to trigger the OCSD, the peak
current limiter prevents excess current from damaging the output FETs, and operation returns to normal after
the short is removed.
3. DC Offset Detect—the circuit detects a dc offset at the output of the amplifier continuously during normal
operation. If the DC offset reaches the level defined in the I2C registers for the specified time period, the
circuit triggers. By default, a DC offset detection event places the output in Hi-Z mode. Disabling and
enabling the shutdown function is through I2C. If enabled, the triggered channel shuts down, but the others
remain playing, but with the FAULT pin asserted. The DC offset level is defined in the I2C registers.
4. Clip Detect—The clip detect circuit indicates the presence of a 100% duty-cycle PWM due to a clipped
waveform. When this occurs, a signal passed to the CLIP_OTW pin asserts it until the 100% duty-cycle
PWM signal is no longer present. All four channels connect to the same CLIP_OTW pin. Through I2C,
change the CLIP_OTW signal clip-only, OTW-only, or both. A fourth mode, used only during diagnostics, is
the option to report tweeter detection events on the CLIP_OTW pin (see the Tweeter Detection section). The
microcontroller in the system can monitor the signal at the CLIP_OTW pin, and can have a configuration that
reduces the volume to all four channels in an active clipping-prevention circuit.
5. Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD) and Thermal Foldback — By
default, the CLIP_OTW pin setting indicates an OTW. The user can make changes through I2C commands. If
selected to indicate a temperature warning, CLIP_OTW pin assertion occurs when the die temperature
reaches warning level 1 as shown in the electrical specifications. The OTW has three temperature thresholds
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Feature Descption (continued)
with a 10°C hysteresis. I2C register 0x04 indicates each threshold in bits 5, 6, and 7. The TAS5404-Q1
device still functions until the temperature reaches the OTSD threshold, at which time the outputs go into Hi-
Z mode and the TAS5404-Q1 device asserts the FAULT pin. I2C is still active in the event of an OTSD, and
the user can read the registers for faults, but all audio ceases abruptly. After the OTSD resets, turn the
TAS5404-Q1 device back on through I2C. The OTW indication remains until the temperature drops below
warning level 1. The thermal foldback decreases the channel gain.
6. Undervoltage (UV) and Power-on-Reset (POR) — The undervoltage (UV) protection detects low voltages
on PVDD, AVDD, and CP. In the event of an undervoltage, the TAS5404-Q1 device asserts the FAULT pin
and updates the I2C registerd, depending on which voltage caused the event. Power-on reset (POR) occurs
when PVDD drops low enough. A POR event causes the I2C to go into a high-impedance state. After the
TAS5404-Q1 device recovers from the POR event, the device re-initialization occurs through I2C.
7. Overvoltage (OV) and Load Dump — The OV protection detects high voltages on PVDD. If PVDD reaches
the overvoltage threshold, the TAS5404-Q1 device asserts the FAULT pin iand updates the I2C register. The
TAS5404-Q1 device can withstand 50-V load-dump voltage spikes.
9.3.7 I2C Serial Communication Bus
The TAS5404-Q1 device communicates with the system processor through the I2C serial communication bus as
an I2C slave-only device. The processor can poll the device through I2C to determine the operating status. All
reports of fault conditions and detections are through I2C. The TAS5404-Q1 device also has numerous features
and operating conditions that can be set through I2C.
The I2C bus allows control of the following configurations:
•
•
•
•
•
•
•
•
Independent gain control of each channel. The gain can be set to 12 dB, 20 dB, 26 dB, and 32 dB.
Select the AM non-interference switching frequency
Select the functionality of the OTW_CLIP pin
Enable or disable the dc-detect function with selectable threshold
Place a channel in Hi-Z (switching stopped) mode (mute)
Select tweeter detect, set the detection threshold, and initiate the function
Initiate the open-load and shorted-load diagnostic
Reset faults and return to normal switching operation from Hi-Z mode (unmute)
In addition to the standard SDA and SCL pins for the I2C bus, the TAS5404-Q1 device includes a single pin that
allows up to four devices to work together in a system with no additional hardware required for communication or
synchronization. The I2C_ADDR pin sets the device in master or slave mode and selects the I2C address for that
device. Tie the I2C_ADDR pin to DGND for master, to 1.2 Vdc for slave 1, to 2.4 Vdc for slave 2, and to D_BYP
for slave 3. The OSC_SYNC pin is for synchronizing the internal clock oscillators to avoid beat frequencies. An
external oscillator can be applied to the OSC_SYNC pin for external control of the switching frequency.
Table 1. Table 7. I2C_ADDR Pin Connection
I2C_ADDR VALUE
0 (OSC MASTER)
I2C_ADDR PIN CONNECTION
I2C ADDRESSES
0xD8/D9
To SGND pin
1 (OSC SLAVE1)
2 (OSC SLAVE2)
3 (OSC SLAVE3)
35% DVDD (resistive voltage divider between D_BYP pin and SGND pin)(1)
65% DVDD (resistive voltage divider between D_BYP pin and SGND pin)(1)
To D_BYP pin
0xDA/DB
0xDC/DD
0xDE/DF
(1) TI recommends RI2C_ADDR resistors with 5% or better tolerance.
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9.3.8 I2C Bus Protocol
The TAS5404-Q1 device has a bidirectional serial control interface that is compatible with the Inter IC (I2C) bus
protocol and supports 400-kbps data transfer rates for random and sequential write and read operations. The
TAS5404-Q1 device is a slave-only device that does not support a multimaster bus environment or wait-state
insertion. The control interface programs the registers of the device and reads device status.
The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data transfer on the bus is serial, one bit at a time. The transfer of address and data is in byte (8-bit)
format with the most-significant bit (MSB) transferred first. In addition, the receiving device acknowledges each
byte transferred on the bus with an acknowledge bit. Each transfer operation begins with the master device
driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus
uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop conditions. A
HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data-
bit transitions must occur within the low time of the clock period. Figure 12 shows these conditions. The master
generates the 7-bit slave address and the read/write bit to open communication with another device and then
wait for an acknowledge condition. The TAS5404-Q1 holds SDA LOW during the acknowledge-clock period to
indicate an acknowledgment. When the acknowledgment occurs, the master device transmits the next byte of the
sequence. Each slave device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible
devices share the same signals through a bidirectional bus using a wired-AND connection. The SDA and SCL
signals must have an external pullup resistor to set the HIGH level for the bus. Any number of bytes can be
transmitted between start and stop conditions. When the last word transfers, the master device generates a stop
condition to release the bus.
8-Bit Register Data For
Address (N)
8-Bit Register Data For
Address (N)
R/
W
8-Bit Register Address (N)
7-Bit Slave Address
A
A
A
A
SDA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
Start
Stop
T0035-01
Figure 12. Typical I2C Sequence
Use the I2C_ADDR pin (pin 2) to program the TAS5404-Q1 device for one of four addresses. These four
addresses are licensed I2C addresses and do not conflict with other licensed I2C audio devices. The I2C master
device uses addresses shown in Figure 12 to communicate. Transmission of read and write data can be through
single-byte or multiple-byte data transfers.
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9.3.9 Hardware Control Pins
The TAS5404-Q1 device has four discrete hardware pins for real-time control and indication of device status:
1. FAULT pin: This active-low open-drain output pin indicates the presence of a fault condition that requires the
TAS5404-Q1 device to go into the Hi-Z mode. On assertion of the FAULT pin, the TAS5404-Q1 device has
protected itself and the system from potential damage. Read the details of the fault through I2C with the
exception of PVDD undervoltage faults below POR, in which case the I2C bus is no longer operational.
However, the fault is still indicated due to FAULT pin assertion.
2. CLIP_OTW pin: Configured through I2C, this active-low open-drain pin indicates one of the following
conditions: overtemperature warning, the detection of clipping, or the logical OR of both of these conditions.
During tweeter detect diagnostics, assertion of the CLIP_OTW pin also occurs when a tweeter is present.
The CLIP_OTW pin can also indicate thermal foldback is active.
3. MUTE pin: This active-low pin is used for hardware control of the mute-unmute function for all four channels.
Capacitor CMUTE controls the time constant for the gain ramp required to produce a pop-and-click-free mute
function. For pop-and-click-free operation, implementation of the mute function should be through I2C
commands. The use of a hard mute with an external transistor does not ensure pop-and-click-free operation,
and TI does not recommend it except as an emergency hard mute function in case of a loss of I2C control.
The CMUTE capacitor cannot be shared between multiple devices.
4. STANDBY pin: On assertion of this active-low pin, the TAS5404-Q1 device goes into a complete shutdown,
and the typical current-draw limit is 2 μA, typical. STANDBY can be used to shut down the device rapidly. If
all channels are in Hi-Z, the device enters standby in approximately 1 ms. If the channels are in play mode,
the device enters standby in approximately 4.5 ms with a pop-and-click-free operation. All I2C register
content is lost and the I2C bus goes into the high-impedance state on assertion of the STANDBY pin.
9.3.10 AM Radio Avoidance
To reduce interference in the AM radio band, the TAS5404-Q1 device has the ability to change the switching
frequency through I2C commands. Table 2 lists the recommended frequencies. The fundamental frequency and
the second harmonic straddle the AM radio band listed, which eliminates the tones that can be present due to
demodulation of the switching frequency by the AM radio.
Table 2. Recommended Switching Frequencies for AM Mode Operation
US
EUROPEAN
SWITCHING
FREQUENCY
(kHz)
SWITCHING
FREQUENCY
(kHz)
AM FREQUENCY
(kHz)
AM FREQUENCY
(kHz)
540–670
680–980
417
500
417
500
417
500
522–675
676–945
417
500
417
500
417
500
990–1180
1190–1420
1430–1580
1590–1700
946–1188
1189–1422
1423–1584
1585–1701
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9.4 Device Functional Modes
Table 3 and Table 5 depict the operating modes and faults.
Table 3. Operating Modes
STATE NAME
STANDBY
Hi-Z
OUTPUT FETS
Hi-Z, floating
CHARGE PUMP
Stopped
OSCILLATOR
Stopped
I2C
AVDD and DVDD
Stopped
Active
Active
Active
OFF
ON
ON
ON
Hi-Z, weak pulldown
Switching at 50%
Switching with audio
Active
Active
Active
Active
Active
Active
Mute
Normal operation
Table 4. Global Faults and Actions
FAULT OR
EVENT
CATEGORY
LATCHED OR
SELF-
CLEARING
FAULT OR
EVENT
MONITORING
REPORTING
METHOD
ACTION
TYPE
ACTION
RESULT
MODES
POR
UV
Voltage fault
All
FAULT pin
I2C + FAULT pin
Hard mute (no ramp)
Standby
Hi-Z
Self-clearing
Latched
Hi-Z, mute, normal
CP UV
OV
Load dump
All
FAULT pin
Standby
None
Self-clearing
Self-clearing
Latched
OTW
Thermal warning
Thermal fault
Hi-Z, mute, normal
Hi-Z, mute, normal
I2C + CLIP_OTW pin
I2C + FAULT pin
None
OTSD
Hard mute (no ramp)
Standby
Table 5. Channel Faults and Actions
LATCHED OR
SELF-
CLEARING
FAULT/
EVENT
FAULT OR EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
TYPE
ACTION
RESULT
Open-short
diagnostic
Diagnostic
Hi-Z (I2C activated)
I2C
None
None
Latched
Clipping
Warning
Mute / Play
CLIP_OTW pin
None
None
Self-clearing
Self-clearing
CBC load current
limit
Online protection
Current Limit
Start OC
timer
OC fault
Output channel fault
Warning
I2C + FAULT pin
Hard mute
Hard mute
Hi-Z
Hi-Z
Latched
Latched
DC offset detect
OT Foldback
I2C + CLIP_OTW
pin
Reduce Gain
None
Self-clearing
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9.4.1 Audio Shutdown and Restart Sequence
The gain ramp of the filtered output signal and the updating of the I2C registers correspond to the MUTE pin
voltage during the ramping process. The value of the external capacitor on the MUTE pin dictates the length of
time that the MUTE pin takes to complete the ramp. With the default 220-nF capacitor, the turn on common-
mode ramp takes approximately 26 ms and the gain ramp takes approximately 76 ms.
tCM
tCM
tGAIN
tGAIN
HIZ_Report_x
(All Channels)
LOW_LOW_Report_x
(All Channels)
MUTE_Report_x
(All Channels)
PLAY_Report_x
MUTE Pin
OUTx_P (Filtered)
(All Channels)
OUTx_M (Filtered)
(All Channels)
T0192-02
Figure 13. Timing Diagram for Click- and Pop-Free Shutdown and Restart Sequence
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9.4.2 Latched-Fault Shutdown and Restart Sequence Control
tI2C_CL
tDEGLITCH
tCM
tDEGLITCH
tGAIN
PVDD Normal Operating Region
UV
Detect
UV
Reset
PVDD
VUV + VUV_HY
VUV
PVDD UV Hysteresis Region
VPOR
HIZ_x
Internal I2C Write
MUTE_Report
UV_DET
Cleared by
External I2C Read
External I2C Read
to Fault Register 1
UV_LATCH
FAULT Pin
MUTE Pin
Pop
OUTx_P (Filtered)
T0194-02
Figure 14. Timing Diagram for Latched-Global-Fault Shutdown and Restart
(UV Shutdown and Recovery)
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tI2C_CL
tDEGLITCH
tCM
tDEGLITCH
tGAIN
PVDD Normal Operating Region
PVDD UV Hysteresis Region
UV
Detect
UV
Reset
PVDD
VUV + VUV_HY
VUV
VPOR
Internal I2C Write
HIZ_Report_1
HIZ_Report_2,3,4
MUTE_Report
UV_DET
Cleared by
External I2C Read
External I2C Read
to Fault Register 1
UV_LATCH
FAULT Pin
MUTE Pin
Pop
Pop
Pop
OUT1_P (Filtered)
OUT2,3,4_P (Filtered)
T0195-02
Figure 15. Timing Diagram for Latched-Global-Fault Shutdown and Individual-Channel Restart
(UV Shutdown and Recovery)
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9.5 Programming
9.5.1 Random Write
As shown in Figure 16, a random write or single-byte write transfer begins with the master device transmitting a
start condition followed by the I2C device address and the read/write bit. The read/write bit determines the
direction of the data transfer. For a single-byte write data transfer, the read/write bit is a 0. After receiving the
correct I2C device address and the read/write bit, the slave device responds with an acknowledge bit. Next, the
master device transmits the address byte or bytes corresponding to the internal memory address being
accessed. After receiving the address byte, the slave device again responds with an acknowledge bit. Next, the
master device transmits the data byte to be written to the memory address being accessed. After receiving the
data byte, the TAS5404Q1 device again responds with an acknowledge bit. Finally, the master device transmits
a stop condition to complete the single-byte write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
R/W
A6 A5 A4 A3 A2 A1 A0
ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
Data Byte
Stop
Condition
T0036-01
Figure 16. Random-Write Transfer
9.5.2 Sequential Write
A sequential write transfer is identical to a single-byte data-write transfer except for the transmisson of multiple
data bytes by the master device as shown in Figure 17. After receiving each data byte, the slave device
responds with an acknowledge bit and automatically increments the I2C subaddress by one.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK D7
Acknowledge
D0 ACK
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4 A3
A1 A0 ACK D7
I2C Device Address and
Read/Write Bit
Subaddress
First Data Byte
Last Data Byte
Stop
Condition
Other Data Bytes
T0036-02
Figure 17. Sequential Write Transfer
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Programming (continued)
9.5.3 Random Read
As shown in Figure 18, a random read or single-byte read transfer begins with the master device transmitting a
start condition followed by the I2C device address and the read/write bit. For the single-byte read transfer, the
master device transmits both a write followed by a read. Initially, a write transfers the address byte or bytes of
the internal memory address to be read. Therefore, the read/write bit is a 0. After receiving the address and the
read/write bit, the slave device responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the device address and
the read/write bit again. At that point the read/write bit is a 1, indicating a read transfer. After receiving the
address and the read/write bit, the slave device again responds with an acknowledge bit. Next, the TAS5404-Q1
device transmits the data byte from the memory address being read. After receiving the data byte, the master
device transmits a not-acknowledge followed by a stop condition to complete the single-byte read transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
A0 ACK
Acknowledge
A6 A5
A1 A0 R/W ACK A7 A6 A5 A4
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and
Read/Write Bit
Data Byte
Stop
Condition
T0036-03
Figure 18. Random Read Transfer
9.5.4 Sequential Read
A sequential read transfer is identical to a single-byte read transfer except for the transmission of multiple data
bytes by the TAS5404-Q1 device to the master device as shown in Figure 19. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte and automatically increments the
I2C subaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge
followed by a stop condition to complete the transfer.
Repeat Start
Condition
Not
Acknowledge
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
D0 ACK D7
A6
A0 R/W ACK A7 A6 A5
A0 ACK
A6
A0 R/W ACK D7
D0 ACK D7
D0 ACK
I2C Device Address and
Read/Write Bit
Subaddress
I2C Device Address and First Data Byte
Read/Write Bit
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 19. Sequential Read Transfer
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9.6 Register Maps
Table 6. TAS5404-Q1 I2C Addresses
SELECTABLE WITH
FIXED ADDRESS
READ/WRITE
BIT
I2C
ADDRESS
ADDRESS PIN
I2C_ADDR VALUE
MSB
6
1
1
1
1
1
1
1
1
5
0
0
0
0
0
0
0
0
4
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
LSB
0
0 (OSC MASTER)
1 (OSC SLAVE1)
2 (OSC SLAVE2)
3 (OSC SLAVE3)
I2C WRITE
I2C READ
I2C WRITE
I2C READ
I2C WRITE
I2C READ
I2C WRITE
I2C READ
1
1
1
1
1
1
1
1
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
1
0
1
0
1
0
1
Table 7. I2C Address Register Definitions
ADDRESS
0x00
TYPE
Read
REGISTER DESCRIPTION
Latched fault register 1, global and channel fault
Latched fault register 2, dc offset and overcurrent detect
Latched diagnostic register 1, load diagnostics
Latched diagnostic register 2, load diagnostics
External status register 1, temperature and voltage detect
External status register 2, Hi-Z and low-low state
External status register 3, mute and play modes
External status register 4, load diagnostics
0x01
Read
0x02
Read
0x03
Read
0x04
Read
0x05
Read
0x06
Read
0x07
Read
0x08
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
Read, Write
–
External control register 1, channel gain select
External control register 2, overcurrent control
External control register 3, switching frequency and clip pin select
External control register 4, load diagnostic, master mode select
External control register 5, output state control
External control register 6, output state control
Not used
0x09
0x0A
0x0B
0x0C
0x0D
0x0E, 0x0F
0x10
Read, Write
Read
External control register 7, dc offset detect threshold selection
0x13
External status register 5, overtemperature shutdown and thermal foldback
Table 8. Fault Register 1 (0x00) Protection
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No protection-created faults, default value
Overtemperature warning has occurred.
DC offset has occurred in any channel.
Overcurrent shutdown has occurred in any channel.
Overtemperature shutdown has occurred.
Charge-pump undervoltage has occurred.
AVDD, analog voltage, undervoltage has occurred.
PVDD undervoltage has occurred.
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
PVDD overvoltage has occurred.
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Table 9. Fault Register 2 (0x01) Protection
D7
0
D6
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No protection-created faults, default value
Overcurrent shutdown channel 1 has occurred.
Overcurrent shutdown channel 2 has occurred.
Overcurrent shutdown channel 3 has occurred.
Overcurrent shutdown channel 4 has occurred.
DC offset channel 1 has occurred.
0
–
–
–
–
–
–
1
–
–
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
1
–
–
–
–
–
DC offset channel 2 has occurred.
–
–
–
–
–
–
–
DC offset channel 3 has occurred.
1
–
–
–
–
–
–
DC offset channel 4 has occurred.
Table 10. Diagnostic Register 1 (0x02) Load Diagnostics
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No load-diagnostic-created faults, default value
Output short to ground channel 1 has occurred.
Output short to PVDD channel 1 has occurred.
Shorted load channel 1 has occurred.
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
Open load channel 1 has occurred.
–
–
–
1
–
–
–
–
Output short to ground channel 2 has occurred.
Output short to PVDD channel 2 has occurred.
Shorted load channel 2 has occurred.
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Open load channel 2 has occurred.
Table 11. Diagnostic Register 2 (0x03) Load Diagnostics
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No load-diagnostic-created faults, default value
Output short to ground channel 3 has occurred.
Output short to PVDD channel 3 has occurred.
Shorted load channel 3 has occurred.
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
Open load channel 3 has occurred.
–
–
–
1
–
–
–
–
Output short to ground channel 4 has occurred.
Output short to PVDD channel 4 has occurred.
Shorted load channel 4 has occurred.
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Open load channel 4 has occurred.
Table 12. External Status Register 1 (0x04) Fault Detection
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No protection-created faults are present, default value.
PVDD overvoltage fault is present.
PVDD undervoltage fault is present.
AVDD, analog voltage fault is present.
Charge-pump voltage fault is present.
Overtemperature shutdown is present.
Overtemperature warning
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
0
0
1
–
–
–
–
–
0
1
1
–
–
–
–
–
Overtemperature warning level 1
1
0
1
–
–
–
–
–
Overtemperature warning level 2
1
1
1
–
–
–
–
–
Overtemperature warning level 3
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Table 13. External Status Register 2 (0x05) Output State of Individual Channels
D7
0
D6
0
D5
0
D4
0
D3
1
D2
1
D1
1
D0
1
FUNCTION
Output is in Hi-Z mode, not in low-low mode(1), default value.
–
–
–
–
–
–
–
0
Channel 1 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
–
–
–
0
–
Channel 2 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
–
–
0
–
–
Channel 3 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
–
0
–
–
–
Channel 4 Hi-Z mode (0 = not Hi-Z, 1 = Hi-Z)
–
–
–
1
–
–
–
–
Channel 1 low-low mode (0 = not low-low, 1 = low-low)(1)
Channel 2 low-low mode (0 = not low-low, 1 = low-low)(1)
Channel 3 low-low mode (0 = not low-low, 1 = low-low)(1)
Channel 4 low-low mode (0 = not low-low, 1 = low-low)(1)
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
(1) Low-low is defined as both outputs actively pulled to ground.
Table 14. External Status Register 3 (0x06) Play and Mute Modes
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Mute mode is disabled, play mode disabled, default value, (Hi-Z mode).
Channel 1 play mode is enabled.
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
Channel 2 play mode is enabled.
–
–
–
–
–
1
–
–
Channel 3 play mode is enabled.
–
–
–
–
1
–
–
–
Channel 4 play mode is enabled.
–
–
–
1
–
–
–
–
Channel 1 mute mode is enabled.
–
–
1
–
–
–
–
–
Channel 2 mute mode is enabled.
–
1
–
–
–
–
–
–
Channel 3 mute mode is enabled.
1
–
–
–
–
–
–
–
Channel 4 mute mode is enabled.
Table 15. External Status Register 4 (0x07) Load Diagnostics
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
No channels are set in load diagnostics mode, default value.
Channel 1 is in load diagnostics mode.
Channel 2 is in load diagnostics mode.
Channel 3 is in load diagnostics mode.
Channel 4 is in load diagnostics mode.
Channel 1 is in overtemperature foldback.
Channel 2 is in overtemperature foldback.
Channel 3 is in overtemperature foldback.
Channel 4 is in overtemperature foldback.
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Table 16. External Control Register 1 (0x08) Gain Select
D7
1
D6
0
D5
1
D4
0
D3
1
D2
0
D1
1
D0
0
FUNCTION
Set gain for all channels to 26 dB, default value.
Set channel 1 gain to 12 dB.
–
–
–
–
–
–
0
0
–
–
–
–
–
–
0
1
Set channel 1 gain to 20 dB.
–
–
–
–
–
–
1
1
Set channel 1 gain to 32 dB.
–
–
–
–
0
0
–
–
Set channel 2 gain to 12 dB.
–
–
–
–
0
1
–
–
Set channel 2 gain to 20 dB.
–
–
–
–
1
1
–
–
Set channel 2 gain to 32 dB.
–
–
0
0
–
–
–
–
Set channel 3 gain to 12 dB.
–
–
0
1
–
–
–
–
Set channel 3 gain to 20 dB.
–
–
1
1
–
–
–
–
Set channel 3 gain to 32 dB.
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Table 16. External Control Register 1 (0x08) Gain Select (continued)
D7
0
D6
D5
–
D4
–
D3
–
D2
–
D1
–
D0
–
FUNCTION
0
1
1
Set channel 4 gain to 12 dB.
Set channel 4 gain to 20 dB.
Set channel 4 gain to 32 dB.
0
–
–
–
–
–
–
1
–
–
–
–
–
–
Table 17. External Control Register 2 (0x09) Overcurrent Control
D7
1
D6
1
D5
1
D4
1
D3
0
D2
0
D1
0
D0
0
FUNCTION
Current limit level 2 for all channels, thermal foldback is active.
Disable thermal foldback
–
–
–
–
–
–
–
1
–
–
–
0
–
–
–
–
Set channel 1 overcurrent limit ( 0 - level 1, 1 - level 2)
Set channel 2 overcurrent limit ( 0 - level 1, 1 - level 2)
Set channel 3 overcurrent limit ( 0 - level 1, 1 - level 2)
Set channel 4 overcurrent limit ( 0 - level 1, 1 - level 2)
Reserved
–
–
0
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
–
–
–
–
–
–
–
–
–
–
1
1
1
–
Table 18. External Control Register 3 (0x0A) Switching Frequency Select and Clip_OTW Configuration
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
1
1
0
1
Set fS = 417 kHz, report clip and OTW, 45° phase, disable hard stop,
CLIP_OTW pin does not report thermal foldback.
–
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
–
–
1
–
–
–
–
–
–
0
0
1
–
–
–
1
–
–
–
0
1
0
–
–
–
–
0
1
1
–
–
–
–
–
–
–
0
0
1
–
–
–
–
–
–
–
Set fS = 500 kHz
Set fS = 357 kHz
Invalid frequency selection (do not set)
Configure CLIP_OTW pin to report tweeter detect only.
Configure CLIP_OTW pin to report clip detect only.
Configure CLIP_OTW pin to report overtemperature warning only.
Enable hard-stop mode.
Set fS to a 180° phase difference between adjacent channels.
Send sync pulse from OSC_SYNC pin (device must be in master mode).
Configure CLIP_OTW pin to report thermal foldback
Table 19. External Control Register 4 (0x0B) Load Diagnostics and Master/Slave Control
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
1
0
1
0
0
0
0
Clock output disabled, master clock mode, dc offset detection enabled,
load diagnostics disabled
–
–
–
–
–
–
–
1
–
–
–
–
–
–
0
–
–
–
–
–
–
1
–
–
–
–
–
–
0
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Run channel 1 load diagnostics
Run channel 2 load diagnostics
Run channel 3 load diagnostics
Run channel 4 load diagnostics
Disable dc offset detection on all channels
Enable tweeter-detect mode
Enable slave mode (external oscillator is necessary)
Enable clock output on OSC_SYNC pin (valid only in master mode)
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Table 20. External Control Register 5 (0x0C) Output Control
D7
0
D6
0
D5
0
D4
1
D3
1
D2
1
D1
1
D0
1
FUNCTION
All channels, Hi-Z, mute, reset disabled, dc offset detect is enabled
Set channel 1 to mute mode, non-Hi-Z
Set channel 2 to mute mode, non-Hi-Z
Set channel 3 to mute mode, non-Hi-Z
Set channel 4 to mute mode, non-Hi-Z
Set non-Hi-Z channels to play mode, (unmute)
DC offsett detect shutdown disabled, but still reports a fault
Reserved
–
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
–
–
–
–
–
0
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
Reset device
Table 21. External Control Register 6 (0x0D) Output Control
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Low-low state disabled, all channels
–
–
–
–
–
–
–
1
Set channel 1 to low-low state
–
–
–
–
–
–
1
–
Set channel 2 to low-low state
–
–
–
–
–
1
–
–
Set channel 3 to low-low state
–
–
–
–
1
–
–
–
Set channel 4 to low-low state
–
–
–
1
–
–
–
–
Connect channel 1 and channel 2 for parallel BTL mode
Connect channel 3 and channel 4 for parallel BTL mode
Reserved
–
–
1
–
–
–
–
–
1
1
–
–
–
–
–
–
Table 22. External Control Register 7 (0x10) Miscellaneous Selection
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
1
Normal speed CM ramp, normal S2P & S2G timing, no delay between
LDG phases, Crosstalk Enhancement Disabled, Default DC offset detect
value (1.6V)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1
–
–
–
1
–
–
–
1
–
–
0
1
–
–
–
0
0
–
–
–
Minimum DC offset detect value (0.8 V)
Maximum DC offset detect value (2.4 V)
Enable crosstalk enhancement
Adds a 20-ms delay between load diagnostic phases
Short-to-power (S2P) and short-to-ground (S2G) load-diagnostic phases
take 4x longer
–
–
1
–
1
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Slow common-mode ramp, increase the default time by 3x
Reserved
Slower common-mode (CM) ramp-down from mute mode
Table 23. External Status Register 5 (0x13) Overtemperature and Thermal Foldback Status
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FUNCTION
Default overtemperature foldback status, no channel is in foldback
Channel 1 in thermal foldback
–
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
Channel 2 in thermal foldback
–
–
–
–
–
1
–
–
Channel 3 in thermal foldback
–
–
–
–
1
–
–
–
Channel 4 in thermal foldback
–
–
–
1
–
–
–
–
Channel 1 in overtemperature shutdown
Channel 2 in overtemperature shutdown
Channel 3 in overtemperature shutdown
Channel 4 in overtemperature shutdown
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
1
–
–
–
–
–
–
–
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The TAS5404-Q1 device is a four-channel class-D audio amplifier designed for use in automotive head units and
external amplifier modules. The TAS5404-Q1 device incorporates all the functionality required to perform in the
demanding OEM applications area.
10.2 Typical Application
Figure 20 shows a typical application circuit for the TAS5404-Q1 device.
Figure 20. TAS5404-Q1 Typical Application Schematic
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Typical Application (continued)
10.2.1 Design Requirements
•
Power Supplies
The TAS5404-Q1 device requires only a single power supply compliant with the recommended operation
range. The TAS5404-Q1 device is designed to work with either a vehicle battery or regulated boost power
supply.
•
Communication
The TAS5404-Q1 device communicates with the system controller with both discrete hardware control pins
2
2
2
and with I C. The TAS5404-Q1 device is an I C slave and thus requires a master. If a master I C-
compliant device is not present in the system, the TAS5404-Q1 device can only be used with the default
settings. Diagnostic information is limited to the discrete reporting FAULT pin.
•
External Components
Table 24 lists the components required for the TAS5404-Q1 device.
Table 24. Supporting Components
EVM Designator
Quanity
Value
0.47μF ± 10%
330 μF ± 20%
1 μF ± 10%
Size
Description
Use in Application
Analog audio input filter, bypass
Power supply
C37, C38, C47, C50
C5, C6, C7, C8
4
4
6
1206
Film, 16-V
10 mm
0805
Low-ESR aluminum capacitor, 35-V
X7R ceramic capacitor, 50-V
C9, C10, C48, C49,
C27, C28
Power supply
C45
1
4
8
2.2uF ± 10%
470nF ± 10%
470 pF ± 10%
0805
0805
0603
Film, 16-V
Analog audio input filter, bypass
Amplifier output filtering
C14, C23, C32, C42
X7R ceramic capacitor, 50-V
X7R ceramic capacitor, 50-V
C11, C15, C20,
C24, C29, C33,
C39, C43
Amplifier output snubbers
C19, C36
C4
2
1
1
2
8
0.1 μF ± 10%
2200 pF ± 10%
0.082 μF ± 10%
4.7 μF ± 10%
0.47 μF ± 10%
0603
0603
0603
1206
0603
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 50-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 25-V
X7R ceramic capacitor, 25-V
Power supply
Power supply
Power supply
Power supply
Output EMI filtering
C3
C1, C2
C12, C17, C21,
C25, C30, C34,
C40, C44
C15
L1
1
1
220nF ± 10%
0603
X7R ceramic capacitor, 25-V
Mute timing
10 μH ± 20%
13.5 mm ×13.5 Shielded ferrite inductor
mm
Power supply
L2, L3, L4, L5, L6,
L7, L8, L9
8
10 μH ± 20%
12 mm × 14
mm
Dual inductor
Amplifier output filtering
R1, R2
2
8
49.9 kΩ ± 1%
5.6 Ω ± 5%
0805
0805
Resistors, 0.125-W
Resistors, 0.125-W
Analog audio input filter
Output snubbers
R3, R4, R5, R6, R8,
R9, R10, R11
R7
1
20.0 kΩ ± 1%
0805
Resistors, 0.125-W
Power supply
10.2.2 Detailed Design Procedure
10.2.2.1 Hardware and Software Design
1. Hardware Schematic Design: Using Figure 20 as a guide, integrate the hardware into the system schematic.
2. Following the recommended layout guidelines, integrate the TAS5404-Q1 device and the supporting
components into the system PCB file.
3. Thermal Design: The TAS5404-Q1 device has an exposed thermal pad which requires proper soldering. For
more information, see the application reports Semiconductor and IC Package Thermal Metrics (SPRA953),
and the PowerPAD Thermally Enhanced Package (SLMA002G).
4. Develop software: The EVM User's Guide has detailed instructions for how to set up the TAS5404-Q1
device, interpret diagnostic information, and so forth. For information about control registers, see the Table 7
section.
For questions and support go to the E2E forums.
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10.2.2.2 Parallel Operation (PBTL)
The TAS5404-Q1 device can drive more current by paralleling BTL channels on the load side of the LC output
filter. Parallel operation requires identical I2C settings for any two paralleled channels to have reliable system
performance and even power dissipation on multiple channels. For smooth power up, power down, and mute
operation, the same control commands (such as mute, play, Hi-Z, and so on) should be sent to the paralleled
channels at the same time. The TAS5404-Q1 device also supports load diagnostics for parallel connection.
Paralleling on the TAS5404-Q1 device side of the LC output filter is not supported, because it can result in
device failure. When paralleling channels, use the parallel BTL I2C control bits in register 0x0D. Parallel channels
1 and 2, and/or channels 3 and 4. Setting these bits allows the thermal foldback to react on both channels
equally. Provide the audio input to channel 2 if paralleing channels 1 and 2, and channel 3 if paralleling channels
3 and 4.
10.2.2.3 Input Filter Design
The IN_M pin should have an impedance to GND that is equivalent to the parallel combination of the input
impedances of all IN_P channels combined, including any source impedance from the previous stage in the
system design. For example, if each of the four IN_P channels have a 1-µF dc blocking capacitor, 1 kΩ of series
resistance due to an input RC filter, and 1 kΩ of source resistance from the DAC supplying the audio signal, then
the IN_M channel should have a 4-µF capacitor in series with a 500-Ω resistor to GND (4 × 1 µF in parallel = 4
µF; 4 × 2 kΩ in parallel = 500 Ω).
10.2.2.4 Amplifier Output Filtering
The output FETs drive the amplifier outputs in an H-bridge configuration. These transistors are either fully off or
on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the audio
signal. The amplifier outputs require a low-pass filter to filter out the PWM modulation carrier frequency. People
frequently call the filter the L-C filter, due to the presence of an inductive element L and a capacitive element C
to make up the 2-pole low-pass filter. The L-C filter attenuates the carrier frequency, reducing electromagnetic
emissions and smoothing the current waveform which the load draws from the power supply. See the Class-D
LC Filter Design application report (SLOA119) for a detailed description on proper component selection and
design of an L-C filter based upon the desired load and response.
10.2.2.5 Line Driver Applications
In many automotive audio applications, the end user would like to use the same head unit to drive either a
speaker (with several ohms of impedance) or an external amplifier (with several kilohms of impedance). The
design is capable of supporting both applications; however, the one must design the output filter and system to
handle the expected output load conditions.
10.2.3 Application Curves
14
12
10
8
100
90
80
70
60
50
40
30
20
10
0
6
4
2
TAS5404-Q1 only
System Efficiency
0
0
10
20
30
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Output Power per Channel
Power per Channel (W)
C002
C001
Figure 21. Efficiency
Figure 22. TAS5404-Q1 Device Power Dissipation
Four Channels AT 4 Ω Each
Four Channels at 4 Ω Each
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11 Power Supply Recommendations
A car battery that can have a large voltage range most commonly provides the power for the TAS5404-Q1
device. PVDD is a filtered battery voltage, and it is the supply for the output FETS and the low-side FET gate
driver. The supply for the high-side FET gate driver comes from a charge pump (CP). The charge pump supplies
the gate-drive voltage for all four channels. An internal linear regulator provides AVDD which powers the analog
circuitry. The supply requires a 0.1-μF, 10-V external bypass capacitor at the A_BYP pin. TI does not
recommend connecting any external components except the bypass capacitor to the A_BYP pin. DVDD, which
comes from an internal linear regulator, powers the digital circuitry. The D_BYP pin requires a 0.1-μF, 10-V
external bypass capacitor. TI does not recommend connecting any external components except the bypass
capacitor to the A_BYP pin.
The TAS5404-Q1 device can withstand fortuitous open-ground and open-power conditions. Fortuitous open
ground usually occurs when a speaker wire shorts to ground, which allows for a second ground path through the
body diode in the output FETs. The diagnostic capability allows debugging of the speakers and speaker wires,
which eliminates the necessity to remove the amplifier to diagnose the problem.
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12 Layout
12.1 Layout Guidelines
•
•
•
•
The EVM layout optimizes for low noise and EMC performance.
The TAS5404-Q1 device has a thermal pad up, so a the layout must take into account an external heatsink.
Layout also affects EMC performance.
The EVM PCB illustrations form the basis for the layout discussions.
12.2 Layout Example
The areas in Figure 23 and Figure 24 indicated by the label "A", are critical to proper operation and EMC layout.
The PVDD and ground-decoupling capacitors should be close to the TAS5404-Q1 device. These ground-
decoupling capacitors must be on both groups of PVDD pins to ground. The ground connections of the snubber
circuits must also be close to the grounds of the TAS5404-Q1 device.
Figure 23. TAS5404 Board Layout - Top View
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Figure 24. TAS5404 Board Layout - Bottom View
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Each layer in the EVM contains a ground plane. All the ground planes should be connected together through
many vias to reduce the impedance between the ground layers, which provides for low inductance paths for
reduced EMI.
Figure 25. TAS5404 Board Layout - Bottom Layer
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12.3 Thermal Consideration
The design of the thermally augmented package is to interface directly to heat sinks using a thermal interface
compound (for example, Arctic Silver®, Ceramique thermal compound). The heat sink then absorbs heat from the
ICs and couples it to the local air. With proper thermal management the process can reach equilibrium at a lower
temperature, and heat can be continually removed from the ICs. Because of the efficiency of the TAS5404-Q1
device, heat sinks can be smaller than those required for linear amplifiers of equivalent performance.
RθJA is a system thermal resistance from junction to ambient air. As such, it is a system parameter with the
following components:
•
•
•
RθJC (the thermal resistance from junction to case, or in this case the heat slug)
Thermal resistance of the thermal grease
Thermal resistance of the heat sink
One can calculate the thermal resistance of the thermal grease from the exposed heat slug area and the
manufacturer's value for the area thermal resistance of the thermal grease (expressed in °C-in2/W or °C-mm2/W).
The area thermal resistance of the example thermal grease with a 0.001-inch (0.0254-mm) thick layer is about
0.007°C-in2/W (4.52°C-mm2/W). The approximate exposed heat slug size for a 64-pin QFP is 0.099 in2 (64 mm2)
Dividing the example area thermal resistance of the thermal grease by the area of the heat slug gives the actual
resistance through the thermal grease for both parts, which is 0.07°C/W.
The thermal resistance of thermal pads is generally considerably higher than a thin thermal-grease layer.
Thermal tape has an even higher thermal resistance and should not be used at all. The heat-sink vendor
generally predicts heat sink thermal resistance, either modeled using a continuous-flow dynamics (CFD) model,
or measured.
Therefore, for a single monaural channel in the IC, the system RθJA = RθJC + thermal-grease resistance + heat-
sink resistance.
Table 25 indicates modeled parameters for one TAS5404-Q1 device on a heat sink. The exposed pad
dimensions are 8 mm × 8 mm. The junction temperature setting is at 115°C while delivering 20 watts per channel
into 4-Ω loads with no clipping. The assumed thickness of the thermal grease is about 0.001 inches (0.0254
mm).
Table 25. QFP Package Modeled Parameters
DEVICE
Ambient temperature
Power to load
64-PIN QFP
25
UNIT
°C
20
W × 4
W × 4
°C
Power dissipation
1.9
ΔT inside package
7.6
ΔT through thermal grease
Required heatsink thermal resistance
Junction temperature
System RθJA
0.46
10.78
115
°C
°C/W
°C
11.85
90
°C/W
°C
RθJA × power dissipation
12.4 Electrical Connection of Heat Slug and Heat Sink
Electrically connect the heat sink attached to the heat slug of the TAS5404-Q1 device to GND, or leave it
floating. Do not connect the heat slug to any other electrical node.
12.5 EMI Considerations
Automotive-level EMI performance depends on both careful integrated circuit design and good system-level
design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the
design.
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EMI Considerations (continued)
The design has minimal parasitic inductances due to the short leads on the package. This dramatically reduces
the EMI that results from current passing from the die to the system PCB. Each channel also operates at a
different phase. The phase between channels is I2C selectable to either 45° or 180°, to reduce EMI caused by
high-current switching. The design also incorporates circuitry that optimizes output transitions that cause EMI.
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 Trademarks
E2E is a trademark of Texas Instruments.
Arctic Silver is a registered trademark of Arctic Silver.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TAS5404TPHDRQ1
ACTIVE
HTQFP
PHD
64
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 105
TAS5404TQ1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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11-Oct-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS5404TPHDRQ1
HTQFP
PHD
64
1000
330.0
24.4
17.0
17.0
1.5
20.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2015
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTQFP PHD 64
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
TAS5404TPHDRQ1
1000
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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