TAS5614PHDR_技术文档

TAS5614A

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SLAS712 –JUNE 2010

150W STEREO / 300W MONO PurePath™ HD DIGITAL-INPUT POWER STAGE

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1

FEATURES

APPLICATIONS

•

Home Theater Systems

AV Receivers

DVD/Blu-ray™ Receivers

Mini Combo Systems

Active Speakers and Subwoofers

23

•

PurePath™ HD Enabled Integrated Feedback

Provides:

–

Signal Bandwidth up to 80kHz for High

Frequency Content From HD Sources

–

Ultralow 0.03% THD at 1W into 4Ω

Ultralow 0.01% THD at 1W into 8Ω

DESCRIPTION

Flat THD at all Frequencies for Natural

Sound

The TAS5614A is a high performance analog input

Class

D amplifier with integrated closed loop

–

80dB PSRR (BTL, No Input Signal)

>100dB (A weighted) SNR

feedback technology (known as PurePath™ HD) with

the ability to drive up to 150W Stereo into 4 to 8 Ω

Speakers from a single 36V supply.

(1)

Click and Pop Free Startup

•

Pin compatible with TAS5631, TAS5616 and

TAS5612

PurePath™ HD technology enables traditional

AB-Amplifier performance (<0.03% THD) levels while

providing the power efficiency of traditional class D

amplifiers.

Multiple Configurations Possible on the Same

PCB With Stuffing Options:

–

Mono Parallel Bridge Tied Load (PBTL)

Stereo Bridge Tied Load (BTL)

Unlike traditional Class D amplifiers, the distortion

curve only increases once the output levels move into

clipping. PurePath™ HD Power PAD™

2.1 Single Ended Stereo Pair and Bridge

Tied Load Subwoofer

PurePath™ HD technology enables lower idle losses

making the device even more efficient.

•

Total Output Power at 10%THD+N

TOTAL HARMONIC DISTORTION+NOISE

VS

OUTPUT POWER

–

300W in Mono PBTL Configuration

150W per Channel in Stereo BTL

Configuration

10

4Ohm (6kHz)

4Ohm (1kHz)

Total Output Power in BTL Configuration at

1%THD+N

1

–

160W Stereo into 3Ω

125W Stereo into 4Ω

85W Stereo into 6Ω

65W Stereo into 8Ω

0,1

0,01

•

>90% Efficient Power Stage With 60-mΩ

Output MOSFETs

TC = 75 C

CONFIG = BTL

0,001

0,01

Self-Protection Design (Including

1

100

Undervoltage, Overtemperature, Clipping, and

Short-Circuit Protection) With Error Reporting

P_O- Output Power - W

•

EMI Compliant When Used With

Recommended System Design

(1) Achievable output power levels are dependent on the thermal

configuration of the target application. A high performance

thermal interface material between the package exposed

heatslug and the heat sink should be used to achieve high

output power levels.

Two Thermally Enhanced Package Options:

–

PHD (64-Pin QFP)

DKD (44-Pin PSOP3)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

PurePath, Power PAD are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TAS5614A

SLAS712 –JUNE 2010

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DEVICE INFORMATION

Terminal Assignment

Both package types contains a heat slug that is located on the top side of the device for convenient thermal

coupling to the heat sink.

PHD PACKAGE

(TOP VIEW)

DKD PACKAGE

(TOP VIEW)

PSU_REF

VDD

1

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

GVDD_AB

BST_A

2

OC_ADJ

RESET

3

PVDD_A

OUT_A

GND_A

GND_B

OUT_B

PVDD_B

BST_B

44 pins PACKAGE

(TOP VIEW)

4

OC_ADJ

RESET

C_STARTUP

INPUT_A

INPUT_B

VI_CM

GND

AGND

VREG

INPUT_C

INPUT_D

TEST

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

GND_A

1

2

3

4

5

6

7

8

C_STARTUP

INPUT_A

INPUT_B

VI_CM

5

GND_B

OUT_B

PVDD_B

BST_B

BST_C

PVDD_C

OUT_C

GND_C

6

7

8

GND

9

10

11

12

13

14

15

16

17

18

19

20

21

22

AGND

VREG

9

10

11

12

13

14

15

16

INPUT_C

INPUT_D

TEST

NC

BST_C

PVDD_C

OUT_C

GND_C

GND_D

OUT_D

PVDD_D

BST_D

NC

SD

64-pins QFP package

NC

GND_D

OTW1

SD

OTW

READY

M1

M2

M3

GVDD_CD

PIN ONE LOCATION PHD PACKAGE

Electrical Pin 1

Pin 1 Marker

White Dot

2

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SLAS712 –JUNE 2010

MODE SELECTION PINS

MODE PINS

OUTPUT

CONFIGURATION

PWM INPUT⁽¹⁾

DESCRIPTION

M3

0

M2

0

M1

0

2N

—

2 × BTL

—

AD mode

Reserved

BD mode

AD mode

0

1

0

1

0

2N

1N

2 × BTL

0

1

1 × BTL +2 ×SE

4 × SE

1

0

INPUT_C⁽²⁾

INPUT_D⁽²⁾

2N

1N

1

0

1

1 × PBTL

0

1

0

AD mode

BD mode

1

0

1

Reserved

(1) The 1N and 2N naming convention is used to indicate the number of PWM lines to the power stage per channel in a specific mode.

(2) INPUT_C and D are used to select between a subset of AD and BD mode operations in PBTL mode

PACKAGE HEAT DISSIPATION RATINGS⁽¹⁾

PARAMETER

TAS5614APHD

TAS5614ADKD

R

_qJC(°C/W) – 2 BTL or 4 SE channels

3.2

5.4

2.1

3.5

R_qJC(°C/W) – 1 BTL or 2 SE channel(s)

R_qJC(°C/W) – 1 SE channel

7.9

5.1

(2)

Pad Area

64mm²

80mm²

(1) J_Cis junction-to-case, C_His case-to-heat sink

(2) _qCHis an important consideration. Assume a 2-mil thickness of thermal grease with a thermal conductivity of 2.5 W/mK between the

R

pad area and the heat sink and both channels active. The R_qCHwith this condition is 1.1°C/W for the PHD package and 0.44°C/W for

the DKD package.

Table 1. ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE

DESCRIPTION

64 pin HTQFP

44 pin PSOP3

0°C–70°C

TAS5614APHD

TAS5614ADKD

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

(1)

TAS5614A

UNIT

V

VDD to GND

–0.3 to 13.2

–0.3 to 53

–0.3 to 66.2

–0.3 to 53

–0.3 to 4.2

–0.3 to 0.3

–0.3 to 4.2

GVDD to GND

V

PVDD_X to GND_X⁽²⁾

OUT_X to GND_X⁽²⁾

BST_X to GND_X⁽²⁾

BST_X to GVDD_X⁽²⁾

VREG to GND

V

GND_X to GND

V

GND to AGND

V

OC_ADJ, M1, M2, M3, OSC_IO+, OSC_IO-, FREQ_ADJ, VI_CM, C_STARTUP, PSU_REF

to GND

V

INPUT_X

–0.3 to 7

9

V

RESET, SD, OTW1, OTW2, CLIP, READY to GND

Maximum continuous sink current (SD, OTW1, OTW2, CLIP, READY)

Maximum operating junction temperature range, T_J

Storage temperature, T_stg

mA

°C

kV

V

0 to 150

–40 to 150

±2

Human body model⁽³⁾(all pins)

Charged device model⁽³⁾(all pins)

Electrostatic discharge

±500

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.

(3) Failure to follow good anti-static ESD handling during manufacture and rework will contribute to device malfunction. Make sure the

operators handling the device are adequately grounded through the use of ground straps or alternative ESD protection.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM

MAX UNIT

PVDD_x

GVDD_x

Half-bridge supply

DC supply voltage

18

36

38

13.2

V

Supply for logic regulators and gate-drive

circuitry

10.8

12

VDD

Digital regulator supply voltage

10.8

3.5

2.8

1.6

12

4

R_L(BTL)

R_L(SE)

R_L(PBTL)

Output filter according to schematics in

the application information section.

Load impedance

3

Ω

Ω

2

Output filter according to schematics in

the application information section. R_OC

22kΩ, add Schottky diodes from OUT_X

to GND_X.

=

R_L(BTL)

Load impedance

2.8

3

L_OUTPUT(BTL)

L_OUTPUT(SE)

L_OUTPUT(PBTL)

F_PWM

7

10

15

10

Output filter inductance

Minimum output inductance at I_OC

mH

PWM frame rate

352 384

2

500

150

kHz

mF

C_PVDD

PVDD close decoupling capacitors

Over-current programming resistor

Junction temperature

R_OC

Resistor tolerance = 5%

22

47

0

30

64

kΩ

°C

R_{OC_LATCHED}

T_J

4

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SLAS712 –JUNE 2010

PIN FUNCTIONS

FUNCTION⁽¹⁾

DESCRIPTION

NAME

PHD NO.

DKD NO.

10

43

34

33

24

—

AGND

8

P

O

I

Analog ground

BST_A

BST_B

BST_C

BST_D

CLIP

54

HS bootstrap supply (BST), external 0.033mF capacitor to OUT_A required.

HS bootstrap supply (BST), external 0.033mF capacitor to OUT_B required.

HS bootstrap supply (BST), external 0.033mF capacitor to OUT_C required.

HS bootstrap supply (BST), external 0.033mF capacitor to OUT_D required.

Clipping warning; open drain; active low

Startup ramp requires a charging capacitor of 4.7nF to GND

Connect to VREG node

41

40

27

18

C_STARTUP

TEST

3

5

12

14

9

GND

7, 23, 24, 57, 58

P

I

Ground

GND_A

GND_B

GND_C

GND_D

GVDD_A

GVDD_B

GVDD_C

GVDD_D

GVDD_AB

GVDD_CD

INPUT_A

INPUT_B

INPUT_C

INPUT_D

M1

48, 49

46, 47

34, 35

32, 33

55

38

37

30

29

—

Power ground for half-bridge A

Power ground for half-bridge B

Power ground for half-bridge C

Power ground for half-bridge D

Gate drive voltage supply requires 0.1mF capacitor to GND

Gate drive voltage supply requires 0.22mF capacitor to GND

Input signal for half bridge A

56

—

25

—

26

—

44

23

6

—

4

5

7

I

Input signal for half bridge B

10

12

13

20

21

22

–

I

Input signal for half bridge C

11

I

Input signal for half bridge D

20

I

Mode selection

M2

21

I

Mode selection

M3

22

I

Mode selection

NC

59–62

13, 14

1

—

O

P

No connect, pins may be grounded.

NC

15, 16

3

No connect, pins may be grounded.

OC_ADJ

OTW

Analog overcurrent programming pin requires resistor to ground.

Overtemperature warning signal, open drain, active low.

Output, half bridge A

—

18

—

OTW1

16

OTW2

17

—

OUT_A

OUT_B

OUT_C

OUT_D

PSU_REF

52, 53

44, 45

36, 37

28, 29

63

39, 40

36

31

27, 28

1

Output, half bridge B

Output, half bridge C

Output, half bridge D

PSU Reference requires close decoupling of 4.7mF to GND

Power supply input for half bridges A requires close decoupling of 2mF capacitor to

GND_A

PVDD_A

PVDD_B

PVDD_C

PVDD_D

50, 51

42, 43

38, 39

30, 31

41, 42

35

P

Power supply input for half bridges B requires close decoupling of 2mF capacitor to

GND_B

Power supply input for half bridges C requires close decoupling of 2mF capacitor to

GND_C

32

Power supply input for half bridges D requires close decoupling of 2mF capacitor to

GND_D

25, 26

READY

RESET

SD

19

2

19

4

O

I

Normal operation; open drain; active high

Device reset Input; active low

15

17

O

Shutdown signal, open drain, active low

Power supply for digital voltage regulator requires a 47mF capacitor in parallel with a

0.1mF capacitor to GND for decoupling.

VDD

64

6

2

8

P

VI_CM

O

Analog comparator reference node requires close decoupling of 4.7mF to GND

(1) I = Input, O = Output, P = Power

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PIN FUNCTIONS (continued)

FUNCTION⁽¹⁾

DESCRIPTION

NAME

PHD NO.

DKD NO.

VREG

9

11

P

Digital regulator supply filter pin requires 0.1mF capacitor to GND

TYPICAL SYSTEM BLOCK DIAGRAM

Caps for

External

Filtering

and

System

microcontroller

AMP RESET

I2C

(2)

Startup/Stop

TAS5518/

TAS5508/

TAS5086

*NOTE1

RESET

BST_A

VALID

Bootstrap

Caps

BST_B

2^ndOrder

OUT_A

L-C Output

PWM_A

PWM_B

INPUT_A

INPUT_B

Left-

Channel

Output

Input

H-Bridge 1

Output

H-Bridge 1

2

Filter for

each

H-Bridge

OUT_B

2

2-CHANNEL

H-BRIDGE

BTL MODE

2^ndOrder

L-C Output

Filter for

each

PWM_C

PWM_D

INPUT_C

INPUT_D

OUT_C

Right-

Channel

Output

Input

H-Bridge 2

Output

H-Bridge 2

2

OUT_D

2

H-Bridge

M1

BST_C

BST_D

Hardwire

Mode

Control

M2

M3

Bootstrap

Caps

8

4

Hardwire

PVDD

GND

PVDD

Power Supply

Decoupling

GVDD, VDD,

3560VV

Over-

Current

Limit

and VREG

Power Supply

Decoupling

SYSTEM

Power

Supplies

GND

12V

GVDD (12V)/VDD (12V)

VAC

(1) Logic AND is inside or outside the micro controller.

6

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SLAS712 –JUNE 2010

FUNCTIONAL BLOCK DIAGRAM

CLIP

READY

OTW1

OTW2

SD

M1

M2

M3

VDD

POWER-UP

RESET

UVP

VREG

AGND

GND

RESET

TEMP

SENSE

GVDD_A

GVDD_C

STARTUP

CONTROL

GVDD_B

GVDD_D

C_STARTUP

OVER-LOAD

PROTECTION

CURRENT

SENSE

CB3C

OC_ADJ

4

PVDD_X

OUT_X

GND_X

PPSC

GVDD_A

BST_A

PWM

ACTIVITY

DETECTOR

PVDD_A

OUT_A

GND_A

GVDD_B

BST_B

PWM

RECEIVER

TIMING

CONTROL

GATE-DRIVE

PSU_REF

VI_CM

-

ANALOG

LOOP FILTER

INPUT_A

+

PVDD_B

OUT_B

GND_B

GVDD_C

BST_C

PWM

RECEIVER

TIMING

CONTROL

+

-

ANALOG

LOOP FILTER

INPUT_B

4

PVDD_X

AGC

GND

INPUT_C

PVDD_C

OUT_C

GND_C

GVDD_D

BST_D

-

ANALOG

LOOP FILTER

+

PWM

RECEIVER

TIMING

CONTROL

INPUT_D

+

-

ANALOG

LOOP FILTER

PVDD_D

OUT_D

GND_D

PWM

RECEIVER

TIMING

CONTROL

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AUDIO CHARACTERISTICS (BTL)

Audio performance is recorded as a chipset consisting of a TAS5518 PWM Processor (modulation index limited to 97.7%)

and a TAS5614A power stage. PCB and system configurations are in accordance with recommended guidelines. Audio

frequency = 1kHz, PVDD_X = 36V, GVDD_X = 12V, R_L= 4Ω, f_S= 384 kHz, R_OC= 30kΩ, T_C= 75°C,

Output Filter: L_DEM= 7mH, C_DEM= 680nF, MODE = 000, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

R_L= 3Ω, 10% THD+N (R_OC= 22kΩ, add Schottky

diodes from OUT_X to GND_X.)

200

R_L= 4Ω, 10% THD+N

150

W

P_O

Power output per channel

R_L= 3Ω, 1% THD+N (R_OC= 22kΩ, add Schottky

diodes from OUT_X to GND_X.)

160

R_L= 4Ω, 1% THD+N

1 W, R_L= 4Ω

125

0.03%

THD+N Total harmonic distortion + noise

1 W, R_L= 8Ω

0.01%

125

20

V_n

Output integrated noise

Output offset voltage

Signal-to-noise ratio⁽¹⁾

A-weighted, TAS5518 Modulator

No signal

mV

40 mV

dB

|V_OS

|

SNR

A-weighted, TAS5518 Modulator

103

A-weighted, input level –60 dBFS using TAS5518

modulator

DNR

Dynamic range

103

2.6

dB

W

Power dissipation due to Idle losses

P_idle

P_O= 0, 4 channels switching⁽²⁾

(I_{PVDD_X}

)

(1) SNR is calculated relative to 1% THD-N output level.

(2) Actual system idle losses also are affected by core losses of output inductors.

8

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AUDIO CHARACTERISTICS (PBTL)

Audio performance is recorded as a chipset consisting of a TAS5518 PWM Processor (modulation index limited to 97.7%)

and a TAS5614A power stage. PCB and system configurations are in accordance with recommended guidelines. Audio

frequency = 1kHz, PVDD_X = 36V, GVDD_X = 12V, R_L= 2Ω, f_S= 384kHz, R_OC= 30kΩ, T_C= 75°C,

Output Filter: L_DEM= 7mH, C_DEM= 1mF, MODE = 101-00, unless otherwise noted.

PARAMETER

TEST CONDITIONS

R_L= 2Ω, 10%, THD+N

MIN

TYP MAX UNIT

300

200

R_L= 3Ω, 10%, THD+N

R_L= 4Ω, 10%, THD+N

R_L= 2Ω, 1% THD+N

R_L= 3Ω, 1% THD+N

R_L= 4Ω, 1% THD+N

1 W

160

P_O

Power output per channel

W

250

160

130

THD+N Total harmonic distortion + noise

0.03%

128

V_n

Output integrated noise

Signal to noise ratio⁽¹⁾

A-weighted, TAS5518 Modulator

mV

SNR

103

2.4

dB

A-weighted, input level –60 dBFS using

TAS5518 modulator

P_O= 0, 4 channels switching⁽²⁾

DNR

P_idle

Dynamic range

dB

W

Power dissipation due to idle losses (I_{PVDD_X}

)

(1) SNR is calculated relative to 1% THD-N output level.

(2) Actual system idle losses are affected by core losses of output inductors.

ELECTRICAL CHARACTERISTICS

PVDD_X = 36V, GVDD_X = 12V, VDD = 12V, T_C(Case temperature) = 75°C, f_S= 384kHz, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION

Voltage regulator, only used as reference

node, VREG

VREG

VI_CM

VDD = 12V

3

3.3

3.6

1.9

V

Analog comparator reference node, VI_CM

1.5

1.75

20

Operating, 50% duty cycle

Idle, reset mode

50% duty cycle

I_VDD

VDD supply current

mA

20

10

I_{GVDD_x}

Gate-supply current per half-bridge

Reset mode

1.5

50% duty cycle without output filter or

load

16.8

620

mA

I_{PVDD_x}

Half-bridge idle current

Reset mode, No switching

mA

OUTPUT-STAGE MOSFETs

Drain-to-source resistance, low side (LS)

Drain-to-source resistance, high side (HS)

T_J= 25°C, excludes metallization

resistance,

GVDD = 12V

60 100

mΩ

R_DS(on)

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ELECTRICAL CHARACTERISTICS (continued)

PVDD_X = 36V, GVDD_X = 12V, VDD = 12V, T_C(Case temperature) = 75°C, f_S= 384kHz, unless otherwise specified.

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

I/O PROTECTION

V_uvp,G

Undervoltage protection limit, GVDD_x

10

V

(1)

V_uvp,hyst

0.6

OTW1⁽¹⁾

OTW2⁽¹⁾

Overtemperature warning 1

Overtemperature warning 2

95

100 105

125 135

°C

115

Temperature drop needed below OTW

temperature for OTW to be inactive after

OTW event.

(1)

OTW_hyst

25

°C

Overtemperature error

OTE-OTW differential

145

155 165

30

°C

OTE⁽¹⁾

A reset needs to occur for SD to be released

following an OTE event

(1)

OTE_HYST

25

2.6

14

°C

OLPC

Overload protection counter

Overcurrent limit protection

f_PWM= 384kHz

ms

Resistor – programmable, nominal peak

current in 1Ω load, R_OCP= 30kΩ

Resistor – programmable, nominal peak

current in 1Ω load, R_OCP= 22kΩ

(With Schottky diodes from OUT_X to

GND_X.)

I_OC

A

18

14

18

Resistor – programmable, nominal peak

current in 1Ω load, R_OCP= 64kΩ

Resistor – programmable, nominal peak

current in 1Ω load, R_OCP= 47kΩ

(With Schottky diodes from OUT_X to

GND_X.)

I_{OC_LATCHED}

Overcurrent limit protection

Overcurrent response time

Time from application of short condition to

Hi-Z of affected half bridge

I_OCT

150

3

ns

Connected when RESET is active to

provide bootstrap charge. Not used in SE

mode.

Internal pulldown resistor at output of each

half bridge

I_PD

mA

STATIC DIGITAL SPECIFICATIONS

V_IH

V_IL

I_lkg

High level input voltage

Low level input voltage

Input leakage current

1.9

20

V

INPUT_X, M1, M2, M3, RESET

0.8

100

mA

OTW/SHUTDOWN (SD)

Internal pullup resistance, OTW1 to VREG,

R_{INT_PU}

V_OH

26

33

kΩ

OTW2 to VREG, SD to VREG

High level output voltage

Low level output voltage

Internal pullup resistor

External pullup of 4.7kΩ to 5V

I_O= 4mA

3

3.3

3.6

5

V

4.5

V_OL

200 500

mV

Device fanout OTW1, OTW2, SD, CLIP,

READY

FANOUT

No external pullup

30

devices

(1) Specified by design.

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION

TOTAL HARMONIC+NOISE

vs

OUTPUT POWER

vs

SUPPLY VOLTAGE

250

200

150

100

10

1

T

= 75°C

T

= 75°C

C

THD+N 10%

3 W

C

4 W

6 W

3 W

4 W

8 W

6 W

8 W

0.1

0.01

50

0

0.001

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

- Supply Voltage - V

0.01

0.1

1 10

- Output Power - W

100

1000

PV

DD

P

O

Figure 1.

Figure 2.

UNCLIPPED OUTPUT POWER

SYSTEM EFFICIENCY

vs

SUPPLY VOLTAGE

OUTPUT POWER

100

90

200

150

100

T

= 75°C

C

4 W

6 W

8 W

80

3 W

70

60

4 W

6 W

8 W

50

40

30

20

50

0

T

C

THD+N = 10%

= 25°C

10

0

200 300

2 Channel Output Power - W

0

50

100 150

250

350 400

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

- Supply Voltage - V

PV

DD

Figure 3.

Figure 4.

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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)

SYSTEMS POWER LOSS

vs

OUTPUT POWER

vs

OUTPUT POWER

CASE TEMPERATURE

30

250

200

150

100

T

= 25°C

THD+N = 10%

C

THD+N = 10%

3 W

4 W

20

6 W

10

8 W

50

0

8 W

0

200 300

2 Channel Output Power - W

0

50

100 150

250

350 400

100

20

30

40

T

C

50

60

70

- Case Temperature - °C

80

90

Figure 5.

Figure 6.

NOISE AMPLITUDE

vs

TOTAL HORMONIC DISTORTION+NOISE

vs

FREQUENCY

0

10

1

R

T

= 4 W,

T

= 75°C,

L

C

REF = 25.46 V,

= 75°C,

-20

-40

C

Sample Rate = 48 kHz,

FFT Size = 16384

Toroidal Output Inductors

-60

-80

0.1

-100

-120

1W

0.01

0.001

4 W

-140

-160

21 W (1/8 Power)

1k 10k

0

5

10 15

f - Frequency - kHz

20

10

100

100k

f - Frequency - Hz

Figure 7.

Figure 8.

12

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TYPICAL CHARACTERISTICS, PBTL CONFIGURATION

TOTAL HARMONIC+NOISE

OUTPUT POWER

vs

OUTPUT POWER

SUPPLY VOLTAGE

400

350

10

1

T

= 75°C

T

= 75°C

2 W

C

THD+N = 10%

3 W

4 W

2 W

300

250

200

150

100

3 W

6 W

4 W

8 W

6 W

0.1

8 W

0.01

50

0

0.001

18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

- Supply Voltage - V

0.01

0.1

1 10

- Output Power - W

100

1000

PV

P

DD

O

Figure 9.

Figure 10.

OUTPUT POWER

vs

CASE TEMPERATURE

400

THD+N = 10%

2 W

350

300

250

200

150

100

3 W

4 W

6 W

8 W

50

0

20

30

40

50

60

70

80

90

100

T

- Case Temperature - °C

C

Figure 11.

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APPLICATION INFORMATION

PCB MATERIAL RECOMMENDATION

FR-4 Glass Epoxy material with 2oz. (70mm) is recommended for use with the TAS5614A. The use of this

material can provide for higher power output, improved thermal performance, and better EMI margin (due to

lower PCB trace inductance.

PVDD CAPACITOR RECOMMENDATION

The large capacitors used in conjunction with each full-bridge, are referred to as the PVDD Capacitors. These

capacitors should be selected for proper voltage margin and adequate capacitance to support the power

requirements. In practice, with a well designed system power supply, 1000mF, 50V support more applications.

The PVDD capacitors should be low ESR type because they are used in a circuit associated with high-speed

switching.

DECOUPLING CAPACITOR RECOMMENDATION

To design an amplifier that has robust performance, passes regulatory requirements, and exhibits good audio

performance, good quality decoupling capacitors should be used. In practice, X7R should be used in this

application.

The voltage of the decoupling capacitors should be selected in accordance with good design practices.

Temperature, ripple current, and voltage overshoot must be considered. This fact is particularly true in the

selection of the 0.1mF that is placed on the power supply to each half-bridge. It must withstand the voltage

overshoot of the PWM switching, the heat generated by the amplifier during high power output, and the ripple

current created by high power output. A minimum voltage rating of 50V is required for use with a 36V power

supply.

SYSTEM DESIGN RECOMMENDATIONS

The following schematics and PCB layouts illustrate best practices in the use of the TAS5614A.

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G N D _ A

P V D D _ A

O U T _ A

G N D _ D

P V D D _ D

O U T _ D

B S T _ D

G V D D _ D

G V D D _ C

G N D

O U T _ A

B S T _ A

G V D D _ A

G V D D _ B

G N D

N C

G N D

M 3

N C

M 2

M 1

R E A D Y

/ C L I P

P S U _ R E F

V D D

/ O T W 2

Figure 12. Typical Differential (2N) BTL Application With BD Modulation Filters

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G N D _ A

P V D D _ A

O U T _ A

G N D _ D

3 2

4 9

5 0

5 1

5 2

5 3

5 4

5 5

5 6

5 7

5 8

5 9

6 0

6 1

6 2

6 3

6 4

P V D D _ D

3 1

P V D D _ D

3 0

O U T _ D

2 9

O U T _ A

O U T _ D

2 8

B S T _ A

B S T _ D

2 7

G V D D _ A

G V D D _ B

G V D D _ D

2 6

G V D D _ C

2 5

G N D

N C

G N D

2 4

G N D

2 3

M 3

2 2

N C

M 2

2 1

M 1

2 0

R E A D Y

1 9

P S U _ R E F

/ C L I P

1 8

V D D

/ O T W 2

1 7

Figure 13. Typical (2N) PBTL Application With BD Modulation Filters

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Figure 14. Typical Differential Input BTL Application with BD Modulation Filters DKD Package

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THEORY OF OPERATION

POWER SUPPLIES

To facilitate system design, the TAS5614A needs only a 12V supply in addition to the (typical) 36V power-stage

supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog

circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is

accommodated by built-in bootstrap circuitry requiring only an external capacitor for each half-bridge.

To provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and

output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate

gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an

additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12 V source,

it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit

board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended

high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their

associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors

must be avoided. (See reference board documentation for additional information.)

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin

(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is

charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the

bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output

potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM

switching frequencies in the range from 300kHz to 4000kHz, it is recommended to use 33nF ceramic capacitors,

size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even

during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the

remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB

placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For

optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is

decoupled with a 2mF ceramic capacitor placed as close as possible to each supply pin. It is recommended to

follow the PCB layout of the TAS5614A reference design. For additional information on recommended power

supply and required components, see the application diagrams in this data sheet.

The 12V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 36V

power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not

critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5614A is fully protected against

erroneous power-stage turn on due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are

non-critical within the specified range (see the Recommended Operating Conditions table of this data sheet).

SYSTEM POWER-UP/POWER-DOWN SEQUENCE

Powering Up

The TAS5614A does not require a power-up sequence. The outputs of the H-bridges remain in a

high-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage

protection (UVP) voltage threshold (see the Electrical Characteristics table of this data sheet). Although not

specifically required, it is recommended to hold RESET in a low state while powering up the device. This allows

an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge

output.

Powering Down

The TAS5614A does not require a power-down sequence. The device remains fully operational as long as the

gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage

threshold (see the Electrical Characteristics table of this data sheet). Although not specifically required, it is a

good practice to hold RESET low during power down, thus preventing audible artifacts including pops or clicks.

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ERROR REPORTING

The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode

signaling to a PWM controller or other system-control device.

Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 goes low

when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature

exceeds 100°C (see the following table).

OTW2,

OTW

SD

0

OTW1

DESCRIPTION

0

Overtemperature (OTE) or overload (OLP) or undervoltage (UVP)

Overload (OLP) or undervoltage (UVP). Junction temperature higher than 100°C (overtemperature

warning)

0

1

0

1

0

1

0

1

Overload (OLP) or undervoltage (UVP)

Junction temperature higher than 125°C (overtemperature warning)

Junction temperature higher than 100°C (overtemperature warning)

Junction temperature lower than 100°C and no OLP or UVP faults (normal operation)

Note that asserting RESET low forces the SD signal high, independent of faults being present. TI recommends

monitoring the OTW signal using the system micro controller and responding to an overtemperature warning

signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown

(OTE).

To reduce external component count, an internal pullup resistor to 3.3V is provided on both SD and OTW

outputs. Level compliance for 5V logic can be obtained by adding external pullup resistors to 5V (see the

Electrical Characteristics table of this data sheet for further specifications).

DEVICE PROTECTION SYSTEM

The TAS5614A contains advanced protection circuitry carefully designed to facilitate system integration and ease

of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as

short circuits, overload, overtemperature, and undervoltage. The TAS5614A responds to a fault by immediately

setting the power stage in a high-impedance (Hi-Z) state and asserting the SD pin low. In situations other than

overload and overtemperature error (OTE), the device automatically recovers when the fault condition has been

removed, i.e., the supply voltage has increased.

The device will function on errors, as shown in the following table.

BTL Mode

PBTL Mode

SE Mode

Local Error In

Turns Off

Local Error In

Turns Off

A

B

C

D

A+B

A

B

C

D

A+B+C+D

A

B

C

D

A+B

C+D

Bootstrap UVP does not shutdown according to the table, it shuts down the respective halfbridge.

PIN-TO-PIN SHORT CIRCUIT PROTECTION (PPSC)

The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is

shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an over current after the

demodulation filter where PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at

startup i.e. when VDD is supplied, consequently a short to either GND_X or PVDD_X after system startup will not

activate the PPSC detection system. When PPSC detection is activated by a short on the output, all half bridges

are kept in a Hi-Z state until the short is removed, the device then continues the startup sequence and starts

switching. The detection is controlled globally by a two step sequence. The first step ensures that there are no

shorts from OUT_X to GND_X, the second step tests that there are no shorts from OUT_X to PVDD_X. The total

duration of this process is roughly proportional to the capacitance of the output LC filter. The typical duration is

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<15 ms/mF. While the PPSC detection is in progress, SD is kept low, and the device will not react to changes

applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is released. A device

reset will not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output configurations, the

detection is not performed in SE mode. To make sure not to trip the PPSC detection system it is recommended

not to insert resistive load to GND_X or PVDD_X.

OVERTEMPERATURE PROTECTION

The two different package options has individual over temperature protection schemes.

PHD Package

The TAS5614A PHD package option has a three-level temperature-protection system that asserts an active-low

warning signal (OTW1) when the device junction temperature exceeds 100°C (typical), (OTW2) when the device

junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the

device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z)

state and SD being asserted low. OTE is latched in this case. To clear the OTE latch, RESET must be asserted.

Thereafter, the device resumes normal operation.

DKD Package

The TAS5614A DKD package option has a two-level temperature-protection system that asserts an active-low

warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction

temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs

being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case. To clear the

OTE latch, RESET must be asserted. Thereafter, the device resumes normal operation.

UNDERVOLTAGE PROTECTION (UVP) AND POWER-ON RESET (POR)

The UVP and POR circuits of the TAS5614A fully protect the device in any power-up/down and brownout

situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are

fully operational when the GVDD_X and VDD supply voltages reach stated in the Electrical Characteristics table.

Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on

any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z)

state and SD being asserted low. The device automatically resumes operation when all supply voltages have

increased above the UVP threshold.

DEVICE RESET

When RESET is asserted low, all power-stage FETs in the four half-bridges are forced into a high-impedance

(Hi-Z) state.

In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset input low enables

weak pulldown of the half-bridge outputs. In the SE mode, the output is forced into a high impedance state when

asserting the reset input low. Asserting reset input low removes any fault information to be signaled on the SD

output, i.e., SD is forced high. A rising-edge transition on reset input allows the device to resume operation after

an overload fault. To ensure thermal reliability, the rising edge of reset must occur no sooner than 4 ms after the

falling edge of SD.

SYSTEM DESIGN CONSIDERATION

A rising-edge transition on reset input allows the device to execute the startup sequence and starts switching.

Apply only audio when the state of READY is high that will start and stop the amplifier without having audible

artifacts that is heard in the output transducers. If an overcurrent protection event is introduced the READY signal

goes low, hence, filtering is needed if the signal is intended for audio muting in non micro controller systems.

The CLIP signal is indicating that the output is approaching clipping. The signal can be used to either an audio

volume decrease or intelligent power supply controlling a low and a high rail.

The device is inverting the audio signal from input to output.

The VREG pin is not recommended to be used as a voltage source for external circuitry.

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PRINTED CIRCUIT BOARD RECOMMENDATION

Use an unbroken ground plane to have good low impedance and inductance return path to the power supply for

power and audio signals. PCB layout, audio performance and EMI are linked closely together. The circuit

contains high fast switching currents; therefore, care must be taken to prevent damaging voltage spikes. Routing

the audio input should be kept short and together with the accompanied audio source ground. A local ground

area underneath the device is important to keep solid to minimize ground bounce.

Netlist for this printed circuit board is generated from the schematic in Figure 12.

Note T1: PVDD decoupling bulk capacitors C60-C64 should be as close as possible to the PVDD and GND_X pins,

the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and

without going through vias. No vias or traces should be blocking the current path.

Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and

close to the pins.

Note T3: Heat sink needs to have a good connection to PCB ground.

Note T4: Output filter capacitors must be linear in the applied voltage range preferable metal film types.

Figure 15. Printed Circuit Board - Top Layer

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Note B1: It is important to have a direct low impedance return path for high current back to the power supply. Keep

impedance low from top to bottom side of PCB through a lot of ground vias.

Note B2: Bootstrap low impedance X7R ceramic capacitors placed on bottom side providing a short low inductance

current loop.

Note B3: Return currents from bulk capacitors and output filter capacitors.

Figure 16. Printed Circuit Board - Bottom Layer

SPACER

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型号：	TAS5614PHDR
厂家：	TEXAS INSTRUMENTS
描述：	150W STEREO / 300W MONO PurePath™ HD DIGITAL-INPUT POWER STAGE 150W立体声/单声道300W的PurePath ™HD数字输入功率级输入元件
文件：	总26页 (文件大小：1312K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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