TAS6421-Q1 [TI]
具有负载突降保护功能的汽车类 75W、2MHz、单通道、4.5V 至 26.4V 数字输入 D 类音频放大器;
| 型号： | TAS6421-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有负载突降保护功能的汽车类 75W、2MHz、单通道、4.5V 至 26.4V 数字输入 D 类音频放大器 放大器 音频放大器 |
| 文件： | 总63页 (文件大小：2920K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TAS6421-Q1
ZHCSJM6A –APRIL 2019–REVISED OCTOBER 2019
具有负载突降保护和 I2C 诊断功能的 TAS6421-Q1 75W、2MHz 数字输入
单通道汽车用 D 类 Burr-Brown™ 音频放大器
1 特性
2 应用
1
•
高级负载诊断功能
•
•
•
汽车音响主机和外部放大器
紧急呼叫 (eCall)
–
–
直流诊断功能，无需输入时钟即可执行
虚拟引擎声浪系统 (VESS)
交流诊断功能，可通过阻抗和相位响应实现高频
扬声器检测
3 说明
•
•
可轻松满足 CISPR25-L5 EMC 规范
符合面向汽车 应用的 AEC-Q100 标准
TAS6421-Q1 器件是一款单通道数字输入 D 类 Burr-
Brown™音频放大器，采用了 2.1MHz PWM 开关频
率，能以非常小的 PCB 尺寸实现成本优化的解决方
案，可针对启停事件在低至 4.5V 的电压下全面运行，
并可在高达 40kHz 的音频带宽下提供出色的音质。
TAS6421-Q1 的尺寸和引脚与 TAS642x-Q1 系列器件
兼容，实现了灵活性，只需进行极少的重新设计即可轻
松支持多种系统配置。
–
温度等级：-40°C 至 +125°C
•
音频输入
–
–
–
I2S 或 4/8 通道 TDM 输入
输入采样率：44.1kHz、48kHz、96kHz
输入格式：16 位至 32 位 I2S 和 TDM
•
音频输出
–
–
–
单通道桥接式负载 (BTL)
最高可达 2.1MHz 的输出开关频率
输出开关频率既可以设置为高于调幅 (AM) 频带，以消
除 AM 频带干扰并降低输出滤波需求及成本；也可以
设置为低于 AM 频带，以优化器件效率。该器件具有
内置负载诊断功能，用于检测和诊断误接的输出，以及
检测交流耦合的高频扬声器。
在 4Ω 负载、14.4V BTL 条件下，输出功率为
27W，THD 为 10%
–
在 2Ω 负载、14.4V BTL 条件下，输出功率为
45W，THD 为 10%
•
•
•
在 4Ω 负载、14.4V BTL 条件下的音频性能
器件信息(1)
–
–
–
输出功率为 1W 时，THD+N < 0.02%
42µVRMS 输出噪声
器件型号
封装
封装尺寸（标称值）
TAS6421-Q1
HSSOP (56)
18.41mm × 7.49mm
–90dB 串扰
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
负载诊断，独立于主机运行
–
–
–
开路和短路输出负载
输出至电池短路或接地短路
线路输出检测高达 6kΩ
功能方框图
VDD
VCOM VREG
VBAT
GVDD
PVDD
保护
MUTE
STANDBY
WARN
Gate Drive
Regulator
Reference
Regulators
Digital Core
–
–
–
–
–
输出电流限制和短路保护
Closed Loop Class D Amplifier
FAULT
40V 负载突降
Digital to PWM
MCLK
SCLK
可承受接地开路和电源开路
过热警告和关断
Volume
Serial
Audio
Port
OUT_P
OUT_M
Control -100
to +24 dB,
0.5 dB steps
Gate
Driver
Powerstage
FSYNC
SDIN1
Clip
Detection
欠压和过压，直流偏移
PLL and Clock
Management
•
常规运行
Protection
DC Load Diagnostics
Short to GND
Short to Power
Open Load
Overcurrent Limit
Overcurrent
SCL
SDA
–
–
–
4.5V 至 26.4V 电源电压
2
I
I2C 控制，具有 4 个地址选项
C Control
Overtemperature
I2C_ADDR0
I2C_ADDR1
Overvoltage and Undervoltage
DC Detection
Shorted Load
AC Load Diagnostics
削波检测（自锁或非自锁）
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLOSE32
TAS6421-Q1
ZHCSJM6A –APRIL 2019–REVISED OCTOBER 2019
www.ti.com.cn
目录
10.3 Feature Description............................................... 19
10.4 Device Functional Modes...................................... 29
10.5 Programming......................................................... 30
10.6 Register Maps....................................................... 33
11 Application and Implementation........................ 47
11.1 Application Information.......................................... 47
11.2 Typical Applications .............................................. 48
12 Power Supply Recommendations ..................... 51
13 Layout................................................................... 51
13.1 Layout Guidelines ................................................. 51
13.2 Layout Example .................................................... 52
13.3 Thermal Considerations........................................ 52
14 器件和文档支持 ..................................................... 54
14.1 文档支持................................................................ 54
14.2 接收文档更新通知 ................................................. 54
14.3 社区资源................................................................ 54
14.4 商标....................................................................... 54
14.5 静电放电警告......................................................... 54
14.6 Glossary................................................................ 54
1
2
3
4
5
6
7
8
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明（续）............................................................... 3
Device Options....................................................... 4
Pin Configuration and Functions......................... 5
Specifications......................................................... 7
8.1 Absolute Maximum Ratings ...................................... 7
8.2 ESD Ratings.............................................................. 7
8.3 Recommended Operating Conditions....................... 8
8.4 Thermal Information.................................................. 8
8.5 Electrical Characteristics........................................... 9
8.6 Typical Characteristics............................................ 13
Parameter Measurement Information ................ 17
9
10 Detailed description............................................ 18
10.1 Overview ............................................................... 18
10.2 Functional Block Diagram ..................................... 18
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (April 2019) to Revision A
Page
•
将器件状态从预告信息 更改为生产 数据................................................................................................................................. 1
2
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TAS6421-Q1
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ZHCSJM6A –APRIL 2019–REVISED OCTOBER 2019
5 说明（续）
在 14.4V 电源电压条件下，当负载为 4Ω、THD+N 为 10% 时，TAS6421-Q1 可提供单通道的 27W 输出功率；当
负载为 2Ω、THD+N 为 10% 时，可提供 45W 的输出功率。在 25V 电源电压条件下，当负载为 4Ω、THD+N 为
10% 时，此器件可提供 75W 的输出功率。
有关兼容引脚的双通道和四通道器件，请参阅 TAS6422-Q1、TAS6424L-Q1、TAS6424M-Q1 和 TAS6424-Q1。
Copyright © 2019, Texas Instruments Incorporated
3
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ZHCSJM6A –APRIL 2019–REVISED OCTOBER 2019
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6 Device Options
Output Power per channel / 10% THD
Channel
Current
Limit (Typ)
Channel Power-Supply
Part Number
4 Ω / BTL
14.4 V
4 Ω / BTL
2 Ω / BTL
2 Ω / PBTL
Max Voltage
Count
Voltage Range
Max Voltage
14.4 V
TAS6424-Q1
TAS6424M-Q1
TAS6424L-Q1
TAS6422-Q1
TAS6421-Q1
4
4
4
2
1
4.5 V to 26.4 V
4.5 V to 18 V
4.5 V to 18 V
4.5 V to 26.4 V
4.5 V to 26.4 V
6.5 A
6.5 A
4.8 A
6.5 A
6.5 A
27 W
27 W
27 W
27 W
27 W
75 W at 25 V
45 W at 18 V
45 W at 18 V
75 W at 25 V
75 W at 25 V
45 W
45 W
27 W
45 W
45 W
150 W at 25 V
80 W at 18 V
80 W at 18 V
150 W at 25 V
N/A
4
Copyright © 2019, Texas Instruments Incorporated
TAS6421-Q1
www.ti.com.cn
ZHCSJM6A –APRIL 2019–REVISED OCTOBER 2019
7 Pin Configuration and Functions
DKQ Package
56-Pin HSSOP With Exposed Thermal Pad
Top View
GND
PVDD
VBAT
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PVDD
PVDD
NC
2
3
AREF
4
NC
VREG
VCOM
AVSS
5
NC
6
NC
7
NC
AVDD
GVDD
NC
8
NC
9
BST_P
OUT_P
GND
OUT_M
BST_M
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GND
MCLK
SCLK
FSYNC
SDIN1
GND
Thermal
Pad
NC
NC
GND
NC
GND
NC
VDD
NC
SCL
NC
SDA
NC
I2C_ADDR0
I2C_ADDR1
STANDBY
MUTE
FAULT
WARN
GND
NC
NC
NC
NC
NC
NC
NC
Not to scale
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TAS6421-Q1
ZHCSJM6A –APRIL 2019–REVISED OCTOBER 2019
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Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
AREF
NO.
4
PWR
PWR
PWR
PWR
PWR
DO
VREG and VCOM bypass capacitor return
AVDD
AVSS
8
Voltage regulator bypass. Connect 1 µF capacitor from AVDD to AVSS
AVDD bypass capacitor return
7
BST_M
BST_P
FAULT
FSYNC
44
48
26
14
Bootstrap capacitor connection pin for high-side gate driver
Bootstrap capacitor connection pin for high-side gate driver
Reports a fault (active low, open drain), 100 kΩ internal pull-up resistor
Audio frame clock input
DI
1, 11, 16, 17,
18, 28, 46
GND
GND
PWR
Ground
GVDD
9
Gate drive voltage regulator derived from VBAT input pin. Connect 2.2 µF capacitor to GND
I2C address pins. Refer to 表 7
I2C_ADDR0
I2C_ADDR1
MCLK
22
23
12
DI
DI
DI
Audio master clock input
Mutes the device outputs (active low) while keeping output FETs switching at 50%, 100 kΩ
internal pull-down resistor
MUTE
NC
25
10, 29-43,
49-54
NC
Not connected or pulled to ground
OUT_M
OUT_P
45
47
NO
PO
Negative output for the channel
Positive output for the channel
PVDD voltage input (can be connected to battery). Bulk capacitor and bypass capacitor
required
PVDD
2, 55, 56
PWR
SCL
20
13
21
15
24
3
DI
DI
I2C clock input
SCLK
SDA
Audio bit and serial clock input
I2C data input and output
TDM data input and audio I2S data input
DI/DO
DI
SDIN1
STANDBY
VBAT
VCOM
VDD
DI
Enables low power standby state (active Low), 100 kΩ internal pull-down resistor
PWR
PWR
PWR
PWR
DO
Battery voltage input
6
Bias voltage
19
5
3.3 V external supply voltage
VREG
WARN
Voltage regulator bypass
27
Clip and overtemperature warning (active low, open drain), 100 kΩ internal pull-up resistor
Provides both electrical and thermal connection for the device. Heatsink must be connected to
GND.
Thermal Pad
—
GND
(1) GND = ground, PWR = power, PO = positive output, NO = negative output, DI = digital input, DO = digital output, DI/DO = digital input
and output, NC = no connection
6
Copyright © 2019, Texas Instruments Incorporated
TAS6421-Q1
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ZHCSJM6A –APRIL 2019–REVISED OCTOBER 2019
8 Specifications
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
-1
MAX
30
UNIT
PVDD, VBAT
VMAX
DC supply voltage relative to GND
Transient supply voltage: PVDD, VBAT
Supply-voltage ramp rate: PVDD, VBAT
DC supply voltage relative to GND
V
V
t ≤ 400 ms exposure
40
VRAMP
75
V/ms
V
VDD
-0.3
3.5
8
IMAX
Maximum current per pin (PVDD, VBAT, OUT_P, OUT_M, GND)
Pulsed supply current per PVDD pin (one shot) t < 100 ms
A
IMAX_PULSED
12
A
Input voltage for logic pins (SCL, SDA, SDIN1, FSYNC, MCLK, BCLK, SCLK,
MUTE, STANDBY, I2C_ADDRx)
VLOGIC
-0.3
VDD + 0.5
V
VGND
TJ
Maximum voltage between GND pins
Maximum operating junction temperature
Storage temperature
-0.3
-55
-55
0.3
150
150
V
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
VALUE
UNIT
V
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±3000
V(ESD)
Electrostatic discharge
All pins
±500
±750
Charged-device model (CDM), per AEC Q100–011
CDM ESD Classification Level C4B
Corner pins (1, 28, 29 and 56)
V
(1) (1) AEC Q100–002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS–001 specification.
Copyright © 2019, Texas Instruments Incorporated
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8.3 Recommended Operating Conditions
MIN
4.5
TYP
MAX
26.4
18
UNIT
PVDD
VBAT
VDD
TA
Output FET Supply Voltage Range
Battery Supply Voltage Input
DC Logic supply
Relative to GND
Relative to GND
Relative to GND
4.5
14.4
3.3
V
3.0
3.5
Ambient temperature
–40
125
°C
An adequate thermal design is
required
TJ
Junction temperature
–40
150
10
RL
Minimum speaker load impedance
BTL Mode
2
1
4
4.7
1
Ω
I2C pullup resistance on SDA and SCL pins
External capacitance on bypass pins
External capacitance on GVDD pin
External capacitance to GND on OUT pins
RPU_I2C
CBypass
CGVDD
COUT
kΩ
µF
µF
µF
Pin 2, 3, 5, 6, 8, 19
Pin 9
2.2
1
Limit set by DC-diagnostic timing
3.3
Minimum inductance at ISD current
levels
LO
Output filter inductance at 2.1MHz
1
µH
8.4 Thermal Information
TAS6421-Q1(2)
THERMAL METRIC(1)
DKQ (HSSOP)
56 PINS
42.8
0.9
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
RθJC(top)
RθJB
Junction-to-board thermal resistance
21.2
0.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
20.2
-
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) JEDEC Standard 4 Layer PCB.
8
Copyright © 2019, Texas Instruments Incorporated
TAS6421-Q1
www.ti.com.cn
ZHCSJM6A –APRIL 2019–REVISED OCTOBER 2019
8.5 Electrical Characteristics
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, fIN = 1
kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings
PARAMETER
OPERATING CURRENT
TEST CONDITIONS
MIN
TYP
MAX UNIT
IPVDD_IDLE
IVBAT_IDLE
IPVDD_STBY
IVBAT_STBY
IVDD
PVDD idle current
Channel playing, no audio input
Channel playing, no audio input
STANDBY Active, VDD = 0 V
STANDBY Active, VDD = 0 V
Channel playing, –60-dB signal
17
28
0.5
4
23
32
1
mA
mA
µA
VBAT idle current
PVDD standby current
VBAT standby current
VDD supply current
6
µA
15
18
mA
OUTPUT POWER
4 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C
20
25
38
42
22
27
40
45
4 Ω, PVDD = 14.4 V, THD+N = 10%, TC =
75°C
2 Ω, PVDD = 14.4 V, THD+N = 1%, TC = 75°C
PO_BTL
Output power per channel, BTL
W
2 Ω, PVDD = 14.4 V, THD+N = 10%, TC =
75°C
4 Ω, PVDD = 25 V, THD+N = 1%, TC = 75°C
4 Ω, PVDD = 25 V, THD+N = 10%, TC = 75°C
50
70
55
75
1 channel operating at 25-W output power, 4 Ω
load, PVDD = 14.4 V, TC = 25°C, including
inductor losses
EFFP
Power efficiency
86%
AUDIO PERFORMANCE
Zero input, A-weighting, gain level 1, PVDD =
14.4 V
42
55
67
85
Zero input, A-weighting, gain level 2, PVDD =
14.4 V
Vn
Output noise voltage
µV
Zero input, A-weighting, gain level 3, PVDD =
18 V
Zero input, A-weighting, gain level 4, PVDD =
25 V
gain level 1, Register 0x01, bit 1-0 = 00
gain level 2, Register 0x01, bit 1-0 = 01
gain level 3, Register 0x01, bit 1-0 = 10
gain level 4, Register 0x01, bit 1-0 = 11
PVDD = 14.4 Vdc + 1 VRMS, f = 1 kHz
7.5
15
GAIN
Peak Output Voltage/dBFS
V/FS
dB
21
29
PSRR
Power-supply rejection ratio
75
THD+N
Total harmonic distortion + noise
0.02%
LINE OUTPUT PERFORMANCE
Zero input, A-weighting, channel set to LINE
MODE
Vn_LINEOUT
VO_LINEOUT
THD+N
LINE output noise voltage
42
5.5
µV
LINE output voltage
0dB input, channel set to LINE MODE
VRMS
Line output total harmonic distortion +
noise
VO = 2 VRMS, channel set to LINE MODE
0.01%
DIGITAL INPUT PINS
VIH
VIL
IIH
Input logic level high
70
%VDD
Input logic level low
30 %VDD
Input logic current, high
Input logic current, low
VI = VDD
VI = 0
15
µA
µA
IIL
-15
PWM OUTPUT STAGE
Not including bond wire and package
resistance
RDS(on)
FET drain-to-source resistance
90
mΩ
OVERVOLTAGE (OV) PROTECTION
VPVDD_OV
PVDD overvoltage shutdown
27.0
27.8
28.8
V
Copyright © 2019, Texas Instruments Incorporated
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Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, fIN = 1
kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PVDD overvoltage shutdown
hysteresis
VPVDD_OV_HYS
VVBAT_OV
0.8
V
VBAT overvoltage shutdown
20
21.5
0.6
23
V
V
VVBAT_OV_HYS VBAT overvoltage shutdown hysteresis
UNDERVOLTAGE (UV) PROTECTION
VBATUV
VBAT undervoltage shutdown
4
0.2
4
4.5
4.5
V
V
V
V
VBAT undervoltage shutdown
hysteresis
VBATUV_HYS
PVDDUV
PVDD undervoltage shutdown
PVDD undervoltage shutdown
hysteresis
PVDDUV_HYS
0.2
BYPASS VOLTAGES
VGVDD
VAVDD
VVCOM
VVREG
Gate drive bypass pin voltage
7
6
V
V
V
V
Analog bypass pin voltage
Common bypass pin voltage
Regulator bypass pin voltage
2.5
5.5
POWER-ON RESET (POR)
VPOR
VDD voltage for POR
VDD POR recovery hysteresis voltage
2.1
0.5
2.7
V
V
VPOR_HYS
OVERTEMPERATURE (OT) PROTECTION
OTW(i)
Channel overtemperature warning
Channel overtemperature shutdown
150
175
°C
°C
OTSD(i)
Global junction overtemperature
warning
OTW
130
°C
Global junction overtemperature
shutdown
OTSD
OTHYS
160
15
°C
°C
Overtemperature hysteresis
LOAD OVERCURRENT PROTECTION
OC Level 1
OC Level 2
4.0
6.0
4.8
6.5
A
A
ILIM Overcurrent cycle-by-cycle limit
OC Level 1, Any short to supply, ground, or
other channels
7
9
A
A
ISD
Overcurrent shutdown
OC Level 2, Any short to supply, ground, or
other channels
MUTE MODE
GMUTE
Output attenuation
100
7
dB
CLICK AND POP
ITU-R 2k filter, High-Z/MUTE to Play, Play to
Mute/High-Z
VCP
Output click and pop voltage
mV
DC OFFSET
VOFFSET
Output offset voltage
2
2
5
mV
V
DC DETECT
DCFAULT
Output DC fault protection
2.5
DIGITAL OUTPUT PINS
VOH
VOL
Output voltage for logic level high
I = ±2 mA
I = ±2 mA
90
%VDD
Output voltage for logic level low
10 %VDD
Signal delay when output clipping
detected
tDELAY_CLIPDET
20 µs
10
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Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, fIN = 1
kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings
PARAMETER
LOAD DIAGNOSTICS
TEST CONDITIONS
MIN
TYP
MAX UNIT
Resistance to detect a short from OUT
pin(s) to PVDD
S2P
S2G
500
Ω
Ω
Resistance to detect a short from OUT
pin(s) to ground
200
SL
Shorted load detection tolerance
Open load
±0.5
Ω
Ω
OL
40
70
TDC_DIAG
LO
TLINE_DIAG
ACIMP
DC diagnostic time
100
ms
kΩ
ms
Line output diagnostic detection
Line output diagnostic time
AC impedance accuracy
AC impedance accuracy
AC diagnostic time
6
Not including the preceeding DC_DIAG time
Gain linearity, ƒ = 19 kHz, RL = 2 Ω to 16 Ω
Offset
40
25%
±0.5
ACIMP
Ω
TAC_DIAG
I2C_ADDR PINS
170
300
ms
Time delay needed for I2C address
set-up
tI2C_ADDR
µs
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Electrical Characteristics (continued)
Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, fIN = 1
kHz, fSW = 2.11 MHz, AES17 Filter, default I2C settings
PARAMETER
I2C CONTROL PORT
TEST CONDITIONS
MIN
TYP
MAX UNIT
Bus free time between a STOP and
START condition
tBUS
1.3
µs
th1
th2
Hold time, SCL to SDA
0
ns
µs
Hold time, start condition to SCL
0.6
I2C startup time after VDD power on
reset
tSTART
12
ms
tRISE
tFALL
tSU1
tSU2
tSU3
tW(H)
tW(L)
Rise time, SCL and SDA
300
300
ns
ns
ns
µs
µs
µs
µs
Fall time, SCL and SDA
Setup, SDA to SCL
100
0.6
0.6
0.6
1.3
Setup, SCL to start condition
Setup, SCL to stop condition
Required pulse duration SCL High
Required pulse duration SCL Low
SERIAL AUDIO PORT
DMCLK, DSCLK
fMCLK
fMCLK_Max
tSCY
Allowable input clock duty cycle
45%
128
50%
55%
Supported MCLK frequencies
Maximum frequency
128, 256, or 512
512 xFS
25 MHz
SCLK pulse cycle time
SCLK pulse-with LOW
SCLK pulse-with HIGH
Rise and fall time
40
16
16
ns
ns
ns
ns
ns
ns
ns
ns
tSCL
tSCH
tRISE/FALL
tSF
<5
SCLK rising edge to FSYNC edge
FSYNC rising edge to SCLK edge
DATA set-up time
8
8
8
8
tFS
tDS
tDH
DATA hold time
Input capacitance, pins MCLK, SCLK,
FSYNC, SDIN1
ci
10
pf
FSYNC = 44.1 kHz or 48 kHz
FSYNC = 96 kHz
30
12
Latency from input to output measured
in FSYNC sample count
TLA
12
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8.6 Typical Characteristics
TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see 图 66 (unless otherwise noted)
0
-20
0
-20
PVDD = 14.4 V
PVDD = 24 V
PVDD = 14.4 V
PVDD = 24 V
-40
-40
-60
-60
-80
-80
-100
-120
-100
20
100
1k
Frequency
10k 20k
20
100
1k
Frequency
10k 20k
PO = 1 W
PO = 1 W
图 1. PVDD PSRR vs Frequency
图 2. VBAT PSRR vs Frequency
10
1
10
1
2 W Load
4 W Load
2 W Load
4 W Load
0.1
0.1
0.01
0.01
0.001
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
PO = 1 W
fSW = 384 kHz
PO = 1 W
fSW = 2.1 MHz
图 3. THD+N vs Frequency
图 4. THD+N vs Frequency
10
1
10
1
2 W Load
4 W Load
2 W Load
4 W Load
0.1
0.1
0.01
0.01
0.001
0.001
20
100
1k
Frequency (Hz)
10k 20k
20
100
1k
Frequency (Hz)
10k 20k
PO = 1 W
24 V
fSW = 384 kHz
PO = 1 W
24 V
fSW = 2.1 MHz
图 5. THD+N vs Frequency
图 6. THD+N vs Frequency
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Typical Characteristics (接下页)
TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see 图 66 (unless otherwise noted)
10
10
2 W Load
4 W Load
2 W Load
4 W Load
1
1
0.1
0.1
0.01
0.01
0.001
0.001
10m
100m
1
Output Power (W)
10
100
10m
100m
1
Output Power (W)
10
100
fSW = 384 kHz
fSW = 2.1 MHz
图 7. THD+N vs Power
图 8. THD+N vs Power
10
1
10
1
4 W Load
4 W Load
0.1
0.1
0.01
0.01
0.001
0.001
10m
100m
1
Output Power (W)
10
100
10m
100m
1
Output Power (W)
10
100
24 V
fSW = 384 kHz
24 V
fSW = 2.1 MHz
图 9. THD+N vs Power
图 10. THD+N vs Power
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
2 W Load
4 W Load
2 W Load
4 W Load
5
7
9
11 13 15 17 19 21 23 25 26
Supply Voltage (V)
5
7
9
11 13 15 17 19 21 23 25 26
Supply Voltage (V)
10% THD
fSW = 384 kHz
10% THD
fSW = 2.1 MHz
图 11. Output Power vs Supply Voltage
图 12. Output Power vs Supply Voltage
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Typical Characteristics (接下页)
TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see 图 66 (unless otherwise noted)
160
140
120
100
80
160
140
120
100
80
Gain Level 1
Gain Level 2
Gain Level 3
Gain Level 4
Gain Level 1
Gain Level 2
Gain Level 3
Gain Level 4
60
60
40
40
20
20
0
0
5
10
15
Supply Voltage (V)
20
25 26
5
10
15
Supply Voltage (V)
20
25
D014
A-weighted Noise
fSW = 384 kHz
A-weighted Noise
fSW = 2.1 MHz
图 13. Noise vs Supply voltage
图 14. Noise vs Supply voltage
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
PVDD = 14.4 V
PVDD = 24 V
PVDD = 14.4 V
PVDD = 24 V
0
10
20
30
Output Power (W)
40
50
60
70
80
0
10
20
30
Output Power (W)
40
50
60
70
80
4 Ω
fSW = 384 kHz
4 Ω
fSW = 2.1 MHz
图 15. PVDD Efficiency vs Output Power
图 16. PVDD Efficiency vs Total Output Power
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
PVDD = 14.4 V
40 50
PVDD = 14.4 V
40 50
0
10
20 30
Output Power (W)
0
10
20 30
Output Power (W)
2 Ω
fSW = 384 kHz
2 Ω
fSW = 2.1 MHz
图 17. PVDD Efficiency vs Total Output Power
图 18. PVDD Efficiency vs Total Output Power
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Typical Characteristics (接下页)
TA = 25 ºC, VVDD = 3.3 V, VBAT = PVDD = 14.4 V, RL = 4 Ω, fIN = 1 kHz, fs = 48 kHz, fSW = 2.1 MHz, AES17 filter, default I2C
settings, see 图 66 (unless otherwise noted)
20
18
16
14
12
10
8
30
25
20
15
10
5
6
4
FPWM = 384 kHz
FPWM = 2.1 MHz
FPWM = 384 kHz
FPWM = 2.1 MHz
2
0
0
5
7
9
11 13 15 17 19 21 23 25 26
Supply Voltage (V)
5
10
Supply Voltage (V)
15
18
D020
图 19. PVDD Idle Current vs Voltage
图 20. VBAT Idle Current vs Voltage
6
5
4
3
2
1
0
10
PVDD = 14.4 V 2 W Load
PVDD = 14.4 V 4 W Load
PVDD = 24 V 4 W Load
8
6
4
2
0
5
7
9
11
13 15 17 19 21 23 25 26
Supply Voltage (V)
0
10
20
30
40
Total Output Power (W)
50
60
70
80
fSW = 384 kHz
图 21. PVDD + VBAT Standby Current vs Voltage
图 22. Power Dissipation vs Output Power
12
10
8
6
4
PVDD = 14.4 V 2 W Load
PVDD = 14.4 V 4 W Load
PVDD = 24 V 4 W Load
2
0
0
10
20
30
40
50
Total Output Power (W)
60
70
80
fSW = 2.1 MHz
图 23. Power Dissipation vs Output Power
16
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9 Parameter Measurement Information
The parameters for the TAS6421-Q1 device were measured using the circuit in 图 66.
For measurements with 2.1 MHz switching frequency the 3.3 µH inductor from the TAS6421-Q1 EVM is used.
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10 Detailed description
10.1 Overview
The TAS6421-Q1 device is a single-channel digital-input Class-D audio amplifier specifically tailored for use in
the automotive industry. The device is designed for vehicle battery operation or boosted voltage systems. This
efficient Class-D technology allows for reduced power consumption, reduced PCB area and reduced heat. The
device realizes an audio sound-system design with smaller size and lower weight than traditional Class-AB
solutions.
The core design blocks are as follows:
•
•
•
•
•
•
•
•
•
•
Serial audio port
Clock management
High-pass filter and volume control
Pulse width modulator (PWM) with output stage feedback
Gate drive
Power FETs
Diagnostics
Protection
Power supply
I2C serial communication bus
10.2 Functional Block Diagram
VDD
VCOM VREG
VBAT
GVDD
PVDD
MUTE
Gate Drive
Regulator
Reference
Regulators
STANDBY
Digital Core
WARN
Closed Loop Class D Amplifier
FAULT
Digital to PWM
MCLK
Volume
Serial
SCLK
Audio
OUT_P
OUT_M
Gate
Driver
Control -100
to +24 dB,
0.5 dB steps
Powerstage
Port
FSYNC
SDIN1
Clip
Detection
PLL and Clock
Management
Protection
DC Load Diagnostics
Short to GND
Short to Power
Open Load
Overcurrent Limit
Overcurrent
SCL
SDA
2
I C Control
Overtemperature
I2C_ADDR0
I2C_ADDR1
Overvoltage and Undervoltage
DC Detection
Shorted Load
AC Load Diagnostics
18
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10.3 Feature Description
10.3.1 Serial Audio Port
The serial audio port (SAP) receives audio in either I2S, left justified, right justified, or TDM formats.
Settings for the serial audio port are programmed in the SAP Control (Serial Audio-Port Control) Register
(address = 0x03) [default = 0x04] and Miscellaneous Control 3 Register (address = 0x21) [default = 0x00].
图 24 shows the digital audio data connections for I2S and TDM8 mode for a five channel system using TAS6424
four-channel Class-D amplifier and a TAS6421-Q1 single-channel Class-D amplifier.
I2S
TDM8
SOC
MCLK
SOC
MCLK
TAS6424
MCLK
TAS6424
MCLK
SCLK
FSYNC
DATA1
DATA2
DATA3
SCLK
SCLK
FSYNC
DATA
SCLK
FSYNC
SDIN1
SDIN2
FSYNC
SDIN1
SDIN2
TAS6421
TAS6421
MCLK
SCLK
MCLK
SCLK
FSYNC
SDIN1
FSYNC
SDIN1
图 24. Digital-Audio Data Connection
10.3.1.1 I2S Mode
I2S timing uses the FSYNC pin to define when the data being transmitted is for the left channel and when the
data is for the right channel. The FSYNC pin is low for the left channel and high for the right channel. The bit
clock, SCLK, runs at 32 × fS or 64 × fS and is used to clock in the data. A delay of one bit clock occurs from the
time the FSYNC signal changes state to the first bit of data on the data lines. The data is presented in 2s-
complement form (MSB-first). The data is valid on the rising edge of the bit clock and is used to clock in the data.
The SAP Control Register Bits 3-5 allows to select if I2S Channel 1 or Channel 2 is amplified.
10.3.1.2 Left-Justified Timing
Left-justified (LJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left channel
and when the data is for the right channel. The FSYNC pin is high for the left channel and low for the right
channel. A bit clock running at 32 × fS or 64 × fS is used to clock in the data. The first bit of data appears on the
data lines at the same time FSYNC toggles. The data is written MSB-first and is valid on the rising edge of the bit
clock. Digital words can be 16-bits or 24-bits wide and pad any unused trailing data-bit positions in the left-right
(L/R) frame with zeros.
10.3.1.3 Right-Justified Timing
Right-justified (RJ) timing also uses the FSYNC pin to define when the data being transmitted is for the left
channel and when the data is for the right channel. The FSYNC pin is high for the left channel and low for the
right channel. A bit clock running at 32 × fS or 64 × fS is used to clock in the data. The first bit of data appears on
the data 8-bit clock periods (for 24-bit data) after the FSYNC pin toggles. In RJ mode the LSB of data is always
clocked by the last bit clock before the FSYNC pin transitions. The data is written MSB-first and is valid on the
rising edge of bit clock. The device pads the unused leading data-bit positions in the L/R frame with zeros.
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Feature Description (接下页)
10.3.1.4 TDM Mode
TDM mode supports 4 or 8 channels of audio data. The TDM mode is automatically selected when the TDM
clocks are present. The device can be configured through I2C to select which TDM channel slot is amplified. The
TDM mode supports 16-bit, 24-bit, and 32-bit input data lengths.
In TDM mode, SCLK must be 128 x fs or 256 x fs, depending on the TDM slot size. In TDM mode SCLK and
MCLK can be connected together. If SCLK and MCLK are connected together or the frequency of SCLK and
MCLK is equal, FSYNC should be minimum 2 MCLK pulses long.
In TDM mode, the SDIN1 pin (pin 15) is used for digital audio data. 表 1 lists register settings for the TDM
channel selection.
表 1. Channel Selection
REGISTER SETTING
AMPLIFIED CHANNEL
0x03
0x03
0x03
BIT 5
BIT 4
BIT 3
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Slot 1 in TDM8/4 or Left Channel in I2S mode
Slot 2 in TDM8/4 or Right Channel in I2S mode
Slot 3 in TDM8/4
Slot 4 in TDM8/4
Slot 5 in TDM8
Slot 6 in TDM8
Slot 7 in TDM8
Slot 8 in TDM8
10.3.1.5 Supported Clock Rates
The device supports MCLK rates of 128 × fS, 256 × fS, or 512 × fS.
The device supports SCLK rates of 32 × fS or 64 × fS in I2S, LJ or RJ modes or 128 × fS, or 256 × fS in TDM
mode.
The device supports FSYNC rates of 44.1 kHz, 48 kHz, or 96 kHz.
The maximum clock frequency is 25 MHz. Therefore, for a 96 kHz FSYNC rate, the maximum MCLK rate is
256 × fS.
Duty cycle of 50% is required for 128x FSYNC, for 256x and 512x 50% duty cycle is not required.
10.3.1.6 Audio-Clock Error Handling
When any kind of clock error, MCLK-FSYNC or SCLK-FSYNC ratio, or clock halt is detected, the device puts all
channels into the Hi-Z state. When all audio clocks are within the expected range, the device automatically
returns to the state it was in. See the Electrical Characteristics table for timing requirements.
20
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FSYNC
(Input)
0.5 × DVDD
0.5 × DVDD
t
t
t
FS
SCH
SCL
SCLK
(Input)
t
t
SF
SCY
DATA
(Input)
0.5 × DVDD
t
t
DH
DS
图 25. Serial Audio Timing
1/f
S
FSYNC
SCLK
L-channel
R-channel
Audio data word = 16 bit, SCLK = 64 f
S
S
0
1
14 15
0
1
14 15
LSB
SDIN
MSB
LSB
MSB
Audio data word = 24 bit, SCLK = 64 f
0
1
22 23
0
1
22 23
LSB
SDIN
MSB
LSB
MSB
Audio data word = 32 bit, SCLK = 64 f
S
0
1
30 31
0
1
30 31
LSB
SDIN
MSB
LSB
MSB
图 26. Left-Justified Audio Data Format
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1/f
S
FSYNC
L-channel
R-channel
SCLK
Audio data word = 16 bit, SCLK = 64 f
S
S
0
1
14 15
0
1
14 15
SDIN
MSB
LSB
MSB
LSB
Audio data word = 24 bit, SCLK = 64 f
0
1
22 23
0
1
22 23
SDIN
MSB
LSB
MSB
LSB
Audio data word = 32 bit, SCLK = 64 f
S
0
1
30 31
LSB
0
1
30 31
SDIN
MSB
MSB
LSB
图 27. I2S Audio Data Format
1/Fs (256 sbclks)
FSYNC
SCLK
SDIN (I2S mode)
23
22
1
0
23
22
1
0
23
22
1
0
23
22
32 SCLK
32 SCLK
8 blocks of 32 SCLK
Audio Data Format: TDM8 mode
图 28. TDM8 Audio Data Format
10.3.2 DC Blocking
Direct-current (DC) content in the audio signal can damage speakers. The data path has a high-pass filter to
remove any DC from the input signal. The corner frequency is selectable from 4 Hz, 8 Hz,15 Hz, 30 Hz and
several more options up to 463 Hz with bits 0 through 2 in register 0x26. The default value of –3 dB is
approximately 4 Hz for 44.1 kHz or 48 kHz and approximately 8 Hz for 96 kHz sampling rates.
22
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10.3.3 Volume Control and Gain
The output channel has a digital-volume control with a range from –100 dB to +24 dB with 0.5-dB steps. The
volume control is set through I2C. The gain-ramp rate is programmable through I2C to take one step every 1, 2,
4, or 8 FSYNC cycles.
The peak output-voltage swing is also configurable in the gain control register through I2C. The four full-scale
voltage settings are 7.5 V, 15 V, 21 V, and 29 V. TI recommends selecting the lowest possible for the expected
PVDD operation to optimize output noise and dynamic range performance.
10.3.4 High-Frequency Pulse-Width Modulator (PWM)
The PWM converts the PCM input data into a switched signal of varying duty cycle. The PWM modulator is an
advanced design with high bandwidth, low noise, low distortion, and excellent stability. The output switching rate
is synchronous to the serial audio-clock input and is programmed through I2C to be between 8× and 48× the
input-sample rate. The option to switch at high frequency allows the use of smaller and lower cost external
filtering components. 表 2 lists the switch frequency options for bits 4 through 6 in the Miscellaneous Control 2
register (address 0x02).
表 2. Output Switch Frequency Option
INPUT SAMPLE RATE
BIT 6:4 SETTINGS
010 to 100
000
001
101
110
111
44.1 kHz
48 kHz
96 kHz
352.8 kHz
384 kHz
384 kHz
441 kHz
480 kHz
480 kHz
RESERVED
RESERVED
RESERVED
1.68 MHz
1.82 MHz
1.82 MHz
1.94 MHz
2.11 MHz
2.11 MHz
2.12 MHz
Not supported
Not supported
10.3.5 Gate Drive
The gate driver accepts the low-voltage PWM signal and level shifts it to drive a high-current, full-bridge, power-
FET stage. The device uses proprietary techniques to optimize EMI and audio performance.
The gate-driver power-supply voltage, GVDD, is internally generated and a decoupling capacitor is connected at
pin 9.
The full H-bridge output stages use only NMOS transistors. Therefore, bootstrap capacitors are required for the
proper operation of the high side NMOS transistors. A 1-µF ceramic capacitor of quality X7R or better, rated for
at least 16 V, must be connected from each output to the corresponding bootstrap input. The bootstrap
capacitors connected between the BST pins and corresponding output function as a floating power supply for the
high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap
capacitors hold the gate-to-source voltage high keeping the high-side MOSFETs turned on.
10.3.6 Power FETs
The BTL output channel comprises four N-channel 90-mΩ FETs for high efficiency and maximum power transfer
to the load. These FETs are designed to handle the fast switching frequency and large voltage transients during
load dump.
10.3.7 Load Diagnostics
The device incorporates both DC-load and AC-load diagnostics, which are used to determine the status of the
load. The DC diagnostics are turned on by default, but if a fast startup without diagnostics is required, the DC
diagnostics can be bypassed through I2C. The DC diagnostics run when the output channel is directed to leave
the Hi-Z state and enter the MUTE or PLAY state. The DC diagnostics can also be enabled manually. DC
Diagnostics can be started from any operating condition, but if the channel is in PLAY state, then the time to
complete the diagnostic is longer because the device must ramp down the audio signal of that channel before
transitioning to the Hi-Z state. The DC diagnostics are available as soon as the device supplies are within the
recommended operating range. The DC diagnostics do not rely on the audio input clocks to be available to
function. DC Diagnostic results are reported through I2C registers.
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10.3.7.1 DC Load Diagnostics
The DC load diagnostics are used to verify the load is connected. The DC diagnostics consists of four tests:
short-to-power (S2P), short-to-ground (S2G), open-load (OL), and shorted-load (SL). The S2P and S2G tests
trigger if the impedance to GND or a power rail is below that specified in the Specifications section. The
diagnostic detects a short to vehicle battery, even when the supply is boosted. The SL test has an I2C-
configurable threshold depending on the expected load to be connected. The OL test reports if the select
channel has a load impedance greater than the limits in the Specifications section.
Open Load
Open Load Detected
OL Maximum
Open Load (OL)
Detection Threshold
Normal or Open Load
May Be Detected
OL Minimum
SL Maximum
SL Minimum
Normal Load
Play Mode
Shorted Load (SL)
Detection Threshold
Normal or Shorted Load
May Be Detected
Shorted Load
Shorted Load Detected
图 29. DC Load Diagnostic Reporting Thresholds
10.3.7.2 Line Output Diagnostics
The device also includes an optional test to detect a line-output load. A line-output load is a high-impedance load
that is above the open-load (OL) threshold such that the DC-load diagnostics report an OL condition. After an OL
condition is detected, if the line output detection bit is also set, the channel checks if a line-output load is present
as well. This test is not pop free, so if an external amplifier is connected it should be muted.
10.3.7.3 AC Load Diagnostics
The AC load diagnostic is used to determine the proper connection of a capacitively-coupled speaker or tweeter
when used with a passive crossover. The AC load diagnostic is controlled through I2C. The AC diagnostics
requires an external input signal and reports the approximate load impedance and phase. The selected signal
frequency should create current flow through the desired speaker for proper detection. The AC load-diagnostic
test procedure is as follows.
10.3.7.3.1 Impedance Magnitude Measurement
For load-impedance detection, use the following test procedure:
1. Set the output channel into the Hi-Z state.
2. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0.
3. Apply a full-scale input signal from the DSP for the tested channel with the desired frequency (recommended
10 kHz to 20 kHz).
注
The device ramps the signal up and down automatically to prevent pops and clicks.
4. Set the device into the AC diagnostic mode (set bit 3 in register 0x15 to 1).
5. Read back the AC impedance (register 0x17).
When the test is complete, the channel reporting register indicates the status change from the AC diagnostic
mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.
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The hexadecimal register value must be converted to decimal and used to calculate the impedance magnitude
using 公式 1:
Impedance _ CHxì2.371mV
(Gain)(I mA)
Channelx Impedance =
(Ohms)
(1)
10.3.7.3.2 Impedance Phase Reference Measurement
The first stage to determine the AC phase is to utilize the built-in loopback mode to determine the reference
value for the phase measurement. This reference nullifies any phase offset in the device and measure only the
phase of the load.
For loopback delay detection, use the following test procedure:
1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 1 to enable AC loopback mode.
2. Apply a 0-dBFS 19 kHz signal and enable AC load diagnostics (set bit 3 in register 0x15 to 1).
3. Read back the 16bit hexadecimal, AC_LDG_PHASE1 value. Register 0x1B holds the MSB and register
0x1C holds the LSB.
4. Set bit 3 in register 0x15 to 0.
When the test is complete, the channel reporting register indicates the status change from the AC diagnostic
mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.
10.3.7.3.3 Impedance Phase Measurement
After performing the phase reference measurements, measure the phase of the speaker load. This is performed
in the same manner as the reference measurements, except the loopback is disabled in register 0x16, bit 7.
For loopback delay detection, use the following test procedure:
1. Set the AC_DIAGS_LOOPBACK bit (bit 7 in register 0x16) to 0 to disable AC loopback mode.
2. Apply a 0-dBFS 19 kHz signal and enable AC load diagnostics by setting bit 3 in register 0x15 to 1.
3. Read back the 16-bit hexadecimal, AC_LDG_PHASE1 value. Register 0x1B holds the MSB and register
0x1C holds the LSB.
4. Read back the hexadecimal stimulus value, STI. Register 0x1D holds the MSB and register 0x1E holds the
LSB.
5. Set bit 3 in register 0x15 to 0.
When the test is complete, the channel reporting register indicates the status change from the AC diagnostic
mode to the Hi-Z state. The detected impedance is stored in the appropriate I2C register.
The AC phase in degrees is calculated using 公式 2:
:
;
2D=OA_%*T .$- F 2D=OA_%*T(.&/)
2D=OA_%*T = 360(
)
56+_%*T(.&/)
(2)
Where:
•
•
•
Phase_CHx(LBK) is the reference phase measurement. LBK stands for loopback mode
Phase_CHx(LDM) is the phase measure of the load. LDM stands for load mode
STI_CHx(LDM) is the stimulus value
表 3. AC Impedance Code to Magnitude
MAPPING FROM CODE TO
MAGNITUDE (Ω/Code)
SETTING
GAIN AT 19 kHz
I(A)
MEASUREMENT RANGE (Ω)
Gain = 4, I = 10 mA
(recommended)
4.28
4.28
1
0.01
0.019
0.01
12
6
0.05832
Gain = 4, I = 19 mA
0.0307
Gain = 1, I = 10 mA
(recommended)
48
24
0.2496
Gain = 1, I = 19 mA
1
0.019
0.1314
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10.3.8 Protection and Monitoring
10.3.8.1 Overcurrent Limit (ILIMIT
)
The overcurrent limit terminates each PWM pulse to limit the output current flow when the current limit (ILIMIT) is
exceeded. Power is limited, but operation continues without disruption and prevents undesired shutdown for
transient music events. ILIMIT is not reported as fault condition to registers or the FAULT pin but as warning
condition to the WARN pin and ILIMIT Status Register (address = 0x25) [default = 0x00]. The two programmable
levels can be set by bit 4 in the Miscellaneous Control 1 register (address 0x01).
10.3.8.2 Overcurrent Shutdown (ISD
)
If the output load current reaches ISD, such as an output short to GND, then a peak current limit occurs, which
shuts down the channel. The time to shutdown the channel varies depending on the severity of the short
condition. The channel is placed into the Hi-Z state, the fault is reported to the register, and the FAULT pin is
asserted. The device remains in this state until the CLEAR FAULT bit is set in Miscellaneous Control 3 Register,
0x21 bit 7. After clearing this bit and if the diagnostics are enabled, the device automatically starts diagnostics on
the channel and, if no load failure is found, the device restarts. If a load fault is found the device continues to
rerun the diagnostics once per second. Because this hiccup mode uses the diagnostics, no high current is
created. If the diagnostics are disabled, the device sets the state for the channel to Hi-Z and requires the MCU to
take the appropriate action, setting the CLEAR FAULT bit after the fault was removed, in order to return to Play
state. The two programmable levels can be set by bit 4 in the Miscellaneous Control 1 register (address 0x01).
10.3.8.3 DC Detect
This circuit checks the DC offset continuously during normal operation at the output of the amplifier. If the DC
offset exceeds the threshold, the channel is placed in the Hi-Z state, the fault is reported to the I2C register, and
the FAULT pin is asserted. A register bit can be used to mask reporting to the FAULT pin if required.
10.3.8.4 Clip Detect
The Clip Detect is reported on the WARN pin if 100% duty-cycle PWM is reached for a minimum number of
PWM cycles set by the Clip Window Register (address = 0x23). The default is 20 PWM cycles. The Clip Detect is
latched and can be cleared by I2C. Masking the clip reporting to the pin is possible through I2C. If desired, the
Clip Detect can be configured to be non-latching through I2C. In non-latching mode, Clip Detect is reported when
the PWM duty cycle reaches 100%, and deasserted once the PWM duty cycle falls below 100%.
10.3.8.5 Global Overtemperature Warning (OTW), Overtemperature Shutdown (OTSD)
Four overtemperature warning levels are available in the device (see the Register Maps section for thresholds).
When the junction temperature exceeds the warning level, the WARN pin is asserted, unless the mask bit has
been set to disable reporting. The device functions until the OTSD value is reached, at which point the channels
are placed in the Hi-Z state and the FAULT pin is asserted. By default, the device remains shut down after the
temperature drops to normal levels. This configuration can be changed in bit 3 of the Miscellaneous Control 3
Register (address = 0x21) [default = 0x00] to auto-recovery: When the junction temperature returns to normal
levels, the device automatically recovers and places the channel into the state indicated by the state control
register. Note that even in auto-recovery configuration the FAULT pin remains asserted until the CLEAR FAULT
bit (bit 7) is set in register 0x21.
10.3.8.6 Channel Overtemperature Warning [OTW(i)] and Shutdown [OTSD(i)]
In addition to the global OTW, the output channel also has an individual overtemperature warning and shutdown.
If the channel exceeds the OTW(i) threshold, the warning register bit is set as the WARN pin is asserted, unless
the mask bit has been set to disable reporting. If the channel temperature exceeds the OTSD(i) threshold then
the channel goes to the Hi-Z state and either remains there or auto-recovers to the state indicated by the state
control register when the temperature drops below the OTW(i) threshold, depending on the setting of bit 3 of the
Miscellaneous Control 3 Register (address = 0x21) [default = 0x00].
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10.3.8.7 Undervoltage (UV) and Power-On-Reset (POR)
The undervoltage (UV) protection detects low voltages on the PVDD and VBAT pins. In the event of an UV
condition, the FAULT pin is asserted, and the I2C register is updated. A power-on reset (POR) on the VDD pin
causes the I2C to goes to the high-impedance (Hi-Z) state, and all registers are reset to default values. At power-
on or after a POR event, the POR warning bit and WARN pin are asserted.
10.3.8.8 Overvoltage (OV) and Load Dump
The overvoltage (OV) protection detects high voltages on the PVDD pin. If the PVDD pin reaches the OV
threshold, the FAULT pin is asserted and the I2C register is updated. The device can withstand 40 V load-dump
voltage spikes.
10.3.9 Power Supply
The device has three power supply inputs, VDD, PVDD, and VBAT, which are described as follows:
VDD
This pin is a 3.3V supply pin that provides power to the low voltage circuitry.
VBAT
This pin is a higher voltage supply that can be connected to the vehicle battery or the regulated
voltage rail in a boosted system within the recommended limits. For best performance, this rail
should be 10 V or higher. See the Recommended Operating Conditions table for the maximum
supply voltage. This supply rail is used for higher voltage analog circuits but not the output FETs.
PVDD
This pin is a high-voltage supply that can either be connected to the vehicle battery or to another
voltage rail in a boosted system. The PVDD pin supplies the power to the output FETs and can be
within the recommended operating limits, even if that is below the VBAT supply, to allow for
dynamic voltage systems.
Several on-chip regulators are included for generating the voltages necessary for the internal circuitry. The
external pins are provided only for bypass capacitors to filter the supply and should not be used to power other
circuits.
The device can withstand fortuitous open ground and power conditions within the absolute maximum ratings for
the device. Fortuitous open ground usually occurs when a speaker wire is shorted to ground, allowing for a
second ground path through the body diode in the output FETs.
10.3.9.1 Vehicle-Battery Power-Supply Sequence
The device can accept any sequence of the VBAT, PVDD and VDD supply.
10.3.9.1.1 Power-Up Sequence
In a typical system, the VBAT and PVDD supplies are both connected to the vehicle battery and power up at the
same time. The VDD supply should be applied after the VBAT and PVDD supplies are within the recommended
operating range.
10.3.9.1.2 Power-Down Sequence
To power-down the device, first set the STANDBY pin low for at least 15ms before removing PVDD, VBAT or
VDD. After 15ms, the power supplies can be removed.
10.3.9.2 Boosted Power-Supply Sequence
In this case, the VBAT and PVDD inputs are not connected to the same supply.
When powering up, apply the VBAT supply first, the VDD supply second, and the PVDD supply last.
When powering down, first set the STANDBY pin low for at least 15ms before removing PVDD, VBAT or VDD.
After 15 ms, the power supplies can be removed.
10.3.10 Hardware Control Pins
The device has four pins for control and device status: FAULT, MUTE, WARN, and STANDBY.
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10.3.10.1 FAULT
The FAULT pin reports faults and is active low under any of the following conditions:
•
•
•
•
Channel faults (overcurrent or DC detection)
Overtemperature shutdown
Overvoltage or undervoltage conditions on the VBAT or PVDD pins
Clock errors
For all listed faults, the FAULT pin remains asserted after the fault condition is rectified. Deassert the FAULT pin
by writing the CLEAR FAULT bit (bit 7) in register 0x21. The only exception is the fault report caused by
Overtemperature shutdown, for which the FAULT pin deasserts automatically when the junction temperature
returns to normal levels and the device automatically recovers.
The register reports for all fault reports remain asserted until they are cleared by writing the CLEAR FAULT bit
(bit 7) in register 0x21.
Register bits are available to mask fault categories from reporting to the FAULT pin. These bits only mask the
setting of the pin and do not affect the register reporting or protection of the device. By default all faults are
reported to the pin. See the Register Maps section for a description of the mask settings.
This pin is an open-drain output with an internal 100 kΩ pull-up resistor to VDD.
10.3.10.2 WARN
This active-low output pin reports audio clipping, overtemperature warnings, overcurrent limit warnings and POR
events.
Clipping is reported if any channel is at the maximum modulation for 20 consecutive PWM clocks (default value)
which results in a 10-µs delay to report the onset of clipping. Changing the number of required consecutive PWM
clocks in the Clip Window Register (address = 0x23) impacts the report delay time. The Clip Detect warning bit is
sticky in latching mode and can be cleared by the CLEAR FAULT bit (bit 7) in register 0x21.
An overtemperature warning (OTW) is reported if the general temperature or the channel temperature warnings
are set. The warning temperature can be set through bits 5 and 6 in register 0x01.
Register bits are available to mask either clipping, OTW or ILIMIT reporting to the pin. These bits only mask the
setting of the pin and do not affect the register reporting. By default clipping, ILIMIT and OTW are reported.
The WARN pin is latched and can be cleared by writing the CLEAR FAULT bit (bit 7) in register 0x21.
This pin is an open-drain output with an internal 100 kΩ pull-up resistor to VDD.
10.3.10.3 MUTE
This active-low input pin is used for hardware control of the mute and unmute function.
This pin has a 100 kΩ internal pull-down resistor.
10.3.10.4 STANDBY
When this active-low input pin is asserted, the device goes into shutdown and current draw is limited. This pin
can be used to shut down the device rapidly. The outputs are ramped down in less than 5 ms if the device is not
already in the Hi-Z state.
This pin has a 100 kΩ internal pull-down resistor.
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10.4 Device Functional Modes
10.4.1 Operating Modes and Faults
The operating modes and faults are listed in the following tables.
Global Faults affect the entire device while the effect and management of Channel Faults is limited to the Output
Stage. Although the system effects of a Global Fault and a Channel Fault can be identical in a 1-channel device
such as TAS6421-Q1, this split and naming convention was selected to remain compatible with the multi-channel
TAS642x-Q1 family devices.
表 4. Operating Modes
STATE NAME
STANDBY
Hi-Z
OUTPUT FETS
Hi-Z
OSCILLATOR
Stopped
Active
I2C
Active
Active
Active
Active
Hi-Z
MUTE
Switching at 50%
Switching with audio
Active
PLAY
Active
表 5. Global Faults and Actions
FAULT/
EVENT
FAULT/EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
RESULT
POR
VBAT UV
PVDD UV
VBAT or PVDD OV
OTW
All
I2C + WARN pin
Standby
Voltage fault
Hi-Z, mute, normal
I2C + FAULT pin
Hi-Z
Thermal warning
Hi-Z, mute, normal
Hi-Z, mute, normal
I2C + WARN pin
I2C + FAULT pin
None
Hi-Z
OTSD
Thermal shutdown
表 6. Channel Faults and Actions
FAULT/
EVENT
FAULT/EVENT
CATEGORY
MONITORING
MODES
REPORTING
METHOD
ACTION
TYPE
I2C + WARN or FAULT
pin
Clipping
Warning
None
Overcurrent limiting
Overcurrent fault
DC detect
Protection
I2C + WARN pin
Current limit
Mute and play
Output channel fault
I2C + FAULT pin
Hi-Z
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10.5 Programming
10.5.1 I2C Serial Communication Bus
The device communicates with the system processor through the I2C serial communication bus as an I2C slave-
only device. The processor can poll the device through I2C to determine the operating status, configure settings,
or run diagnostics. For a complete list and description of all I2C controls, see the Register Maps section.
The device includes two I2C address pins, so up to four devices can be used together in a system with no
additional bus switching hardware. The I2C ADDRx pins set the slave address of the device as listed in 表 7.
表 7. I2C Addresses
DESCRIPTION
I2C ADDR1
I2C ADDR0
I2C Write
0xD4
I2C Read
0xD5
Device 0
Device 1
Device 2
Device 3
0
0
1
1
0
1
0
1
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
10.5.2 I2C Bus Protocol
The device has a bidirectional serial-control interface that is compatible with the Inter IC (I2C) bus protocol and
supports 100 kbps and 400 kbps data transfer rates for random and sequential write and read operations. The
TAS6421-Q1 device is a slave-only device that does not support a multimaster bus environment or wait-state
insertion. The control interface is used to program the registers of the device and to read device status.
The I2C bus uses two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially, one bit at a time. The address and data are transferred in byte (8-
bit) format with the most-significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data terminal (SDA) while the clock is HIGH to indicate a start and stop
conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. The master generates the 7-bit
slave address and the read/write (R/W) bit to open communication with another device and then wait for an
acknowledge condition. The device holds SDA LOW during the acknowledge-clock period to indicate an
acknowledgment. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals
via a bidirectional bus using a wired-AND connection. An external pull-up resistor must be used for the SDA and
SCL signals to set the HIGH level for the bus. The number of bytes that can be transmitted between start and
stop conditions is unlimited. When the last word transfers, the master generates a stop condition to release the
bus.
R/
W
8-Bit Register Data for
Address (N)
8-Bit Register Data for
Address (N)
7-Bit Slave Address
A
8-Bit Register Address (N)
A
A
A
SDA
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SCL
Start
Stop
图 30. Typical I2C Sequence
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t
t
t
r
t
f
w(H)
w(L)
SCL
t
t
h1
su1
SDA
图 31. SCL and SDA Timing
Use the I2C ADDRx pins to program the device slave address. Read and write data can be transmitted using
single-byte or multiple-byte data transfers.
10.5.3 Random Write
As shown in 图 32, a single-byte data-write transfer begins with the master device transmitting a start condition
followed by the I2C device address and the R/W bit. The R/W bit determines the direction of the data transfer.
For a write data transfer, the R/W bit is a 0. After receiving the correct I2C device address and the R/W bit, the
device responds with an acknowledge bit. Next, the master transmits the address byte or bytes corresponding to
the internal memory address being accessed. After receiving the address byte, the device again responds with
an acknowledge bit. Next, the master device transmits the data byte to be written to the memory address being
accessed. After receiving the data byte, the device again responds with an acknowledge bit. Finally, the master
device transmits a stop condition to complete the single-byte data-write transfer.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
ACK
A4
R/W
A7
ACK
A6 A5 A4 A3 A2 A1 A0
D7 D6 D5
ACK
A6 A5
A3 A2 A1 A0
D4 D3 D2 D1 D0
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
Data Byte
图 32. Random Write Transfer
10.5.4 Sequential Write
A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are
transmitted by the master to the device as shown in 图 33. After receiving each data byte, the device responds
with an acknowledge bit and the I2C subaddress is automatically incremented by one.
Start
Condition
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A5
A0
A4 A3
A0
ACK
A1
R/W ACK
A6 A5
ACK
ACK
ACK
D0
A6
A7
A1
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte
Other Data Byte
Last Data Byte
图 33. Sequential Write Transfer
10.5.5 Random Read
As shown in 图 34, a single-byte data-read transfer begins with the master device transmitting a start condition
followed by the I2C device address and the R/W bit. For the data-read transfer, both a write followed by a read
occur. Initially, a write occurs to transfer the address byte or bytes of the internal memory address to be read. As
a result, the R/W bit is a 0. After receiving the address and the R/W bit, the device responds with an
acknowledge bit. In addition, after sending the internal memory address byte or bytes, the master device
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transmits another start condition followed by the address and the R/W bit again. This time the R/W bit is a 1,
indicating a read transfer. After receiving the address and the R/W bit, the device again responds with an
acknowledge bit. Next, the device transmits the data byte from the memory address being read. After receiving
the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the
single-byte data-read transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
D0 D6
A6 A5
A1 A0
A7 A6 A5 A4
A0
A6 A5
A1 A0
D7 D6
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
Data Byte
图 34. Random Read Transfer
10.5.6 Sequential Read
A sequential data-read transfer is identical to a single-byte data-read transfer except that multiple data bytes are
transmitted by the device to the master device as shown in 图 35. Except for the last data byte, the master
device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C
subaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge bit followed
by a stop condition to complete the transfer.
Repeat Start
Condition
Acknowledge
Start
Condition
Not
Acknowledge
Acknowledge
Acknowledge
Acknowledge
Acknowledge
R/W ACK
ACK
R/W ACK
ACK
ACK
ACK
D0
A6
A0
A7 A6 A5
A0
A6
A0
D7
D0
D7
D0
D7
I2C Device Address
and R/W Bit
I2C Device Address
and R/W Bit
Stop
Condition
Subaddress
First Data Byte Other Data Byte Last Data Byte
图 35. Sequential Read Transfer
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10.6 Register Maps
表 8. I2C Address Register Definitions
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
Type
R/W
R/W
R/W
R/W
R/W
R/W
R
Register Description
Section
Go
Mode Control
Miscellaneous Control 1
Miscellaneous Control 2
Go
Go
SAP Control (Serial Audio-Port Control)
Channel State Control
Channel 1 Volume Control
RESERVED
Go
Go
Go
R
RESERVED
R
RESERVED
R/W
R/W
R
DC Diagnostic Control 1
DC Diagnostic Control 2
RESERVED
Go
Go
R
DC Load Diagnostic Report 1
RESERVED
Go
R
R
DC Load Diagnostic Report 3 - Line Output
Channel State Reporting
Channel Faults (Overcurrent, DC Detection)
Global Faults 1
Go
Go
Go
Go
Go
Go
Go
Go
Go
Go
R
R
R
R
Global Faults 2
R
Warnings
R/W
R/W
R/W
R
Pin Control
AC Load Diagnostic Control 1
AC Load Diagnostic Control 2
AC Load Diagnostic Report Channel 1
RESERVED
R
R
RESERVED
R
RESERVED
R
AC Load Diagnostic Phase Report High
AC Load Diagnostic Phase Report Low
AC Load Diagnostic STI Report High
AC Load Diagnostic STI Report Low
RESERVED
Go
Go
Go
Go
R
R
R
R
R
RESERVED
R/W
R/W
R/W
R
Miscellaneous Control 3
Clip Control
Go
Go
Go
Go
Go
Go
Clip Window
Clip Warning
R
ILIMIT Status
R/W
R
Miscellaneous Control 4
RESERVED
R
RESERVED
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10.6.1 Mode Control Register (address = 0x00) [default = 0x00]
The Mode Control register is shown in 图 36 and described in 表 9.
图 36. Mode Control Register
7
6
5
4
3
2
1
0
RESET
R/W-0
RESERVED
CH1 LO MODE
R/W-0
RESERVED
表 9. Mode Control Field Descriptions
Bit
Field
Type
Reset
Description
7
RESET
R/W
0
0: Normal operation
1: Resets the device. Self-clearing, reads back 0.
RESERVED
6-4
3
RESERVED
R/W
R/W
000
0
CH1 LO MODE
0: Channel 1 is in normal/speaker mode
1: Channel 1 is in line output mode
RESERVED
2-0
RESERVED
R/W
000
10.6.2 Miscellaneous Control 1 Register (address = 0x01) [default = 0x32]
The Miscellaneous Control 1 register is shown in 图 37 and described in 表 10.
图 37. Miscellaneous Control 1 Register
7
6
5
4
3
2
1
0
HPF BYPASS
R/W-0
OTW CONTROL
R/W-01
OC CONTROL
R/W-1
VOLUME RATE
R/W-00
GAIN
R/W-10
表 10. Misc Control 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
HPF BYPASS
R/W
0
0: High pass filter enabled
1: High pass filter disabled
6–5
OTW CONTROL
R/W
01
00: Global overtemperature warning set to 140°C
01: Global overtemperature warning set to 130C
10: Global overtemperature warning set to 120°C
11: Global overtemperature warning set to 110°C
4
OC CONTROL
VOLUME RATE
R/W
R/W
1
0: Overcurrent is level 1
1: Overcurrent is level 2
3–2
00
00: Volume update rate is 1 step / FSYNC
01: Volume update rate is 1 step / 2 FSYNCs
10: Volume update rate is 1 step / 4 FSYNCs
11: Volume update rate is 1 step / 8 FSYNCs
1–0
GAIN
R/W
10
00: Gain level 1 = 7.5 V peak output voltage
01: Gain Level 2 = 15 V peak output voltage
10: Gain Level 3 = 21 V peak output voltage
11: Gain Level 4 = 29 V peak output voltage
10.6.3 Miscellaneous Control 2 Register (address = 0x02) [default = 0x62]
The Miscellaneous Control 2 register is shown in 图 38 and described in 表 11.
34
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图 38. Miscellaneous Control 2 Register
7
6
5
4
3
2
1
0
RESERVED
PWM FREQUENCY
R/W-110
RESERVED
SDM_OSR
R/W-0
RESERVED
表 11. Misc Control 2 Field Descriptions
Bit
7
Field
RESERVED
Type
R/W
R/W
Reset
0
Description
RESERVED
6–4
PWM FREQUENCY
110
000: 8 × fS (352.8 kHz / 384 kHz)
001: 10 × fS (441 kHz / 480 kHz)
010: RESERVED
011: RESERVED
100: RESERVED
101: 38 × fS (1.68 MHz / 1.82 MHz)
110: 44 × fS (1.94 MHz / 2.11 MHz)
111: 48 × fS (2.12 MHz / not supported)
RESERVED
3
2
RESERVED
SDM_OSR
R/W
R/W
0
0
0: 64x Oversampling rate
1: 128x Oversampling rate
RESERVED
1–0
RESERVED
R/W
10
10.6.4 SAP Control (Serial Audio-Port Control) Register (address = 0x03) [default = 0x04]
The SAP Control (serial audio-port control) register is shown in 图 39 and described in 表 12.
图 39. SAP Control Register
7
6
5
4
3
2
1
0
INPUT SAMPLING RATE
R/W-00
TDM SLOT SELECT
R/W-000
INPUT FORMAT
R/W-100
表 12. SAP Control Field Descriptions
Bit
Field
Type
Reset
Description
7–6
INPUT SAMPLING RATE
R/W
00
00: 44.1 kHz
01: 48 kHz
10: 96 kHz
11: RESERVED
000: Select slot 1 in TDM8/4 or channel 1 in I2S mode
001: Select slot 2 in TDM8/4 or channel 2 in I2S mode
010: Select slot 3 in TDM8/4
5–3
TDM SLOT SELECT
R/W
000
011: Select slot 4 in TDM8/4
100: Select slot 5 in TDM8
101: Select slot 6 in TDM8
110: Select slot 7 in TDM8
111: Select slot 8 in TDM8
2–0
INPUT FORMAT
R/W
100
000: 24-bit right justified
001: 20-bit right justified
010: 18-bit right justified
011: 16-bit right justified
100: I2S (16-bit or 24-bit)
101: Left justified (16-bit or 24-bit)
110: DSP mode (16-bit or 24-bit)
111: RESERVED
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10.6.5 Channel State Control Register (address = 0x04) [default = 0x55]
The Channel State Control register is shown in 图 40 and described in 表 13.
图 40. Channel State Control Register
7
6
5
4
3
2
1
0
CH1 STATE CONTROL
R/W-01
RESERVED
表 13. Channel State Control Field Descriptions
Bit
Field
Type
Reset
Description
7–6
CH1 STATE CONTROL
R/W
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
RESERVED
5–0
RESERVED
R/W
010101
36
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10.6.6 Channel 1 Volume Control Register (address = 0x05) [default = 0xCF]
The Channel 1 Volume Control registers is shown in 图 41 and described in 表 14.
图 41. Channel 1 Volume Control Register
7
6
5
4
3
2
1
0
CH 1 VOLUME
R/W-11001111
表 14. Ch 1 Volume Control Field Descriptions
Bit
Field
CH 1 VOLUME
Type
Reset
Description
7–0
R/W
11001111
8-Bit Volume Control for the output channel, 0.5 dB/step:
0xFF: 24 dB
0xCF: 0 dB
0x07: –100 dB
< 0x07: MUTE
10.6.7 DC Load Diagnostic Control 1 Register (address = 0x09) [default = 0x00]
The DC Diagnostic Control 1 register is shown in 图 42 and described in 表 15.
图 42. DC Load Diagnostic Control 1 Register
7
6
5
4
3
2
1
0
DC LDG
ABORT
2x_RAMP
2x_SETTLE
RESERVED
LDG LO
ENABLE
LDG BYPASS
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
表 15. DC Load Diagnostics Control 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
DC LDG ABORT
R/W
0
0: Default state, clear after abort
1: Aborts the load diagnostics in progress
6
5
2x_RAMP
R/W
R/W
0
0
0: Normal ramp time
1: Double ramp time
2x_SETTLE
0: Normal Settle time
1: Double settling time
RESERVED
4–2
1
RESERVED
R/W
R/W
000
0
LDG LO ENABLE
0: Line output diagnostics are disabled
1: Line output diagnostics are enabled
0
LDG BYPASS
R/W
0
0: Automatic diagnostics when leaving Hi-Z and after
channel fault
1: Diagnostics are not run automatically
10.6.8 DC Load Diagnostic Control 2 Register (address = 0x0A) [default = 0x11]
The DC Diagnostic Control 2 register is shown in 图 43 and described in 表 16.
图 43. DC Load Diagnostic Control 2 Register
7
6
5
4
3
2
1
0
CH1 DC LDG SL
R/W-0001
RESERVED
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表 16. DC Load Diagnostics Control 2 Field Descriptions
Bit
Field
Type
Reset
Description
7–4
CH1 DC LDG SL
R/W
0001
DC load diagnostics shorted-load threshold
0000: 0.5 Ω
0001: 1 Ω
0010: 1.5 Ω
...
1001: 5 Ω
RESERVED
3–0
RESERVED
R/W
0001
10.6.9 DC Load Diagnostic Report 1 Register (address = 0x0C) [default = 0x00]
DC Load Diagnostic Report 1 register is shown in 图 44 and described in 表 17.
图 44. DC Load Diagnostic Report 1 Register
7
6
5
4
3
2
1
0
CH1 S2G
R-0
CH1 S2P
R-0
CH1 OL
R-0
CH1 SL
R-0
RESERVED
表 17. DC Load Diagnostics Report 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1 S2G
CH1 S2P
CH1 OL
R
0
0: No short-to-GND detected
1: Short-To-GND Detected
6
5
R
R
R
R
0
0: No short-to-power detected
1: Short-to-power detected
0
0: No open load detected
1: Open load detected
4
CH1 SL
0
0: No shorted load detected
1: Shorted load detected
RESERVED
3–0
RESERVED
0000
38
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10.6.10 DC Load Diagnostics Report 3 Line Output Register (address = 0x0E) [default = 0x00]
The DC Load Diagnostic Report, Line Output, register is shown in 图 45 and described in 表 18.
图 45. DC Load Diagnostics Report 3 Line Output Register
7
6
5
4
3
2
1
0
RESERVED
CH1 LO LDG
R-0
RESERVED
表 18. DC Load Diagnostics Report 3 Line Output Field Descriptions
Bit
7–4
3
Field
Type
R
Reset
0000
0
Description
RESERVED
CH1 LO LDG
RESERVED
R
0: No line output detected on channel 1
1: Line output detected on channel 1
RESERVED
2–0
RESERVED
R
000
10.6.11 Channel State Reporting Register (address = 0x0F) [default = 0x40]
The Channel State Reporting register is shown in 图 46 and described in 表 19.
图 46. Channel State-Reporting Register
7
6
5
4
3
2
1
0
CH1 STATE REPORT
R-01
RESERVED
表 19. State-Reporting Field Descriptions
Bit
Field
Type
Reset
Description
7–6
CH1 STATE REPORT
R
01
00: PLAY
01: Hi-Z
10: MUTE
11: DC load diagnostics
RESERVED
5–0
RESERVED
R
000000
10.6.12 Channel Faults (Overcurrent, DC Detection) Register (address = 0x10) [default = 0x00]
The Channel Faults (overcurrent, DC detection) register is shown in 图 47 and described in 表 20.
图 47. Channel Faults Register
7
6
5
4
3
2
1
0
CH1 OC
R-0
RESERVED
CH1 DC
R-0
RESERVED
表 20. Channel Faults Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1 OC
R
0
0: No overcurrent fault detected
1: Overcurrent fault detected
RESERVED
6–4
3
RESERVED
CH1 DC
R
R
000
0
0: No DC fault detected
1: DC fault detected
RESERVED
2–0
RESERVED
R
000
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10.6.13 Global Faults 1 Register (address = 0x11) [default = 0x00]
The Global Faults 1 register is shown in 图 48 and described in 表 21.
图 48. Global Faults 1 Register
7
6
5
4
3
2
1
0
RESERVED
INVALID
CLOCK
PVDD OV
VBAT OV
PVDD UV
VBAT UV
R-0
R-0
R-0
R-0
R-0
表 21. Global Faults 1 Field Descriptions
Bit
7–5
4
Field
Type
R
Reset
000
0
Description
RESERVED
RESERVED
INVALID CLOCK
R
0: No clock fault detected
1: Clock fault detected
3
2
1
0
PVDD OV
VBAT OV
PVDD UV
VBAT UV
R
R
R
R
0
0
0
0
0: No PVDD overvoltage fault detected
1: PVDD overvoltage fault detected
0: No VBAT overvoltage fault detected
1: VBAT overvoltage fault detected
0: No PVDD undervoltage fault detected
1: PVDD undervoltage fault detected
0: No VBAT undervoltage fault detected
1: VBAT undervoltage fault detected
10.6.14 Global Faults 2 Register (address = 0x12) [default = 0x00]
The Global Faults 2 register is shown in 图 49 and described in 表 22.
图 49. Global Faults 2 Register
7
6
5
4
3
2
1
0
RESERVED
OTSD
R-0
CH1 OTSD
R-0
RESERVED
表 22. Global Faults 2 Field Descriptions
Bit
7–5
4
Field
Type
R
Reset
000
0
Description
RESERVED
OTSD
RESERVED
R
0: No global overtemperature shutdown
1: Global overtemperature shutdown
3
CH1 OTSD
RESERVED
R
R
0
0: No overtemperature shutdown on Ch1
1: Overtemperature shutdown on Ch1
RESERVED
2–0
000
10.6.15 Warnings Register (address = 0x13) [default = 0x20]
The Warnings register is shown in 图 50 and described in 表 23.
图 50. Warnings Register
7
6
5
4
3
2
1
0
RESERVED
VDD POR
R-1
OTW
R-0
OTW CH1
R-0
RESERVED
40
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表 23. Warnings Field Descriptions
Bit
7–6
5
Field
Type
R
Reset
00
Description
RESERVED
VDD POR
RESERVED
R
1
0: No VDD POR has occurred
1: VDD POR occurred
4
3
OTW
R
R
R
0
0: No global overtemperature warning
1: Global overtemperature warning
OTW CH1
RESERVED
0
0: No overtemperature warning on channel 1
1: Overtemperature warning on channel 1
RESERVED
2–0
000
10.6.16 Pin Control Register (address = 0x14) [default = 0x00]
The Pin Control register is shown in 图 51 and described in 表 24.
图 51. Pin Control Register
7
6
5
4
3
2
1
0
MASK OC
R/W-0
MASK OTSD
R/W-0
MASK UV
R/W-0
MASK OV
R/W-0
MASK DC
R/W-0
RESERVED
MASK CLIP
R/W-0
MASK OTW
R/W-0
表 24. Pin Control Field Descriptions
Bit
Field
MASK OC
Type
Reset
Description
7
R/W
0
0: Report overcurrent faults on the FAULT pin
1: Do not report overcurrent faults on the FAULT Pin
6
5
4
3
MASK OTSD
MASK UV
MASK OV
MASK DC
R/W
R/W
R/W
R/W
0
0
0
0
0: Report overtemperature faults on the FAULT pin
1: Do not report overtemperature faults on the FAULT pin
0: Report undervoltage faults on the FAULT pin
1: Do not report undervoltage faults on the FAULT pin
0: Report overvoltage faults on the FAULT pin
1: Do not report overvoltage faults on the FAULT pin
0: Report DC faults on the FAULT pin
1: Do not report DC faults on the FAULT pin
RESERVED
2
1
RESERVED
MASK CLIP
R/W
R/W
0
0
0: Report clipping on the configured pin (WARN or FAULT)
1: Do not report clipping on the configured pin (WARN or
FAULT)
0
MASK OTW
R/W
0
0: Report overtemperature warnings on the WARN pin
1: Do not report overtemperature warnings on the WARN pin
10.6.17 AC Load Diagnostic Control 1 Register (address = 0x15) [default = 0x00]
The AC Load Diagnostic Control 1 register is shown in 图 52 and described in 表 25.
图 52. AC Load Diagnostic Control 1 Register
7
6
5
4
3
2
1
0
CH1 GAIN
R/W-0
RESERVED
CH1 ENABLE
R/W-0
RESERVED
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表 25. AC Load Diagnostic Control 1 Field Descriptions
Bit
Field
Type
Reset
Description
7
CH1: GAIN
R/W
0
0: Gain 1
1: Gain 4
6–4
3
RESERVED
R/W
R/W
000
0
RESERVED
CH1 ENABLE
0: AC diagnostics disabled
1: Enable AC diagnostics
RESERVED
2–0
RESERVED
R/W
000
10.6.18 AC Load Diagnostic Control 2 Register (address = 0x16) [default = 0x00]
The AC Load Diagnostic Control 2 register is shown in 图 53 and described in 表 26.
图 53. AC Load Diagnostic Control 2 Register
7
6
5
4
3
2
1
0
AC_DIAGS_LO
OPBACK
RESERVED
AC TIMING
AC CURRENT
RESERVED
R/W-0
R/W-0
R/W-0
R/W-0
表 26. AC Load Diagnostic Control 2 Field Descriptions
Bit
Field
Type
Reset
Description
7
AC_DIAGS_LOOPBACK
R/W
0
0: Disable AC Diag loopback
1: Enable AC Diag loopback
RESERVED
6-5
4
RESERVED
AC TIMING
R/W
R/W
00
0
0: 32 Cycles
1: 64 Cycles
3-2
AC CURRENT
R/W
00
00: 10mA
01: 19 mA
10: RESERVED
11: RESERVED
RESERVED
1-0
RESERVED
R/W
00
10.6.19 AC Load Diagnostic Impedance Report Ch1 Register (address = 0x17) [default = 0x00]
The AC Load Diagnostic Report Ch1 registers is shown in 图 54 and described in 表 27.
图 54. AC Load Diagnostic Impedance Report Ch1 Register
7
6
5
4
3
2
1
0
CH1 IMPEDANCE
R-00000000
表 27. Ch1 AC LDG Impedance Report Field Descriptions
Bit
Field
CH1 IMPEDANCE
Type
Reset
Description
7–0
R
00000000
8-bit AC-load diagnostic report for each channel with a step size
of 0.2496 Ω/bit (control by register 0x15 and register 0x16)
0x00000000: 0 Ω
0x00000001: 0.2496 Ω
...
0x11111111: 63.65 Ω
42
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10.6.20 AC Load Diagnostic Phase Report High Register (address = 0x1B) [default = 0x00]
The AC Load Diagnostic Phase High value registers is shown in 图 55 and described in 表 28.
图 55. AC Load Diagnostic (LDG) Phase High Report Register
7
6
5
4
3
2
1
0
AC Phase High
R-00000000
表 28. AC LDG Phase High Report Field Descriptions
Bit
Field
AC Phase High
Type
Reset
Description
7–0
R
00000000 Bit 15:8
10.6.21 AC Load Diagnostic Phase Report Low Register (address = 0x1C) [default = 0x00]
The AC Load Diagnostic Phase Low value registers is shown in 图 56 and described in 表 29.
图 56. AC Load Diagnostic (LDG) Phase Low Report Register
7
6
5
4
3
2
1
0
AC Phase Low
R-00000000
表 29. AC LDG Phase Low Report Field Descriptions
Bit
Field
AC Phase Low
Type
Reset
Description
7–0
R
00000000 Bit 7:0
10.6.22 AC Load Diagnostic STI Report High Register (address = 0x1D) [default = 0x00]
The AC Load Diagnostic STI High value registers is shown in 图 57 and described in 表 30.
图 57. AC Load Diagnostic (LDG) STI High Report Register
7
6
5
4
3
2
1
0
AC STI High
R-00000000
表 30. AC LDG STI High Report Field Descriptions
Bit
Field
AC STI High
Type
Reset
Description
7–0
R
00000000 Bit 15:8
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10.6.23 AC Load Diagnostic STI Report Low Register (address = 0x1E) [default = 0x00]
The AC Load Diagnostic STI Low value registers is shown in 图 58 and described in 表 31.
图 58. AC Load Diagnostic (LDG) STI Low Report Register
7
6
5
4
3
2
1
0
AC STI Low
R-00000000
表 31. Ch1 AC LDG STI Low Report Field Descriptions
Bit
Field
Type
Reset
Description
7–0
AC STI Low
R
00000000 Bit 7:0
10.6.24 Miscellaneous Control 3 Register (address = 0x21) [default = 0x00]
The Miscellaneous Control 3 register is shown in 图 59 and described in 表 32.
图 59. Miscellaneous Control 3 Register
7
6
5
4
3
2
1
0
CLEAR FAULT
TDM SLOT
SIZE
MASK ILIMIT
WARNING
RESERVED
OTSD AUTO
RECOVERY
RESERVED
R/W-0
R/W-0
R/W-0
R/W-0
表 32. Misc Control 3 Field Descriptions
Bit
Field
CLEAR FAULT
Type
Reset
Description
7
R/W
0
0: Normal operation
1: Clear fault
6
5
TDM SLOT SIZE
R/W
R/W
0
0
0: TDM slot size is 24-bit or 32-bit
1: TDM slot size is 16-bit
MASK ILIMIT WARNING
0: Report ILIMIT on the WARN pin
1: Do not report ILIMIT on the WARN pin
RESERVED
4
3
RESERVED
R/W
R/W
0
0
OTSD AUTO RECOVERY
0: OTSD is latched
1: OTSD is auto-recovery
RESERVED
2–0
RESERVED
R/W
000
10.6.25 Clip Control Register (address = 0x22) [default = 0x01]
The Clip Detect register is shown in 图 60 and described in 表 33. To ensure the Clip Detect Warning is
operating according to the expectation, the related bit values in the Clip Window Register (address = 0x23)
[default = 0x14] and Clip Warning Register must be set accordingly.
图 60. Clip Control Register
7
6
5
4
3
2
1
0
RESERVED
CLIP_PIN
R/W-0
CLIP_LATCH
R/W-0
CLIPDET_EN
R/W-1
表 33. Clip Control Field Descriptions
Bit
7–3
2
Field
Type
R/W
R/W
Reset
00000
0
Description
RESERVED
CLIP_PIN
RESERVED
0: CH1 Clip Detect reports to WARN pin
1: CH1 Clip Detect reports to FAULT pin
44
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表 33. Clip Control Field Descriptions (接下页)
Bit
Field
Type
Reset
Description
1
CLIP_LATCH
R/W
0
0: Pin latching
1: Pin non-latching
0
CLIPDET_EN
R/W
1
0: Clip detect disable
1: Clip Detect Enable
10.6.26 Clip Window Register (address = 0x23) [default = 0x14]
The Clip Window register is shown in 图 61 and described in 表 34. The register value represents the minimum
number of 100% duty-cycle PWM cycles in hexadecimal notation before Clip Detect is reported. A register value
of 0 is not permitted. If Clip Detect is set to non-latching, the register value has no function.
图 61. Clip Window Register
7
6
5
4
3
2
1
0
CLIP_WINDOW_SEL[7:1]
R/W-00010100
表 34. Clip Window Field Descriptions
Bit
Field
CLIP_WINDOW_SEL[7:1]
Type
Reset
Description
7–0
R/W
00010100
00010100: 20 100% duty-cycle PWM cycles before Clip
Detect is triggered
10.6.27 Clip Warning Register (address = 0x24) [default = 0x00]
The Clip Window register is shown in 图 62 and described in 表 35.
图 62. Clip Warning Register
7
6
5
4
3
2
1
0
RESERVED
CH1_CLIP
R-0
表 35. Clip Warning Field Descriptions
Bit
7–1
0
Field
Type
R
Reset
0000000
0
Description
RESERVED
CH1_CLIP
RESERVED
R
0: No Clip Detect
1: Clip Detect
10.6.28 ILIMIT Status Register (address = 0x25) [default = 0x00]
The ILIMIT Status register is shown in 图 63 and described in 表 36.
图 63. ILIMIT Status Register
7
6
5
4
3
2
1
0
RESERVED
CH1_ILIMIT_W
ARN
R-0
表 36. ILIMIT Status Field Descriptions
Bit
7–1
0
Field
Type
R
Reset
0000000
0
Description
RESERVED
RESERVED
CH1_ILIMIT_WARN
R
0: No ILIMIT
1: ILIMIT Warning
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10.6.29 Miscellaneous Control 4 Register (address = 0x26) [default = 0x40]
The Miscellaneous Control 4 register is shown in and described in 表 37.
图 64. Miscellaneous Control 4 Register
7
6
5
4
3
2
1
0
RESERVED
BCLK_INV
R/W-0
HPF_CORNER[2:0]
R/W-000
表 37. Misc Control 4 Field Descriptions
Bit
7–4
3
Field
Type
R/W
R/W
Reset
0100
0
Description
RESERVED
BCLK_INV
RESERVED
0: All other MCLK/BCLK frequency / phase use cases
1: Inverted MCLK/BCLK phase relationship when MCLK/BCLK
run at the same frequency
2–0
HPF_CORNER[2:0]
R/W
000
000: 3.7 Hz
001: 7.4 Hz
010: 15 Hz
011: 30 Hz
100: 59 Hz
101: 118 Hz
110: 235 Hz
111: 463 Hz
46
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11 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The TAS6421-Q1 is a mono-channel class-D digital-input audio-amplifier design for use in automotive head units
and external amplifier modules. The TAS6421-Q1 incorporates the necessary functionality to perform in
demanding OEM applications.
11.1.1 AM-Radio Band Avoidance
AM-radio frequency interference can be avoided by setting the switching frequency of the device above the AM
band. The switching frequency options available are 38 × fS, 44 × fS, and 48 × fS. If the switch frequency cannot
be set above the AM band, then use the two options of 8 × fS and 10 × fS. These options should be changed to
avoid AM active channels.
11.1.2 Demodulation Filter Design
The amplifier outputs are driven by high-current LDMOS transistors in an H-bridge configuration. These
transistors are either fully off or fully on. The result is a square-wave output signal with a duty cycle that is
proportional to the amplitude of the audio signal. An LC demodulation filter is used to recover the audio signal.
The filter attenuates the high-frequency components of the output signals that are out of the audio band. The
design of the demodulation filter significantly affects the audio performance of the power amplifier. Therefore, to
meet the system THD+N requirements, the selection of the inductors used in the output filter should be carefully
considered.
11.1.3 Line Driver Applications
In many automotive audio applications, the same head unit must drive either a speaker (with several ohms of
impedance) or an external amplifier input (with several kiloohms of impedance). The design is capable of
supporting both applications and has special line-drive gain and diagnostics. Coupled with the high switching
frequency, the device is well suited for this type of application. Set the output channel in line driver mode through
I2C register 0x00, the externally connected amplifier must have a differential impedance from 600 Ω to 4.7 kΩ for
the DC line diagnostic to detect the connected external amplifier. 图 65 shows the recommended external
amplifier input configuration.
Output Filter
External Amplifier
3.3 µH
1 …F
1 …F
1 nF
600 ꢀ
to
1 …F
4.7 kꢀ
1 nF
3.3 µH
1 …F
100 kꢀ
100 kꢀ
图 65. External Amplifier Input Configuration for Line Driver
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11.2 Typical Applications
11.2.1 BTL Application
图 66 shows the schematic of a typical mono-channel solution in a typical use case.
PVDD
Input
PVDD
1 ꢀF
1 nF
100 ꢀF
Chassis GND
56
PVDD
PVDD
PVDD
1
GND
0.1 ꢀF
10 ꢀF
1 ꢀF
55
2
3
4
5
PVDD
VBAT
AREF
VREG
PVDD
54
53
52
51
NC
NC
NC
NC
1 ꢀF
1 ꢀF
6
VCOM
50
49
7
8
NC
NC
AVSS
AVDD
1 ꢀF
48
47
46
45
9
1 ꢀF
BST_P
OUT_P
GND
GVDD
3.3 ꢀH
2.2 ꢀF
10
11
1 ꢀF
1 ꢀF
1 nF
1 nF
NC
4 ꢁ
GND
3.3 ꢀH
OUT_M
BST_M
NC
12
13
14
15
16
MCLK
SCLK
FSYNC
SDIN1
GND
44
43
1 ꢀF
DSP
42
41
40
39
38
NC
NC
NC
NC
NC
17
18
GND
GND
1 uF
19
VDD
SCL
VDD
2 kꢁ
2 kꢁ
20
21
37
36
NC
NC
SDA
22
23
I2C ADDR0
35
34
33
32
31
30
29
NC
NC
NC
NC
NC
NC
NC
I2C ADDR1
STANDBY
Micro
24
25
MUTE
FAULT
WARN
26
27
28
GND
图 66. TAS6421-Q1 Typical Mono-Channel BTL Application Schematic
48
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Typical Applications (接下页)
11.2.1.1 Design Requirements
Use the following requirements for this design:
•
•
•
This example is focused on the smallest solution size for 1× 25 W output power into 4 Ω with a battery supply
of 14.4 V.
The switching frequency is set above the AM-band with 44 times the input sample rate of 48 kHz which
results in a frequency of 2.11 MHz.
The selection of a 2.11 MHz switching frequency enables the use of a small output inductor value of 3.3 µH
which leads to a very small solution size.
11.2.1.1.1 Communication
All communications to the TAS6421-Q1 are through the I2C protocol. A system controller can communicate with
the device through the SDA pins and SCL pins. The TAS6421-Q1 is an I2C slave device and requires a master.
The device cannot generate an I2C clock or initiate a transaction. The maximum clock speed accepted by the
device is 400 kHz. If multiple TAS6421-Q1 devices are on the same I2C bus, the I2C address must be different
for each device. Up to four TAS6421-Q1 devices can be on the same I2C bus.
The I2C bus is shared internally.
注
Complete any internal operations, such as load diagnostics, before reading the registers
for the results.
11.2.1.2 Detailed Design Procedure
11.2.1.2.1 Hardware Design
Use the following procedure for the hardware design:
•
Determine the input format. The input format can be either I2S or TDM mode. The mode determines the
correct pin connections and the I2C register settings.
•
Determine the power output that is required into the load. The power requirement determines the required
power-supply voltage and current. The output reconstruction-filter components that are required are also
driven by the output power.
•
With the requirements, adjust the typical application schematic in 图 66 for the input connections.
11.2.1.2.2 Digital Input and the Serial Audio Port
The TAS6421-Q1 device supports four different digital input formats which are: I2S, Right Justified, Left Justified,
and TDM mode. Depending on the format, the device can support 16, 18, 20, 24, and 32 bit data. The supported
frequencies are 96 kHz, 48 kHz, and 44.1 kHz. Please see SAP Control (Serial Audio-Port Control) Register
(address = 0x03) [default = 0x04] for the complete matrix to set up the serial audio port.
注
Bits 3, 4, and 5 in this register are ignored in all input formats except for TDM. Setting up
all the control registers to the system requirements should be done before the device is
placed in Mute mode or Play mode. After the registers are setup, use bit 7 in register 0x21
to clear any faults. Then read the fault registers to make sure no faults are present. When
no faults are present, use register 0x04 to place the device properly into play mode.
11.2.1.2.3 Bootstrap Capacitors
The bootstrap capacitors provide the gate-drive voltage of the upper N-channel FET. These capacitors must be
sized appropriately for the system specification. A special condition can occur where the bootstrap may sag if the
capacitor is not sized accordingly. The special condition is just below clipping where the PWM is slightly less
than 100% duty cycle with sustained low-frequency signals. Changing the bootstrap capacitor value to 2.2 µF for
driving subwoofers that require frequencies below 30 Hz may be necessary.
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Typical Applications (接下页)
11.2.1.2.4 Output Reconstruction Filter
The output FETs drive the amplifier outputs in an H-Bridge configuration. These transistors are either fully off or
fully on. The result is a square-wave output signal with a duty cycle that is proportional to the amplitude of the
audio signal. The amplifier outputs require a reconstruction filter that comprises a series inductor and a capacitor
to ground on each output, generally called an LC filter. The LC filter attenuates the PWM frequency and reduces
electromagnetic emissions, allowing the reconstructed audio signal to pass to the speakers. Refer to the Class-D
LC Filter Design Application Report for a detailed description of proper component description and design of the
LC filter based upon the specified load and frequency response. The recommended low-pass cutoff frequency of
the LC filter is dependent on the selected switching frequency. The low-pass cutoff frequency can be as high as
100 kHz for a PWM frequency of 2.1 MHz. At a PWM frequency of 384 kHz the low-pass cutoff frequency should
be less than 40 kHz. Certain specifications must be understood for a proper inductor. The inductance value is
given at zero current, but the TAS6421-Q1 device has current. Use the inductance versus current curve for the
inductor to make sure the inductance does not drop below 1 µH (for fSW = 2.1 MHz) at the maximum current
provided by the system design. The DCR of the inductor directly affects the output power of the system design.
The lower the DCR, the more power is provided to the speakers. The typical inductor DCR for a 4 Ω system is 40
to 50 mΩ and for a 2 Ω system is 20 to 25 mΩ. Further guidance is provided in the Inductor Selection Guide for
2.1 MHz Class-D Amplifiers.
11.2.2 Application Curves
10
100
90
80
70
60
50
40
30
20
10
0
2 W Load
4 W Load
2 W Load
4 W Load
1
0.1
0.01
0.001
10m
100m
1
Output Power (W)
10
100
5
7
9
11 13 15 17 19 21 23 25 26
Supply Voltage (V)
fSW = 2.1 MHz
10% THD
fSW = 2.1 MHz
图 67. THD+N vs Power
图 68. Output Power vs Supply Voltage
50
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12 Power Supply Recommendations
The TAS6421-Q1 requires three power supplies. The PVDD supply is the high-current supply in the
recommended supply range. The VBAT supply is a lower current supply that must be in the recommended
supply range. The PVDD and VBAT pins can be connected to the same supply if the recommended supply range
for VBAT is maintained. The VDD supply is the 3.3 Vdc logic supply and must be maintained in the tolerance as
shown in the Recommended Operating Conditions table.
For best device performance and to avoid unexpected device behavior follow the recommendations in the
Vehicle-Battery Power-Supply Sequence section.
13 Layout
13.1 Layout Guidelines
The pinout of the TAS6421-Q1 was selected to provide flowthrough layout with all high-power connections on the
right side, and all low-power signals and supply decoupling on the left side.
图 69 shows the area for the components in the application example (see the Typical Applications section).
The TAS6421-Q1 EVM uses a four-layer PCB. The copper thickness was selected as 70 µm to optimize power
loss.
The small value of the output filter provides a small size and, in this case, the low height of the inductor enables
double-sided mounting.
The EVM PCB shown in 图 69 is the basis for the layout guidelines.
13.1.1 Electrical Connection of Thermal pad and Heat Sink
For the DKQ package, the heat sink connected to the thermal pad of the device should be connected to GND.
The thermal pad must not be connected to any other electrical node.
13.1.2 EMI Considerations
Automotive-level EMI performance depends on both careful integrated circuit design and good system-level
design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the
design. The design has minimal parasitic inductances because of the short leads on the package which reduces
the EMI that results from current passing from the die to the system PCB. Each channel also operates at a
different phase. The design also incorporates circuitry that optimizes output transitions that cause EMI.
For optimizing the EMI a solid ground layer plane is recommended, for a PCB design that fulfills the CISPR25
level 5 requirements, see the TAS6421-Q1 EVM layout.
13.1.3 General Guidelines
The EVM layout is optimized for low noise and EMC performance.
The TAS6421-Q1 has an exposed thermal pad that is up, away from the PCB. The layout must consider an
external heat sink.
Refer to 图 69 for the following guidelines:
•
•
•
A ground plane, A, on the same side as the device pins helps reduce EMI by providing a very-low loop
impedance for the high-frequency switching current.
The decoupling capacitors on PVDD, B, are very close to the device with the ground return close to the
ground pins.
The ground connections for the capacitors in the LC filter, C, have a direct path back to the device and also
the ground return for each channel is the shared. This direct path allows for improved common mode EMI
rejection.
•
•
The traces from the output pins to the inductors, D, should have the shortest trace possible to allow for the
smallest loop of large switching currents.
Heat-sink mounting screws, E, should be close to the device to keep the loop short from the package to
ground.
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Layout Guidelines (接下页)
•
Many vias, F, stitching together the ground planes can create a shield to isolate the amplifier and power
supply.
13.2 Layout Example
图 69. Mono Channel EVM Layout
13.3 Thermal Considerations
The thermally enhanced PowerPAD package has an exposed pad up for connection to a heat sink. The output
power of any amplifier is determined by the thermal performance of the amplifier as well as limitations placed on
it by the system, such as the ambient operating temperature. The heat sink absorbs heat from the TAS6421-Q1
and transfers it to the air. With proper thermal management this process can reach equilibrium and heat can be
continually transferred from the device. Heat sinks can be smaller than that of classic linear amplifier design
because of the excellent efficiency of class-D amplifiers. This device is intended for use with a heat sink,
therefore, RθJC is used as the thermal resistance from junction to the exposed metal package. This resistance
dominates the thermal management, so other thermal transfers are not considered. The thermal resistance of
RθJA (junction to ambient) is required to determine the full thermal solution. The thermal resistance is comprised
of the following components:
•
•
•
RθJC of the TAS6421-Q1
Thermal resistance of the thermal interface material
Thermal resistance of the heat sink
52
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Thermal Considerations (接下页)
The thermal resistance of the thermal interface material can be determined from the manufacturer’s value for the
area thermal resistance (expressed in °Cmm2/W) and the area of the exposed metal package. For example, a
typical, white, thermal grease with a 0.0254 mm (0.001 inch) thick layer is approximately 4.52°C mm2/W. The
TAS6421-Q1 in the DKQ package has an exposed area of 47.6 mm2. By dividing the area thermal resistance by
the exposed metal area determines the thermal resistance for the thermal grease. The thermal resistance of the
thermal grease is 0.094°C/W
表 38 lists the modeling parameters for one device on a heat sink. The junction temperature is assumed to be
115°C while delivering and average power of 10 watts per channel into a 4 Ω load. The thermal-grease example
previously described is used for the thermal interface material. Use 公式 3 to design the thermal system.
RθJA = RθJC + thermal interface resistance + heat sink resistance
(3)
表 38. Thermal Modeling
Description
Ambient Temperature
Value
25°C
Average Power to load
10W
Power dissipation
2W
115°C
Junction Temperature
ΔT inside package
1.8°C (0.9°C/W × 2W)
0.188°C (0.094°C/W × 2W)
44.0°C/W ([115°C – 25°C – 1.8°C – 0.188°C] / 2W)
45.1°C/W
ΔT through thermal interface material
Required heat sink thermal resistance
System thermal resistance to ambient RθJA
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14 器件和文档支持
14.1 文档支持
14.1.1 相关文档
请参阅如下相关文档：
•
•
PurePath™ Console 3 图形开发套件
《TAS6421-Q1 EVM 用户指南》（文献编号：SLOU415）
14.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
14.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 中文在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2echina.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
E2E 音频放大器论坛 TI 的音频放大器工程师对工程师 (E2E) 社区此社区的创建目的在于促进工程师之间的协作。
用户可进行实时问答。
14.4 商标
Burr-Brown, PurePath, E2E are trademarks of Texas Instruments.
14.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
14.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
54
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TAS6421QDKQRQ1
ACTIVE
HSSOP
DKQ
56
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TAS6421
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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18-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAS6421QDKQRQ1
HSSOP
DKQ
56
1000
330.0
32.4
11.35 18.67
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Oct-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HSSOP DKQ 56
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 55.0
TAS6421QDKQRQ1
1000
Pack Materials-Page 2
PACKAGE OUTLINE
DKQ0056A
PowerPADTM HSSOP - 2.475 mm max height
S
C
A
L
E
1
.
0
0
0
PLASTIC SMALL OUTLINE
C
10.67
10.03
TYP
SEATING PLANE
A
PIN 1 ID AREA
0.1 C
54X 0.635
56
1
EXPOSED
THERMAL PAD
18.54
18.29
NOTE 3
8.661
8.611
2X
17.15
5.533
5.483
28
29
0.37
56X
0.17
0.13
(2.29)
7.59
7.39
B
C A B
NOTE 4
0.25
0.13
2.29 0.05
TYP
2.475
2.240
NOTE 6
0.25
GAGE PLANE
SEE DETAIL A
0.08
0.00
1.02
0.51
0 - 8
DETAIL A
TYPICAL
4221870/D 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. The exposed thermal pad is designed to be attached to an external heatsink.
6. For clamped heatsink design, refer to overall package height above the seating plane as 2.325 +/- 0.075 and molded body
thickness dimension.
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EXAMPLE BOARD LAYOUT
DKQ0056A
PowerPADTM HSSOP - 2.475 mm max height
PLASTIC SMALL OUTLINE
56X (1.9)
SEE DETAILS
SYMM
1
56
56X (0.4)
54X (0.635)
SYMM
28
29
(R0.05) TYP
(9.5)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:6X
METAL UNDER
SOLDER MASK
SOLDER MASK
METAL
SOLDER MASK
OPENING
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MIN
AROUND
0.05 MAX
AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221870/D 01/2019
NOTES: (continued)
7. Publication IPC-7351 may have alternate designs.
8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
DKQ0056A
PowerPADTM HSSOP - 2.475 mm max height
PLASTIC SMALL OUTLINE
56X (1.9)
SYMM
1
56
56X (0.4)
54X (0.635)
SYMM
28
29
(R0.05) TYP
(9.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE:6X
4221870/D 01/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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