TB5R3LDWR [TI]
QUAD DIFFERENTIAL PECL RECEIVERS; 四通道差分PECL接收机
| 型号： | TB5R3LDWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUAD DIFFERENTIAL PECL RECEIVERS |
| 文件： | 总15页 (文件大小：627K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TB5R3
www.ti.com
SLLS643A–SEPTEMBER 2005–REVISED OCTOBER 2007
QUAD DIFFERENTIAL PECL RECEIVERS
1
FEATURES
DESCRIPTION
•
Functional Replacement for the Agere BRF1A
Pin Equivalent to General Trade 26LS32
High Input Impedance Approximately 8 kΩ
<2.6-ns Maximum Propagation Delay
•
•
•
•
•
These quad differential receivers accept digital data
over balanced transmission lines. They translate
differential input logic levels to TTL output logic
levels.
TB5R3 Provides 50-mV Hysteresis (Typical)
The TB5R3 is
replacement for the Agere systems BRF1A; it
includes 3-kV HBM and 2-kV CDM ESD protection.
a pin- and function-compatible
-1.1-V to 7.1-V Common-Mode Input Voltage
Range
•
•
•
•
Single 5-V ±10% Supply
The power-down loading characteristics of the
receiver input circuit are approximately 8 kΩ relative
to the power supplies; hence they do not load the
transmission line when the circuit is powered down.
ESD Protection HBM > 3 kV and CDM > 2 kV
Operating Temperature Range: -40°C to 85°C
Available in Gull-Wing SOIC (JEDEC MS-013,
DW) and SOIC (D) Package
The packaging for this differential line receiver is a
16-pin gull wing SOIC (DW) or a 16 pin SOIC (D).
APPLICATIONS
The enable inputs of this device include internal
pull-up resistors of approximately 40 kΩ that are
connected to VCC to ensure a logical high level input
if the inputs are open circuited.
•
Digital Data or Clock Transmission Over
Balanced Lines
FUNCTIONAL BLOCK DIAGRAM
PIN ASSIGNMENTS
AI
SOIC PACKAGE
(TOP VIEW)
AO
AI
BI
BO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AI
AI
AO
E1
BO
BI
BI
VCC
DI
DI
DO
E2
CO
CI
BI
C1
CO
C1
D1
DO
D1
E1
E2
GND
CI
Enable Truth Table
OUTPUT
CONDITION
E1
E2
0
1
0
1
0
0
1
1
Active
Active
Disabled
Active
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2007, Texas Instruments Incorporated
TB5R3
www.ti.com
SLLS643A–SEPTEMBER 2005–REVISED OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PART NUMBER(1)
TB5R3DW
PART MARKING
TB5R3
PACKAGE(2)
Gull-Wing SOIC
SOIC
LEAD FINISH
NiPdAu
STATUS
Production
Production
TB5R3D
TB5R3
NiPdAu
(1) Add the R suffix for tape and reel carrier (i.e., TB5R3DR)
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
POWER DISSIPATION RATINGS
THERMAL RESISTANCE,
JUNCTION-TO-AMBIENT
WITH NO AIR FLOW
DERATING
FACTOR(1)
CIRCUIT BOARD
MODEL
POWER RATING
A ≤ 25°C
POWER RATING
PACKAGE
T
TA = 85°C
TA ≥ 25°C
Low-K(2)
High-K(3)
Low-K(2)
High-K(3)
831 mW
1240 mW
763 mW
1190 mW
120.3°C/W
80.8°C/W
131.1°C/W
84.1°C/W
8.3 mW/°C
12.4 mW/°C
7.6 mW/°C
11.9 mW/°C
332 mW
494 mW
305 mW
475 mW
DW
D
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow.
(2) In accordance with the low-K thermal metric definitions of EIA/JESD51-3.
(3) In accordance with the high-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
PACKAGE
VALUE
53.7
UNIT
DW
D
θJB
Junction-to-Board Thermal Resistance
°C/W
47.5
DW
D
47.1
θJC
Junction-to-Case Thermal Resistance
°C/W
44.2
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
0 V to 6 V
8.4 V
Supply voltage, VCC
Magnitude of differential bus (input) voltage, |VAI - VAI|, |VBI - VBI|, |VCI - VCI|, |VDI - VDI
|
Human Body Model(2)
Charged-Device Model(3)
All pins
All pins
±3.5 kV
±2 kV
ESD
Continuous power dissipation
Storage temperature, Tstg
See Dissipation Rating Table
-65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3) Tested in accordance with JEDEC Standard 22, Test Method C101.
2
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TB5R3
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SLLS643A–SEPTEMBER 2005–REVISED OCTOBER 2007
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
Supply voltage, VCC
4.5
-1.2(1)
0.1
5
5.5
7.2
6
V
V
V
V
V
Bus pin input voltage, VAI, VAI, VBIVBI, VCI , or VCI, VDI, VDI
Magnitude of differential input voltage, |VAI - VAI|, |VBI - VBI|, |VCI - VCI|, |VDI - VDI
Low-level enable input voltage(2), VIL (VCC = 5.5 V)
High-level enable input voltage(2), VIH (VCC = 5.5 V)
Operating free-air temperature, TA
|
0.8
2
-40
85 °C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless
otherwise noted.
(2) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.
DEVICE ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
Outputs disabled
Outputs enabled
MIN TYP MAX UNIT
50
48
mA
mA
ICC
Supply current(1)
(1) Current is dc power draw as measured through GND pin and does not include power delivered to load.
RECEIVER ELECTRICAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOL
VOH
VIK
Output low voltage
Output high voltage
VCC = 4.5 V,
IOL = 8 mA
IOH = -400 µA
II = -5 mA
0.4
V
V
V
VCC = 4.5 V,
2.4
Enable input clamp voltage
VCC = 4.5 V,
-1(1)
VTH+
Positive-going differential input threshold voltage(2), (Vxl - VxI)
x = A, B, C, or D
100 mV
-
VTH-
Negative-going differential input threshold voltage(2), (Vxl - VxI)
x = A, B, C, or D
VCC = 5.5 V
mV
100(1)
VHYST Differential input threshold voltage hysteresis, (VTH+ - VTH–
)
50
mV
µA
µA
IOZL
VO = 0.4 V
VO = 2.4 V
-20(1)
20
Output off-state current, (High-Z)
IOZH
-
IOS
IIL
Output short circuit current
Enable input low current
VCC = 5.5 V
VCC = 5.5 V,
mA
µA
400(1)
-
VIN = 0.4 V
400(1)
Enable input high current
Enable input reverse current
Differential input low current
Differential input high current
VIN = 2.7 V
VIN = 5.5 V
VIN = -1.2 V
VIN = 7.2 V
20
µA
µA
IIH
VCC = 5.5 V
100
-2(1) mA
IIL
VCC = 5.5V,
VCC= 5.5V,
Output High
Output Low
IIH
1
mA
50
25
RO
Small-signal output resistance
Ω
(1) This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original
Agere data sheet.
(2) The input levels and difference voltage provide no noise immunity and should be tested only in a static, noise-free environment.
Copyright © 2005–2007, Texas Instruments Incorporated
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SLLS643A–SEPTEMBER 2005–REVISED OCTOBER 2007
SWITCHING CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
1.64
MAX UNIT
CL = 0 pF(1)
,
tPLH
tPHL
tPLH
tPHL
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
Propagation delay time, low-to-high-level output
Propagation delay time, high-to-low-level output
<2.6
ns
See Figure 2 and Figure 4
1.57
2.2
<2.6
3.5
ns
CL = 50 pF, See Figure 2 and Figure 4(2)
CL = 5 pF, See Figure 3 and Figure 5
2.1
3.5
Output disable time, high-level-to-high-impedance
output(3)
tPHZ
tPLZ
7.7
5.2
12
12
ns
ns
Output disable time, low-level-to-high-impedance
output(3)
CL = 10 pF, See Figure 2 and Figure 4
CL = 150 pF, See Figure 2 and Figure 4
0.7
4
ns
ns
tskew1
Pulse-width distortion, |tPHL - tPLH|
CL = 10 pF, TA = 75°C, See Figure 2 and
Figure 4
0.8
1.4
ns
Δtskew1p
-p
Part-to-part output waveform skew
Same part output waveform skew
CL = 10 pF, See Figure 2 and Figure 4
CL = 10 pF, See Figure 2 and Figure 4
1.5
0.3
ns
ns
Δtskew
Output enable time, high-impedance-to-high-level
output(3)
tPZH
6.9
6.3
12
12
ns
ns
CL = 10 pF, See Figure 3 and Figure 4
CL = 10 pF, See Figure 2 and Figure 4
Output enable time, high-impedance-to-low-level
output(3)
tPZL
tTLH
tTHL
Rise time (20%-80%)
Fall time (80%-20%)
1
1
ns
ns
(1) The propagation delay values with a 0 pF load are based on design and simulation.
(2) tr/tf: 3 ns (20% - 80%)
(3) See Table 1.
See Note A
See Note A
t
t
f
r
3.7 V
INPUT
INPUT
80%
20%
80%
20%
3.2 V
2.7 V
t
t
PHL
PLH
80%
V
OUTPUT
OH
80%
1.5 V
V OL
20%
t
20%
t
THL
TLH
A. tr/tf: 3 ns (20% - 80%)
Figure 1. Receiver Propagation Delay Times
4
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SLLS643A–SEPTEMBER 2005–REVISED OCTOBER 2007
E2
See
Note A
2.4 V
1.5 V
0.4 V
2.4 V
1.5 V
0.4 V
E1
See
Note B
t
t
t
t
PHZ
PZH
PLZ
PZL
V
OH
OUTPUT
0.2 V
V
OL
0.2 V
0.2 V
0.2 V
A. E2 = 1 while E1 changes states.
B. E1 = 0 while E2 changes states.
Figure 2. Receiver Enable and Disable Timing
Parametric values specified under the Electrical Characteristics and Timing Characteristics sections for the data
transmission driver devices are measured with the following output load circuits.
5 V
2 k
TO OUTPUT
OF DEVICE
UNDER TEST
DIODES TYPE
458E, 1N4148,
OR EQUIVALENT
C
5 k
L
CL includes test-fixture and probe capacitance.
Figure 3. Receiver Propagation Delay Time and Enable Time (tPZH, tPZL) Test Circuit
TO OUTPUT
OF DEVICE
W
500
1.5 V
UNDER TEST
CL
CL includes test-fixture and probe capacitance.
Figure 4. Receiver Disable Time (tPHZ, tPLZ) Test Circuit
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SLLS643A–SEPTEMBER 2005–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS
TYPICAL PROPAGATION DELAY
vs
LOAD CAPACITANCE
4
3.5
t
3
PLH
t
PHL
2.5
2
1.5
1
0.5
0
0
25
50
75 100 125 150 175 200 225
C − Load Capacitance − pF
L
NOTE: This graph is included as an aid to the system designers. Total circuit delay varies with load capacitance. The total delay is the
sum of the delay due to external capacitance and the intrinsic delay of the device. Intrinsic delay is listed in the table above as the 0
pF load condition. The incremental increase in delay between the 0 pF load condition and the actual total load capacitance
represents the extrinsic, or external delay contributed by the load.
Figure 5.
6
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SLLS643A–SEPTEMBER 2005–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (continued)
LOW-TO-HIGH PROPAGATION DELAY
HIGH-TO-LOW PROPAGATION DELAY
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.5
2.5
2
V
= 5 V
V
CC
= 5 V,
CC
Loaded per Figure 3
Loaded per Figure 3
Max
Typ
Max
2
Typ
1.5
1
1.5
1
Min
Min
0.5
0
0.5
0
−50 −25
0
25
50 75 100 125 150 175
−50 −25
0
25
50 75 100 125 150 175
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 6.
Figure 7.
MINIMUM VOH AND MAXIMUM VOL
vs
TYPICAL AND MAXIMUM ICC
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
4
50
45
V
CC
= 5.5 V
3.5
V , min
OH
V , min
OH
40
35
3
2.5
2
30
25
V , max
OL
V
= 4.5 V,
CC
Loaded per Figure 3
20
15
1.5
1
10
V
, max
OL
0.5
0
5
0
−50 −25
0
25
50 75 100 125 150 175
−50 −25
0
25
50 75 100 125 150 175
T − Junction Temperature − 5C
J
T − Junction Temperature − 5C
J
Figure 8.
Figure 9.
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SLLS643A–SEPTEMBER 2005–REVISED OCTOBER 2007
APPLICATION INFORMATION
which the device is mounted and on the airflow over
the device and PCB. JEDEC/EIA has defined
standardized test conditions for measuring θJA. Two
commonly used conditions are the low-K and the
high-K boards, covered by EIA/JESD51-3 and
EIA/JESD51-7 respectively. Figure 10 shows the
low-K and high-K values of θJA versus air flow for this
device and its package options.
Power Dissipation
The power dissipation rating, often listed as the
package dissipation rating, is a function of the
ambient temperature, TA, and the airflow around the
device. This rating correlates with the device's
maximum junction temperature, sometimes listed in
the absolute maximum ratings tables. The maximum
junction temperature accounts for the processes and
materials used to fabricate and package the device,
in addition to the desired life expectancy.
The standardized θJA values may not accurately
represent the conditions under which the device is
used. This can be due to adjacent devices acting as
heat sources or heat sinks, to nonuniform airflow, or
to the system PCB having significantly different
thermal characteristics than the standardized test
PCBs. The second method of system thermal
analysis is more accurate. This calculation uses the
power dissipation and ambient temperature, along
with two device and two system-level parameters:
There are two common approaches to estimating the
internal die junction temperature, TJ. In both of these
methods, the device internal power dissipation PD
needs to be calculated This is done by totaling the
supply power(s) to arrive at the system power
dissipation:
ǒ
Ǔ
ȍ
VSn ISn
•
•
•
•
θJC, the junction-to-case thermal resistance, in
degrees Celsius per watt
θJB, the junction-to-board thermal resistance, in
degrees Celsius per watt
θCA, the case-to-ambient thermal resistance, in
degrees Celsius per watt
θBA, the board-to-ambient thermal resistance, in
degrees Celsius per watt.
(1)
and then subtracting the total power dissipation of the
external load(s):
ȍ(
)
VLn ILn
(2)
The first TJ calculation uses the power dissipation
and ambient temperature, along with one parameter:
θJA, the junction-to-ambient thermal resistance, in
degrees Celsius per watt.
In this analysis, there are two parallel paths, one
through the case (package) to the ambient, and
another through the device to the PCB to the
ambient. The system-level junction-to-ambient
thermal impedance, θJA(S), is the equivalent parallel
impedance of the two parallel paths:
The product of PD and θJA is the junction temperature
rise above the ambient temperature. Therefore:
ǒ
Ǔ
TJ + TA ) PD qJA
(3)
140
120
100
ǒ
Ǔ
TJ + TA ) PD qJA(S)
(4)
where
D, Low−K
ǒ
Ǔ
ƫ
ƪǒ
Ǔ
qJC)qCA qJB)qBA
qJA(S)
+
ǒ
Ǔ
qJC)qCA)qJB)qBA
DW, Low−K
(5)
The device parameters θJC and θJB account for the
internal structure of the device. The system-level
parameters θCA and θBA take into account details of
the PCB construction, adjacent electrical and
mechanical components, and the environmental
conditions including airflow. Finite element (FE), finite
difference (FD), or computational fluid dynamics
(CFD) programs can determine θCA and θBA. Details
on using these programs are beyond the scope of
this data sheet, but are available from the software
manufacturers.
80
DW, High−K
D, High−K
60
40
0
100
200
300
400
500
Figure 10. Thermal Impedance vs Air Flow
Note that θJA is highly dependent on the PCB on
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2007
PACKAGING INFORMATION
Orderable Device
TB5R3D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TB5R3DG4
TB5R3DR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TB5R3DRG4
TB5R3DW
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
DW
DW
DW
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TB5R3DWG4
TB5R3DWR
TB5R3DWRG4
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TB5R3LD
TB5R3LDR
TB5R3LDW
TB5R3LDWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
16
16
16
16
40
2500
40
TBD
TBD
TBD
TBD
CU SNPB
CU SNPB
CU SNPB
CU SNPB
Level-1-220C-UNLIM
Level-1-220C-UNLIM
Level-1-220C-UNLIM
Level-1-220C-UNLIM
DW
DW
2000
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TB5R3DR
SOIC
SOIC
D
16
16
2500
2000
330.0
330.0
16.4
16.4
6.5
10.3
10.7
2.1
2.7
8.0
16.0
16.0
Q1
Q1
TB5R3DWR
DW
10.75
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TB5R3DR
SOIC
SOIC
D
16
16
2500
2000
346.0
346.0
346.0
346.0
33.0
33.0
TB5R3DWR
DW
Pack Materials-Page 2
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
Logic
Military
Power Mgmt
Microcontrollers
RFID
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
RF/IF and ZigBee® Solutions www.ti.com/lprf
www.ti.com/wireless
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