TCA9416_V03 [TI]

TCA9416 Ultra-Low-Voltage I2C Translator with Rise Time Accelerators;
TCA9416_V03
型号: TCA9416_V03
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
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TCA9416 Ultra-Low-Voltage I2C Translator with Rise Time Accelerators

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TCA9416  
SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021  
TCA9416 Ultra-Low-Voltage I2C Translator with Rise Time Accelerators  
1 Features  
3 Description  
2-bit bidirectional translator for SDA and SCL lines  
in I2C applications  
Provides bidirectional voltage translation with no  
direction pin  
High-impedance output SCL_A, SDA_A, SCL_B,  
SDA_B pins when OE = 0 V or VCC = 0 V  
Internal 10-kΩ pull-up resistor on all SDA and SCL  
pins are enabled based on respective VCC voltage  
1.08 V to 3.6 V on both A and B ports  
VCC Isolation feature: If either VCC input is at  
GND, both ports are in the high-impedance state  
(excluding pull-ups)  
The TCA9416 is a 2-bit bidirectional I2C and SMBus  
voltage-level translator with an output enable (OE)  
input and rising and falling edge accelerators. It is  
operational from 1.08 V to 3.6 V on both the A-  
side and B-side. This allows the device to interface  
between lower and higher logic signal levels at any of  
the typical 1.2-V, 1.8-V, 2.5-V, and 3.3-V supply rails.  
The OE input pin is referenced to VCCA, can be  
tied directly to VCCA, but it is also 3.6-V tolerant.  
The OE pin can also be controlled and set to a  
logic low to place all the SCL and SDA pins in a  
high-impedance state, which significantly reduces the  
quiescent current consumption.  
No power-supply sequencing required: either VCCA  
or VCCB can be ramped first  
Low Ioff of 2.5 µA when either VCCA or VCCB = 0 V  
OE input can be tied directly to VCCA or controlled  
by GPIO  
Latch-up performance exceeds 100 mA per JESD  
78, class II  
ESD Protection exceeds JESD 22  
– 2500-V Human-body model (A114-B)  
– 1500-V Charged-device model (C101)  
Under normal I2C and SMBus configurations, the  
TCA9416 is compatible with standard speeds where  
the frequency of SCL is 100 kHz (Standard-mode),  
400 kHz (Fast-mode), or 1 MHz (Fast-mode Plus).  
The TCA9416 features internal 10-kΩ pull-up resistors  
on SCL_A, SDA_A, SCL_B, and SDA_B. Additional  
external pull-up resistors can be added to the bus to  
reduce the total pull-up resistance and speed up rising  
edges.  
2 Applications  
Device Information  
Wearables  
Personal electronics  
Servers  
PART NUMBER  
TCA9416  
PACKAGE(1)  
BODY SIZE (NOM)  
1.35 mm × 0.80 mm  
2.9 mm × 1.6 mm  
X2SON (8)  
SOT-23-T (8)  
(1) For all available packages, see the orderable addendum at  
the end of the datasheet.  
spacer  
Typical Application Block Diagram for TCA9416  
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
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SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021  
Table of Contents  
1 Features............................................................................1  
2 Applications.....................................................................1  
3 Description.......................................................................1  
4 Revision History.............................................................. 2  
5 Pin Configuration and Functions...................................3  
6 Specifications.................................................................. 4  
6.1 Absolute Maximum Ratings ....................................... 4  
6.2 ESD Ratings .............................................................. 4  
6.3 Recommended Operating Conditions ........................5  
6.4 Thermal Information ...................................................5  
6.5 Electrical Characteristics ............................................6  
6.6 Timing Requirements .................................................7  
6.7 Switching Characteristics ...........................................8  
6.8 Typical Characteristics................................................9  
7 Parameter Measurement Information..........................10  
7.1 Voltage Waveforms................................................... 11  
8 Detailed Description......................................................12  
8.1 Overview...................................................................12  
8.2 Functional Block Diagram.........................................12  
8.3 Feature Description...................................................12  
8.4 Device Functional Modes..........................................14  
9 Application and Implementation..................................15  
9.1 Application Information............................................. 15  
9.2 Typical Application.................................................... 15  
10 Power Supply Recommendations..............................17  
11 Layout...........................................................................18  
11.1 Layout Guidelines................................................... 18  
11.2 Layout Example...................................................... 18  
12 Device and Documentation Support..........................19  
12.1 Receiving Notification of Documentation Updates..19  
12.2 Support Resources................................................. 19  
12.3 Trademarks.............................................................19  
12.4 Electrostatic Discharge Caution..............................19  
12.5 Glossary..................................................................19  
4 Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision * (February 2021) to Revision A (August 2021)  
Page  
Changed the document status from: Advanced Information to: Production data............................................... 1  
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SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021  
5 Pin Configuration and Functions  
SCL_A  
1
7
6
5
SCL_B  
SCL_A  
OE  
1
2
3
4
8
7
6
5
SCL_B  
VCCB  
GND  
8
VCCA  
SDA_A  
OE  
SDA_B  
VCCA  
2
VCCB  
Not to scale  
4
Figure 5-2. 8-PIN DDF, (Top View)  
GND  
SDA_A  
3
SDA_B  
Not to scale  
Figure 5-1. 8-PIN DTM, (Top View)  
Table 5-1. Pin Functions  
PIN  
TYPE  
DESCRIPTION  
NAME  
SCL_A  
VCCA  
SDA_A  
GND  
DTM  
DDF  
1
2
3
4
5
6
7
1
3
4
6
5
7
8
I/O  
Power  
I/O  
Input/output A. Referenced to VCCA  
.
A-port supply voltage. 1.08 V ≤ VCCA ≤ 3.6 V  
Input/output A. Referenced to VCCA  
Ground  
.
GND  
I/O  
SDA_B  
VCCB  
SCL_B  
Input/output B. Referenced to VCCB  
.
Power  
I/O  
B-port supply voltage. 1.08 V ≤ VCCB ≤ 3.6 V  
Input/output B. Referenced to VCCB  
Output enable (active High). Pull OE low to place all outputs in 3-state mode.  
Referenced to VCCA  
.
OE  
8
2
Input  
.
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6 Specifications  
6.1 Absolute Maximum Ratings  
over recommended operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
–0.5  
MAX  
UNIT  
V
VCCA  
VCCB  
Supply voltage range  
Supply voltage range  
4
4
V
A port  
B port  
A port  
B port  
A port  
B port  
VI < 0  
VO < 0  
4
VI  
Input voltage range(1)  
V
V
V
4
4
Voltage range applied to any output  
VO  
VO  
in the high-impedance or power-off state(1)  
4
4
Voltage range applied to any output in the high or low state(1) (2)  
4
IIK  
IOK  
IO  
Input clamp current  
–50  
–50  
±50  
±100  
150  
mA  
mA  
mA  
mA  
°C  
Output clamp current  
Continuous output current  
Continuous current through VCCA, VCCB, or GND  
Storage temperature  
Tstg  
–65  
(1) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.  
(2) The value of VCCA and VCCB are provided in the recommended operating conditions table.  
6.2 ESD Ratings  
VALUE  
±2500  
UNIT  
A-Ports, B-Ports  
VCCA, VCCB, OE  
V
V
V
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)  
V(ESD)  
Electrostatic discharge  
±2000  
±1000  
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
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6.3 Recommended Operating Conditions  
over recommended operating free-air temperature range (unless otherwise noted)  
VCCA  
VCCB  
MIN  
1.08  
1.08  
MAX  
3.6  
UNIT  
V
VCCA  
VCCB  
Supply voltage  
Supply voltage  
3.6  
V
A-port I/Os, B-port  
I/Os, OE  
VI  
Input voltage  
0 V to 3.6 V  
0 V to 3.6 V  
0
3.6  
3.6  
V
V
High-level  
input voltage  
VIH  
OE input  
OE input  
1.08 V to 3.6 V  
1.08 V to 3.6 V  
1.08 V to 3.6 V  
1.08 V to 3.6 V  
VCCA × 0.65  
Low-level  
input voltage  
VIL  
TA  
0
VCCA × 0.35  
125  
V
Operating free-air temperature  
–40  
°C  
6.4 Thermal Information  
TCA9416  
TCA9416  
THERMAL METRIC(1)  
DDF  
8 PINS  
177.6  
98.7  
DTM  
8 PINS  
212.5  
105.3  
124.1  
4.5  
UNIT  
RθJA  
RθJC(top)  
RθJB  
ψJT  
Junction-to-ambient thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
97.8  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
12.2  
ψJB  
97.2  
23.8  
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application  
report.  
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SCPS238A – FEBRUARY 2021 – REVISED AUGUST 2021  
6.5 Electrical Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
TEST  
CONDITIONS  
PARAMETER  
VCCA  
VCCB  
MIN  
0.65  
0.6  
TYP  
0.9  
MAX  
UNIT  
VUVLO_RIS UVLO Rising  
VUVLO for VCCA and  
VCCB are independent  
0 V to 3.6 V  
0 V to 3.6 V  
1
V
V
V
V
Threshold  
E
VUVLO_FAL UVLO Falling  
VUVLO for VCCA and  
VCCB are independent  
0 V to 3.6 V  
0 V to 3.6 V  
0.85  
0.95  
Threshold  
L
RTA(2) Activation  
Threshold  
VCCI  
×
VCCI  
×
(1)  
VRTA  
1.08 V to 3.6 V  
1.08 V to 3.6 V  
1.08 V to 3.6 V  
1.08 V to 3.6 V  
0.30  
0.45  
FTA(2) Activation  
Threshold  
VCCI  
×
VCCI  
×
(1)  
VFTA  
0.60  
0.70  
RPU  
VI = 0.15 V  
1.08V to 3.6V  
1.08 V to 3.6 V  
1.08 V to 3.6 V  
1.08V to 3.6V  
1.08 V to 3.6 V  
1.08 V to 3.6 V  
7.5  
10  
±0.1  
0
12.5  
±1  
kΩ  
μA  
μA  
II  
OE  
VI = VCCA or GND  
OE less than VIL  
IOZ  
A or B port  
±2.5  
VI = 3.6 V, VO = 0  
V (TA ≤ 85 C)  
A port  
B port  
A port  
B port  
0 V  
0 V to 3.6 V  
0 V  
±0.1  
±0.1  
±0.1  
±0.1  
±0.5  
±0.5  
±2.5  
±2.5  
VI = 3.6 V, VO = 0  
V (TA ≤ 85 C)  
0 to 3.6 V  
0 V  
Ioff  
μA  
VI = 3.6 V, VO = 0  
V (TA ≤ 125 C)  
0 V to 3.6 V  
0 V  
VI = 3.6 V, VO = 0  
V (TA ≤ 125 C)  
0 to 3.6 V  
VI = VO = open,  
IO = 0,  
OE = 0 V  
VCCA  
VCCB  
4
3
13  
13  
ICC_OFF  
1.08 V to 3.6 V  
1.08 V to 3.6 V  
μA  
μA  
VI = VO = open,  
IO = 0,  
OE = 0 V  
1.32 V  
1.32 V to 3.6 V  
1.32 V to 3.6 V  
1.32 V to 3.6 V  
1.32 V to 3.6 V  
0 V  
3
4
6
10  
14  
1.98 V  
VI = VO = open,  
IO = 0,  
OE = VCCA  
ICCA  
3.6 V  
6
0 V  
-0.5  
-0.5  
0
1.32 V to 3.6 V  
1.32 V to 3.6 V  
1.32 V to 3.6 V  
1.32 V to 3.6 V  
1.32 V to 3.6 V  
0 V  
3
12  
6
1.32 V  
1.5  
2
1.98 V  
8
VI = VO = open,  
IO = 0,  
OE = VCCA  
ICCB  
3.6 V  
5
12  
μA  
μA  
0 V  
0
1.32 V to 3.6 V  
1.32 V  
1
7
12  
15  
23  
50  
50  
25  
55  
25  
15  
4
1.32 V  
4
VI = VO = open,  
IO = 0,  
OE = VCCA  
ICCA + ICCB  
1.98 V  
1.98 V  
6
3.6 V  
3.6 V  
11  
28  
28  
15  
30  
15  
10  
2.5  
7
VI = 0.2 V, IO = 2 mA  
VI = 0.2 V, IO = 2 mA  
VI = 0.2 V, IO = 3 mA  
VI = 0.2 V, IO = 2 mA  
VI = 0.2 V, IO = 3 mA  
VI = 0.2 V, IO = 6 mA  
1.08 V  
1.08 V  
1.08 V, 1.8 V  
1.65 V  
1.8 V, 1.08 V  
1.65 V  
Ron  
1.08 V, 3.0 V  
1.65 V, 3.0 V  
3.0 V  
3.0 V, 1.08 V  
3.0 V, 1.65 V  
3.0 V  
CI  
OE  
3.3 V  
3.3 V  
pF  
pF  
Cio  
A or B port  
0 V, 1.08 V, 3.6 V  
0 V, 1.08 V, 3.6 V  
10  
(1) VCCI is the VCC associated with the input port.  
(2) RTA is "rise time accelerator" and FTA is "fall time accelerator"  
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6.6 Timing Requirements  
over operating free-air temperature range (unless otherwise noted). Typical specifications are at TA = 25 °C, VCC = 3.3 V,  
unless otherwise noted.  
PARAMETER  
TEST CONDITIONS  
SDA,SCL = Hi-Z  
MIN  
TYP  
MAX  
UNIT  
tRTA  
Time from VRTA to RTA disabling  
80  
210  
ns  
EN = VCC  
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6.7 Switching Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
TEST CONDITIONS  
VCCA = 1.08 V  
MIN  
TYP  
MAX  
UNIT  
17  
10  
7
30  
20  
25  
23  
25  
20  
20  
20  
30  
20  
25  
23  
25  
20  
20  
20  
8
VCCA = 1.8 V  
VCCA = 2.5 V  
VCCA = 3.6 V  
VCCA = 1.08 V  
VCCA = 1.8 V  
VCCA = 2.5 V  
VCCA = 3.6 V  
VCCB = 1.08 V  
VCCB = 1.8 V  
VCCB = 2.5 V  
VCCB = 3.6 V  
VCCB = 1.08 V  
VCCB = 1.8 V  
VCCB = 2.5 V  
VCCB = 3.6 V  
tPHL  
tPLH  
tPHL  
tPLH  
A
A
B
B
B
B
A
A
ns  
6
9
5
ns  
ns  
ns  
4
2
17  
10  
7
6
9
5
4
2
tSK(O)-RISE  
tSK(O)-FALL  
ten  
Rising Channel-to-channel skew (Propagation)  
Falling Channel-to-channel skew (Propagation)  
ns  
ns  
ns  
ns  
8
OE  
OE  
A or B  
A or B  
70  
60  
18  
12  
11  
10  
18  
12  
11  
10  
13  
12  
12  
11  
13  
12  
12  
11  
350  
160  
35  
30  
25  
25  
35  
30  
25  
25  
30  
30  
35  
40  
30  
30  
35  
40  
tdis  
VCCA = 1.08 V  
VCCA = 1.8 V  
VCCA = 2.5 V  
VCCA = 3.6 V  
VCCB = 1.08 V  
VCCB = 1.8 V  
VCCB = 2.5 V  
VCCB = 3.6 V  
VCCA = 1.08 V  
VCCA = 1.8 V  
VCCA = 2.5 V  
VCCA = 3.6 V  
VCCB = 1.08 V  
VCCB = 1.8 V  
VCCB = 2.5 V  
VCCB = 3.6 V  
trA  
trB  
tfA  
tfB  
B-port  
A-port  
B-port  
A-port  
A-port  
B-port  
A-port  
B-port  
ns  
ns  
ns  
ns  
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6.8 Typical Characteristics  
35  
9
8
7
6
5
4
3
2
-40 C  
25 C  
125 C  
-40 C  
25 C  
125 C  
30  
25  
20  
15  
10  
5
1
1.2 1.4 1.6 1.8  
2
2.2 2.4 2.6 2.8  
3
1
1.5  
2
2.5  
3
3.5  
4
Min(VCCA, VCCB) (V)  
VCCA (V)  
The Min(VCCA, VCCB) signifies that the lower voltage of VCCA or  
VCCB is used. As an example, if VCCA = 1.8 V and VCCB = 3.3 V,  
then the Min(VCCA, VCCB) is 1.8 V.  
Figure 6-2. ICCA (μA) vs VCCA (V)  
Figure 6-1. RON (Ω) vs Min(VCCA, VCCB) (V)  
7
-40 C  
25 C  
125 C  
6
5
4
3
2
1
1
1.5  
2
2.5  
3
3.5  
4
VCCB (V)  
Figure 6-3. ICCB (μA) vs VCCB (V)  
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7 Parameter Measurement Information  
VCC  
VCC  
RL  
(see Note A)  
VIN  
VOUT  
S1  
PULSE  
DUT  
GND  
GENERATOR  
R
T
C = 57 pF  
L
(see Note B)  
(see Note C)  
TEST  
tPLZ/tPZL  
S1  
VCC  
TEST CIRCUIT FOR OPEN-DRAIN OUTPUT  
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Figure 7-1. Load Circuit for Pulse Duration, Propagation Delay, Output Rise-Time and Fall-Time  
Measurement  
1. RL = 1.35 kΩ  
2. RT termination resistance should be equal to ZOUT of pulse generators.  
3. CL includes probe and jig capacitance. CL = 50 pF when on the B-side.  
4. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,  
slew rate ≥ 1 V/ns.  
5. tPLZ and tPHZ are the same as tdis.  
6. tPZL and tPZH are the same as ten.  
7. VCCI is the VCC associated with the input port.  
8. VCCO is the VCC associated with the output port.  
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7.1 Voltage Waveforms  
VCCI  
Input  
VCCI / 2  
VCCI / 2  
0 V  
tPLH  
tPHL  
VOH  
0.9 × VCCO  
0.1 × VCCO  
VCCO / 2  
tr  
Output  
VCCO / 2  
VOL  
tf  
Figure 7-2. Propagation Delay Times  
spacer  
VCCA  
VCCA / 2  
VCCA / 2  
OE input  
0 V  
tPLZ  
tPZL  
VOH  
Output  
Waveform 1  
S1 at 2 × VCCO  
VCCO / 2  
VCCO× 0.1  
VOL  
(see Note 2)  
tPHZ  
tPZH  
VOH  
0 V  
Output  
Waveform 2  
S1 at GND  
VCCO× 0.9  
VCCO / 2  
(see Note 2)  
1. CL includes probe and jig capacitance.  
2. Waveform 1 in Figure 7-3 is for an output with internal such that the output is high, except when OE is high (see Figure 7-1).  
Waveform 2 in Figure 7-3 is for an output with conditions such that the output is low, except when OE is high.  
3. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.  
4. The outputs are measured one at a time, with one transition per measurement.  
5. tPLZ and tPHZ are the same as tdis  
.
6. tPZL and tPZH are the same as ten  
.
7. tPLH and tPHL are the same as tpd  
.
8. VCCI is the VCC associated with the input port.  
9. VCCO is the VCC associated with the output port.  
Figure 7-3. Enable and Disable Times  
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8 Detailed Description  
8.1 Overview  
The TCA9416 device is a directionless voltage-level translator specifically designed for translating logic voltage  
levels. The A and B ports are able to accept I/O voltages ranging from 1.08 V to 3.6 V. The device is a pass-gate  
architecture with edge-rate accelerators (one-shots) to improve the overall data rate. 10-kΩ pull up resistors,  
commonly used in open-drain applications, have been conveniently integrated so that an external resistor is not  
needed. When TCA9416 is disabled the one shots are also disabled, but the internal pull ups are still enabled.  
Pull up resistors are gated on the supply voltage. When supply is above UVLO, the pull up resistor for that  
specific side (A vs B) is enabled.  
8.2 Functional Block Diagram  
VCCA  
VCCB  
Gate Bias  
Generator  
OE  
Rise/Fall  
Rise/Fall  
Accelerator  
Accelerator  
10 k  
10 k  
SCL_A  
SCL_B  
Rise/Fall  
Rise/Fall  
Accelerator  
Accelerator  
10 k  
10 k  
SDA_A  
SDA_B  
8.3 Feature Description  
8.3.1 Architecture  
The TCA9416 architecture (see Figure 8-1) is an auto-direction-sensing based translator that does not require a  
direction-control signal to control the direction of data flow from A to B or from B to A.  
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VCCA  
VCCB  
Gate Bias  
Generator  
Rise Time  
Logic  
Rise Time  
10 k  
10 k  
Logic  
A
B
Fall Time  
Logic  
Fall Time  
Logic  
VCCA  
VCCB  
Figure 8-1. Architecture of a TCA9416 Cell  
These two bidirectional channels support both directions of data flow without a direction-control signal. By  
properly biasing the gate of the pass-FET, the FET can turn on (low RDSON), when either side input voltage drops  
to ~ 1 voltage threshold below the lowest of the two supplies.  
The TCA9416 is part of the TI "Switch" type voltage translator family and employs key circuits to enable this  
voltage translation:  
1. An N-channel pass-gate transistor topology that ties the A-port to the B-port.  
2. Output rise time accelerator circuitry to detect and accelerate rising edges on the A or B ports  
3. Output fall time accelerator circuitry to detect and accelerate falling edges on the A or B ports  
For bidirectional voltage translation, pull up resistors are included on the device for dc current sourcing  
capability. The VGATE gate bias of the N-channel pass transistor is set to the lower supply voltage and can  
be represented with MIN(VCCA, VCCB).  
The rise and fall time accelerator (RTA and FTA, respectively) circuitry speeds up the output slew rate by  
monitoring the input edge for transitions, helping maintain the data rate through the device. During a low-to-high  
signal rising edge, the rise time accelerator (RTA) circuit turns on to increase the current drive capability of  
the driver. This edge-rate acceleration provides high ac drive by bypassing the internal 10-kΩ pull up resistors  
during the low-to-high transition to speed up the signal. The output resistance of the driver is decreased to  
approximately 150 Ω during this acceleration phase. During a high-to-low signal falling edge, the fall time  
accelerator (FTA) turns on to increase the current drive capability of the driver, similar to the rise time  
accelerator. This helps reduce the fall time for large capacitive loads. For light capacitive loads, the fall time  
accelerator will not enable.  
Both the rise and fall time accelerators have logic to control the rate at which they turn on and off, in order to  
reduce ringing and over/undershoots.  
8.3.2 Enable and Disable  
The TCA9416 has an OE input that is used to disable the device by setting OE low, which prevents any signals  
from propagating across the device. This pin is referenced to the VCCA supply. The rise and fall time accelerators  
are also disabled. Note that the internal pull up resistors will still be enabled if the supply is above VUVLO. The  
disable time (tdis) indicates the delay between the time when OE goes low and when the outputs are disabled  
(Hi-Z). The enable time (ten) indicates the amount of time the user must allow for the one-shot circuitry to  
become operational after OE is taken high.  
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8.3.3 Pull up resistors on I/O Lines  
Each A-port I/O has an internal 10-kΩ pull up resistor to VCCA, and each B-port I/O has an internal 10-kΩ pull  
up resistor to VCCB. If a smaller value of pull up resistor is required, an external resistor must be added from  
the I/O to VCCA or VCCB (in parallel with the internal 10-kΩ resistors). However, adding lower value pull up  
resistors effects VOL levels. It is recommended not to go below 1.5-kΩ. The internal pull ups of the TCA9416  
are controlled by their respective supplies. The resistors have back-biasing protection, so that if a supply is off,  
the current cannot flow through the resistors back into the supply. If a supply is above VUVLO_RISE, the pull up  
resistor for its side is enabled.  
8.4 Device Functional Modes  
The TCA9416 device has two functional modes, enabled and disabled. To disable the device set the OE input  
low, which disables the rise time and fall time accelerators, and prevents signals from propagating across the  
channels. The internal pull up resistors are not affected by the OE input. Setting the OE input high enables the  
device.  
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9 Application and Implementation  
Note  
Information in the following applications sections is not part of the TI component specification,  
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for  
determining suitability of components for their purposes, as well as validating and testing their design  
implementation to confirm system functionality.  
9.1 Application Information  
The TCA9416 can be used to bridge the digital-switching compatibility gap between two voltage nodes to  
successfully interface logic threshold levels found in electronic systems. It should be used in a point-to-point  
topology for interfacing devices or systems operating at different interface voltages with one another. The  
primary target application use is for interfacing with open-drain drivers on the data I/Os such as I2C or SMBus,  
where the data is bidirectional and no control signal is available.  
9.2 Typical Application  
Optional Resistors  
1.8 V  
3.3 V  
0.1 F  
VCCA  
V
CCB
SDA_A  
SCL_A  
SDA_B  
SCL_B  
Controller  
I2C  
Bus  
Devices  
I2C  
Bus  
OE  
OE is referenced to VCCA  
Figure 9-1. Typical Application Circuit  
9.2.1 Design Requirements  
For this design example, use the parameters listed in Table 9-1.  
Table 9-1. Design Parameters  
DESIGN PARAMETER  
EXAMPLE VALUE  
Input voltage range  
1.08 to 3.6 V  
Output voltage range  
1.08 to 3.6 V  
9.2.2 Detailed Design Procedure  
To begin the design process, determine the following:  
Input voltage range  
– Use the supply voltage of the device that is driving the TCA9416 device to determine the input voltage  
range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low, the  
value must be less than the VIL of the input port.  
Output voltage range  
– Use the supply voltage of the device that the TCA9416 device is driving to determine the output voltage  
range  
– The TCA9416 device has 10-kΩ internal pull up resistors. External pull up resistors can be added to  
reduce the total RC of a signal trace if necessary.  
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9.2.2.1 Startup Considerations with Large Capacitive Load Mismatches  
Due to the FET based architecture of this translator, there are some considerations a system designer must  
be aware of during powering up with large differences in capacitance between the sides. If one supply with  
smaller capacitance is already powered up, and the other is ramping (with OE pin high), the side with the heavier  
load can ramp slower than the power supply ramp, due to only having an internal 10kΩ pull up resistor. In this  
situation, once the rising POR threshold is met, the device enables all circuitry. If the heavy capacitance side  
has not yet risen above about 70% of supply, the device determines this as low, and briefly turns on the fall time  
accelerators to propagate a low. Once the fall time accelerator has timed out, the signals rise and sit idle high.  
This phenomenon can be eliminated by holding the OE pin low (disabled) until all supplies and busses have  
ramped up, since this explicitly disables the bus acceleration circuitry until the bus has completed power up.  
Slower supply ramps also help reduce this since the bus voltage follows the supply closer if the ramp is slow.  
9.2.3 Application Curve  
Figure 9-2. Level-Translation of a 1-MHz Signal  
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10 Power Supply Recommendations  
The TCA9416 has no supply restrictions outside of the 1.08 V to 3.6 V range. VCCA can be higher than or lower  
than VCCB. The internal circuitry will select the appropriate supply automatically to correctly support translation.  
VCCA can also be the same as VCCB, and the device can be used as a buffer.  
The sequencing of each power supply does not damage the device during the power up operation, so either  
power supply can be ramped up first. The output-enable (OE) input circuit is designed so that when the (OE)  
input is low, the outputs are disabled. No signals may propagate, and the rise time and fall time accelerators are  
disabled, but the internal pull up resistors will remain unaffected. To make sure the signals do not pass through  
during power up or power down, the OE input pin must be tied to GND through a pull down resistor and should  
not be enabled until VCCA and VCCB are fully ramped and stable. If OE is tied to VCCA, this is OK, but might result  
in a glitch on the bus during power up depending on the capacitive load and ramp rates. The minimum value of  
the pull down resistor to ground is determined by the current-sourcing capability of the driver.  
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11 Layout  
11.1 Layout Guidelines  
For reliability of the device, the following common printed-circuit board layout guidelines are recommended:  
1. Bypass capacitors should be used on power supplies and should be placed as close as possible to the  
VCCA, VCCB pin, and GND pin.  
2. Short trace lengths should be used to avoid excessive loading.  
3. Keep SCL and SDA lengths close to prevent skewing the signals.  
4. PCB signal trace-lengths must be kept short enough so that the round-trip delay of any reflection is less than  
the one-shot duration, approximately 30 ns. Making sure that any reflection encounters low impedance at the  
source driver.  
11.2 Layout Example  
SCL_A  
OE  
SCL_B  
VCCB  
GND  
To MCU  
GND  
VCCB  
GND  
CAP  
TCA9416  
CAP  
VCCA  
SDA_A  
VCCA  
SDA_B  
Figure 11-1. TCA9416 Layout Example (DDF)  
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12 Device and Documentation Support  
12.1 Receiving Notification of Documentation Updates  
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on  
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For  
change details, review the revision history included in any revised document.  
12.2 Support Resources  
TI E2Esupport forums are an engineer's go-to source for fast, verified answers and design help — straight  
from the experts. Search existing answers or ask your own question to get the quick design help you need.  
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do  
not necessarily reflect TI's views; see TI's Terms of Use.  
12.3 Trademarks  
TI E2Eis a trademark of Texas Instruments.  
All trademarks are the property of their respective owners.  
12.4 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
12.5 Glossary  
TI Glossary  
This glossary lists and explains terms, acronyms, and definitions.  
Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
5-Dec-2021  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TCA9416DDFR  
TCA9416DTMR  
ACTIVE SOT-23-THIN  
DDF  
DTM  
8
8
3000 RoHS & Green  
NIPDAU  
Level-1-260C-UNLIM  
-40 to 125  
-40 to 125  
2JGF  
LC  
ACTIVE  
X2SON  
5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
5-Dec-2021  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
6-Dec-2021  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TCA9416DDFR  
SOT-  
DDF  
8
3000  
180.0  
8.4  
3.2  
3.2  
1.4  
4.0  
8.0  
Q3  
23-THIN  
TCA9416DTMR  
TCA9416DTMR  
X2SON  
X2SON  
DTM  
DTM  
8
8
5000  
5000  
180.0  
178.0  
9.5  
8.4  
0.93  
0.93  
1.49  
1.49  
0.43  
0.43  
2.0  
2.0  
8.0  
8.0  
Q1  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
6-Dec-2021  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TCA9416DDFR  
TCA9416DTMR  
TCA9416DTMR  
SOT-23-THIN  
X2SON  
DDF  
DTM  
DTM  
8
8
8
3000  
5000  
5000  
210.0  
189.0  
205.0  
185.0  
185.0  
200.0  
35.0  
36.0  
33.0  
X2SON  
Pack Materials-Page 2  
PACKAGE OUTLINE  
DDF0008A  
SOT-23 - 1.1 mm max height  
S
C
A
L
E
4
.
0
0
0
PLASTIC SMALL OUTLINE  
C
2.95  
2.65  
SEATING PLANE  
TYP  
PIN 1 ID  
AREA  
0.1 C  
A
6X 0.65  
8
1
2.95  
2.85  
NOTE 3  
2X  
1.95  
4
5
0.4  
0.2  
8X  
0.1  
C A  
B
1.65  
1.55  
B
1.1 MAX  
0.20  
0.08  
TYP  
SEE DETAIL A  
0.25  
GAGE PLANE  
0.1  
0.0  
0 - 8  
0.6  
0.3  
DETAIL A  
TYPICAL  
4222047/B 11/2015  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm per side.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DDF0008A  
SOT-23 - 1.1 mm max height  
PLASTIC SMALL OUTLINE  
8X (1.05)  
SYMM  
1
8
8X (0.45)  
SYMM  
6X (0.65)  
5
4
(R0.05)  
TYP  
(2.6)  
LAND PATTERN EXAMPLE  
SCALE:15X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4222047/B 11/2015  
NOTES: (continued)  
4. Publication IPC-7351 may have alternate designs.  
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DDF0008A  
SOT-23 - 1.1 mm max height  
PLASTIC SMALL OUTLINE  
8X (1.05)  
SYMM  
(R0.05) TYP  
8
1
8X (0.45)  
SYMM  
6X (0.65)  
5
4
(2.6)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:15X  
4222047/B 11/2015  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
7. Board assembly site may have different recommendations for stencil design.  
www.ti.com  
PACKAGE OUTLINE  
DTM0008A  
X2SON - 0.4 mm max height  
S
C
A
L
E
1
2
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD  
0.85  
0.75  
A
B
PIN 1 INDEX AREA  
1.4  
1.3  
C
0.4 MAX  
SEATING PLANE  
0.05 C  
0.04  
0.00  
SYMM  
(0.102) TYP  
5
3
0.27  
0.17  
2X  
4
2X  
1
SYMM  
0.54  
2
1
6
7
4X  
8
0.5  
0.25  
0.15  
6X  
PIN 1 ID  
0.27  
0.17  
6X  
0.1  
C B A  
C
0.05  
4224755/A 01/2019  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. The package thermal pad(s) must be soldered to the printed circuit board for thermal and mechanical performance.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DTM0008A  
X2SON - 0.4 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
6X (0.42)  
6X (0.2)  
(
0.22)  
1
7
8
(0.27)  
SYMM  
(45 X 0.75)  
(0.5)  
4
5
3
(45 X 0.1)  
(R0.05) TYP  
SYMM  
(0.78)  
SEE SOLDER MASK  
DETAILS  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:40X  
0.0325 MIN  
ALL AROUND  
0.0325 MAX  
ALL AROUND  
EXPOSED METAL  
EXPOSED METAL  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
SOLDER MASK  
OPENING  
METAL EDGE  
SOLDER MASK  
DEFINED  
(PREFERRED)  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4224755/A 01/2019  
NOTES: (continued)  
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature  
number SLUA271 (www.ti.com/lit/slua271).  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DTM0008A  
X2SON - 0.4 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
(0.2) TYP  
4X (0.42)  
(
0.22)  
7
6X (0.2)  
(0.411)  
1
8
(0.27)  
SYMM  
(0.5)  
4
5
3
EXPOSED  
METAL  
SYMM  
(R0.05) TYP  
(0.78)  
PINS: 1,3,5,7  
SOLDER PASTE EXAMPLE  
BASED ON 0.075 mm THICK STENCIL  
SCALE: 40X  
4224755/A 01/2019  
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
www.ti.com  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, regulatory or other requirements.  
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an  
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TI

TCA9509DGKR

LEVEL-TRANSLATING I2C/SMBUS BUS REPEATER

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TI

TCA9509MRVHR

具有内部 1mA 拉电流的 2 位电平转换 400kHz I2C/SMBus 缓冲器/中继器 | RVH | 8 | -40 to 85

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TI

TCA9509RVHR

LEVEL-TRANSLATING I2C/SMBUS BUS REPEATER

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TI

TCA9509_13

LEVEL-TRANSLATING I2C/SMBUS BUS REPEATER

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TI

TCA9511A

2 位双向 2.3V 至 5.5V 热插拔 400kHz I2C/SMBus 缓冲器

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TI

TCA9511ADGKR

2 位双向 2.3V 至 5.5V 热插拔 400kHz I2C/SMBus 缓冲器 | DGK | 8 | -40 to 125

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TI

TCA9517

LEVEL-TRANSLATING I2C BUS REPEATER

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TI

TCA9517-Q1

具有断电高阻抗的汽车类 2 位电平转换 400kHz I2C/SMBus 缓冲器/中继器

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TI

TCA9517A

LEVEL-TRANSLATING I2C BUS REPEATER

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TI

TCA9517ADGKR

LEVEL-TRANSLATING I2C BUS REPEATER

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TI

TCA9517DGKR

LEVEL-TRANSLATING I2C BUS REPEATER

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TI