TCAN1046A-Q1 [TI]

具有待机模式的增强型汽车类双路 CAN 收发器;
TCAN1046A-Q1
型号: TCAN1046A-Q1
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

具有待机模式的增强型汽车类双路 CAN 收发器

文件: 总22页 (文件大小:1954K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TCAN1046A-Q1  
ZHCSLK9 JULY 2021  
TCAN1046A-Q1 具有待机模式的汽车类双CAN FD 收发器  
1 特性  
3 说明  
AEC-Q1001):符合汽车应用要求  
• 两个具有模式控制功能的独立高CAN FD 收发器  
• 符ISO 11898-2:2016 物理层标准要求  
提供功能安全  
TCAN1046A-Q1 是一款双路高速控制器局域网 (CAN)  
收发器符合 ISO 11898-2:2016 高速 CAN 规范的物  
理层要求。  
该器件支持传统 CAN CAN FD 网络数据速率高达  
8 兆位/(Mbps)。此外该器件具有两个带独立电  
VCC1 VCC2 模式控制引脚STB1 和  
STB2CAN FD 通道允许每个 CAN 通道真正独  
立地运行。在需要冗余或额外 CAN FD 通道作为系统  
故障时的备份的应用中能够独立操作每个通道的能力  
非常重要。  
可帮助进行功能安全系统设计的文档  
• 支持传CAN 和经优化CAN FD 性能数据速  
25 8Mbps)  
– 具有较短的对称传播延迟时间可增加时序裕量  
• 支12V 24V 电池应用  
• 接收器共模输入电压±12V  
• 保护特性:  
该器件具有很多保护和诊断功能包括热关断 (TSD)、  
TXD 显性超时 (DTO) 和高达 ±58V 的总线故障保护,  
并且定义了电源欠压或引脚悬空情况下的失效防护行  
为。  
– 总线故障保护±58V  
– 欠压保护  
TXD 显性超(DTO)  
• 数据速率低9.2kbps  
– 热关断保(TSD)  
• 工作模式:  
– 正常模式  
– 支持远程唤醒请求功能的低功耗待机模式  
• 优化了未上电时的性能  
器件信息  
封装(1)  
VSON (DMT) (14)  
SOIC (D) (14)  
封装尺寸标称值)  
4.50mm x 3.00mm  
8.95mm x 3.91mm  
器件型号  
TCAN1046A-Q1  
(1) 如需了解所有可用封装请参阅数据表末尾的可订购产品附  
录。  
– 总线和逻辑引脚为高阻抗运行总线或应用上无  
负载)  
VIN  
VIN  
VOUT  
– 支持热插拔在总线RXD 输出上可实现上电  
和断电无干扰运行  
• 结温范围40°C 150°C  
• 采SOIC (14) 封装和无引线VSON (14) 封装  
(4.5mm x 3.0mm)具有改进的自动光学检(AOI)  
功能  
5V Voltage  
Regulator  
(e.g. TPSxxxx)  
4
11  
VCC2  
CANH1  
VDD  
VCC1  
13  
14  
GPIO  
STB1  
4
RXD1  
TXD1  
CAN FD  
Controller  
1
12  
CANL1  
System Controller  
Optional:  
Terminating  
Node  
Optional:  
Filtering,  
TCAN1046A-Q1  
Transient and  
ESD  
Dual CAN FD  
Transceiver  
2 应用  
8
GPIO  
STB2  
10  
CANH2  
7
6
CAN FD  
Controller  
RXD2  
TXD2  
• 汽车和运输  
车身控制模块  
汽车网关  
9
CANL2  
高级驾驶辅助系(ADAS)  
信息娱乐系统  
Optional:  
Terminating  
Node  
Optional:  
Filtering,  
Transient and  
ESD  
简化版原理图  
本文档旨在为方便起见提供有TI 产品中文版本的信息以确认产品的概要。有关适用的官方英文版本的最新信息请访问  
www.ti.com其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前请务必参考最新版本的英文版本。  
English Data Sheet: SLLSFJ4  
 
TCAN1046A-Q1  
ZHCSLK9 JULY 2021  
www.ti.com.cn  
4 Pin Configuration and Functions  
TXD1  
GND1  
VCC1  
RXD1  
TXD2  
GND2  
VCC2  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
STB1  
TXD1  
GND1  
VCC1  
RXD1  
TXD2  
GND2  
VCC2  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
STB1  
CANH1  
CANL1  
STB2  
CANH1  
CANL1  
STB2  
Thermal  
Pad  
CANH2  
CANL2  
RXD2  
CANH2  
CANL2  
RXD2  
8
8
Not to scale  
Not to scale  
4-1. D Package, 14 Pin SOIC, Top View  
4-2. DMT Package, 14 Pin VSON, Top View  
4-1. Pin Functions  
Pins  
Type  
Description  
Name  
TXD1  
GND1  
VCC1  
No.  
1
Digital Input CAN transmit data input 1, integrated pull-up  
2
GND1  
Ground connection, transceiver 1  
5-V supply voltage, transceiver 1  
3
Supply  
RXD1  
TXD2  
GND2  
VCC2  
4
Digital Output CAN receive data output 1, tri-state when VCC < UVVCC  
Digital Input CAN transmit data input 2, integrated pull-up  
5
6
GND2  
Ground connection, transceiver 2  
5-V supply voltage, transceiver 2  
7
Supply  
RXD2  
CANL2  
CANH2  
STB2  
8
Digital Output CAN receive data output 2, tri-state when VCC < UVVCC  
9
Bus IO  
Bus IO  
Low-level CAN bus 2 input/output line  
High-level CAN bus 2 input/output line  
10  
11  
12  
13  
14  
Digital Input Standby input 2 for mode control, integrated pull-up  
CANL1  
CANH1  
STB1  
Bus IO  
Bus IO  
Low-level CAN bus 1 input/output line  
High-level CAN bus 1 input/output line  
Digital Input Standby input 1 for mode control, integrated pull-up  
Electrically connected to GND, connect the thermal pad to the printed circuit board (PCB)  
ground plane for thermal relief  
Thermal Pad (VSON only)  
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5 Device and Documentation Support  
5.1 Device Support  
This device conforms to the following CAN standards. The core of what is needed is covered within this system  
specification; however, reference should be made to these standards and any discrepancies pointed out and  
discussed. This document should provide all the basics of what is needed. However, for a full understanding of  
CAN including the protocol these additional sources are helpful as the scope of CAN protocol in detail is outside  
the scope of this physical layer (transceiver) specification.  
5.1.1 Device Nomenclature  
CAN Transceiver Physical Layer Standards:  
ISO 11898-2:2016 High speed medium access unit (original High Speed CAN transceiver standard)  
ISO 11898-5 High speed medium access unit with low power mode (super sets -2 standard electrically in  
several specs and adds the original wake up capability via the bus in low power mode).  
ISO 11898-6 High speed medium access unit with selective wake.  
ISO 8802-3: CSMA/CD referenced for collision detection from ISO11898-2  
CAN FD 1.0 Spec and Papers  
Bosch Configuration of CAN Bit Timing, Paper from 6th International CAN Conference (ICC), 1999. This  
is repeated a lot in the DCAN IP CAN Controller spec copied into this system spec.  
GMW3122: GM requirements for HS CAN  
SAE J2284-2: High Speed CAN (HSC) for Vehicle Applications at 250 kbps  
SAE J2284-3: High Speed CAN (HSC) for Vehicle Applications at 500 kbps  
EMC requirements:  
HW Requirements for CAN, LIN, FR V1.3: German OEM requirements for HS CAN  
Conformance Test requirements:  
HS_TRX_Test_Spec_V_1_0: GIFT / ICT CAN test requirements for High Speed Physical Layer  
5.2 接收文档更新通知  
要接收文档更新通知请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册即可每周接收产品信息更  
改摘要。有关更改的详细信息请查看任何已修订文档中包含的修订历史记录。  
5.3 支持资源  
TI E2E支持论坛是工程师的重要参考资料可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解  
答或提出自己的问题可获得所需的快速设计帮助。  
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范并且不一定反映 TI 的观点请参阅  
TI 《使用条款》。  
5.4 Trademarks  
TI E2Eis a trademark of Texas Instruments.  
所有商标均为其各自所有者的财产。  
5.5 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled  
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may  
be more susceptible to damage because very small parametric changes could cause the device not to meet its published  
specifications.  
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5.6 术语表  
TI 术语表  
本术语表列出并解释了术语、首字母缩略词和定义。  
Mechanical, Packaging, and Orderable Information  
The following pages include mechanical, packaging, and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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6.1 Tape and Reel Information  
REEL DIMENSIONS  
TAPE DIMENSIONS  
K0  
P1  
W
B0  
Reel  
Diameter  
Cavity  
A0  
A0 Dimension designed to accommodate the component width  
B0 Dimension designed to accommodate the component length  
K0 Dimension designed to accommodate the component thickness  
Overall width of the carrier tape  
W
P1 Pitch between successive cavity centers  
Reel Width (W1)  
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE  
Sprocket Holes  
Q1 Q2  
Q3 Q4  
Q1 Q2  
Q3 Q4  
User Direction of Feed  
Pocket Quadrants  
Reel  
Diameter  
(mm)  
Reel  
Width W1  
(mm)  
Package  
Type  
Package  
Drawing  
A0  
(mm)  
B0  
(mm)  
K0  
(mm)  
P1  
(mm)  
W
(mm)  
Pin1  
Quadrant  
Device  
Pins  
SPQ  
TCAN1046ADMTRQ1  
TCAN1046ADRQ1  
VSON  
SOIC  
DMT  
D
14  
14  
3000  
2500  
330.0  
330.0  
12.4  
16.4  
3.2  
6.5  
4.7  
9.0  
1.15  
2.1  
8.0  
8.0  
12.0  
16.0  
Q1  
Q1  
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TAPE AND REEL BOX DIMENSIONS  
Width (mm)  
H
W
L
Device  
Package Type  
Package Drawing Pins  
SPQ  
3000  
2500  
Length (mm) Width (mm)  
Height (mm)  
55.0  
TCAN1046ADMTRQ1  
TCAN1046ADRQ1  
VSON  
SOIC  
DMT  
D
14  
14  
370.0  
853.0  
355.0  
449.0  
35.0  
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PACKAGE OUTLINE  
D0014A  
SOIC - 1.75 mm max height  
S
C
A
L
E
1
.
8
0
0
SMALL OUTLINE INTEGRATED CIRCUIT  
C
6.2  
5.8  
TYP  
SEATING PLANE  
0.1 C  
PIN 1 ID  
AREA  
A
12X 1.27  
14  
1
2X  
8.75  
8.55  
NOTE 3  
7.62  
7
8
0.51  
0.31  
14X  
4.0  
3.8  
B
1.75 MAX  
0.25  
C A B  
NOTE 4  
0.25  
0.13  
TYP  
SEE DETAIL A  
0.25  
GAGE PLANE  
0.25  
1.27  
0.10  
0.40  
0 - 8  
DETAIL A  
TYPICAL  
4220718/A 09/2016  
NOTES:  
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not  
exceed 0.15 mm, per side.  
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.  
5. Reference JEDEC registration MS-012, variation AB.  
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EXAMPLE BOARD LAYOUT  
D0014A  
SOIC - 1.75 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
14X (1.55)  
SYMM  
1
14  
14X (0.6)  
12X (1.27)  
SYMM  
8
7
(R0.05)  
TYP  
(5.4)  
LAND PATTERN EXAMPLE  
SCALE:8X  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL UNDER  
SOLDER MASK  
METAL  
0.07 MAX  
ALL AROUND  
0.07 MIN  
ALL AROUND  
SOLDER MASK  
DEFINED  
NON SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4220718/A 09/2016  
NOTES: (continued)  
6. Publication IPC-7351 may have alternate designs.  
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.  
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EXAMPLE STENCIL DESIGN  
D0014A  
SOIC - 1.75 mm max height  
SMALL OUTLINE INTEGRATED CIRCUIT  
14X (1.55)  
SYMM  
1
14  
14X (0.6)  
12X (1.27)  
SYMM  
7
8
(5.4)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
SCALE:8X  
4220718/A 09/2016  
NOTES: (continued)  
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
9. Board assembly site may have different recommendations for stencil design.  
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PACKAGE OUTLINE  
DMT0014B  
VSON - 1 mm max height  
SCALE 3.200  
PLASTIC SMALL OUTLINE - NO LEAD  
3.1  
2.9  
A
B
PIN 1 INDEX AREA  
4.6  
4.4  
0.1 MIN  
(0.13)  
1.0  
0.8  
S
C
A
L
E
3
0
.
0
0
0
SECTION A-A  
TYPICAL  
C
SEATING PLANE  
0.08 C  
0.05  
0.00  
1.6 0.1  
SYMM  
EXPOSED  
THERMAL PAD  
(0.2) TYP  
7
8
(0.19) TYP  
A
A
2X  
15  
SYMM  
3.9  
4.2 0.1  
14  
1
12X 0.65  
0.35  
0.25  
14X  
0.45  
0.35  
PIN 1 ID  
(OPTIONAL)  
14X  
0.1  
C A B  
0.05  
C
4225087/B 01/2021  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.  
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EXAMPLE BOARD LAYOUT  
DMT0014B  
VSON - 1 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
(1.6)  
14X (0.6)  
14X (0.3)  
SYMM  
1
14  
2X  
(1.85)  
12X (0.65)  
SYMM  
15  
(4.2)  
(0.69)  
TYP  
(
0.2) VIA  
TYP  
8
7
(R0.05) TYP  
(0.55) TYP  
(2.8)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:15X  
0.07 MAX  
ALL AROUND  
0.07 MIN  
ALL AROUND  
EXPOSED METAL  
EXPOSED METAL  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL  
METAL UNDER  
SOLDER MASK  
NON SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
4225087/B 01/2021  
NOTES: (continued)  
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature  
number SLUA271 (www.ti.com/lit/slua271).  
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown  
on this view. It is recommended that vias under paste be filled, plugged or tented.  
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EXAMPLE STENCIL DESIGN  
DMT0014B  
VSON - 1 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
(1.47)  
15  
14X (0.6)  
1
14  
14X (0.3)  
(1.18)  
12X (0.65)  
SYMM  
(1.38)  
(R0.05) TYP  
METAL  
TYP  
8
7
SYMM  
(2.8)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
EXPOSED PAD 15  
77.4% PRINTED SOLDER COVERAGE BY AREA  
SCALE:20X  
4225087/B 01/2021  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
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PACKAGE OPTION ADDENDUM  
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PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TCAN1046ADMTRQ1  
TCAN1046ADRQ1  
ACTIVE  
ACTIVE  
VSON  
SOIC  
DMT  
D
14  
14  
3000 RoHS & Green  
2500 RoHS & Green  
NIPDAU  
Level-2-260C-1 YEAR  
Level-1-260C-UNLIM  
-40 to 150  
-40 to 150  
1046A  
1046A  
Samples  
Samples  
NIPDAU  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
3-Jun-2022  
Addendum-Page 2  
GENERIC PACKAGE VIEW  
DMT 14  
3 x 4.5, 0.65 mm pitch  
VSON - 0.9 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
This image is a representation of the package family, actual package may vary.  
Refer to the product data sheet for package details.  
4225088/A  
www.ti.com  
PACKAGE OUTLINE  
DMT0014B  
VSON - 1 mm max height  
SCALE 3.200  
PLASTIC SMALL OUTLINE - NO LEAD  
3.1  
2.9  
A
B
PIN 1 INDEX AREA  
4.6  
4.4  
0.1 MIN  
(0.13)  
1.0  
0.8  
SECTION A-A  
SCALE 30.000  
SECTION A-A  
TYPICAL  
C
SEATING PLANE  
0.08 C  
0.05  
0.00  
1.6 0.1  
SYMM  
EXPOSED  
THERMAL PAD  
(0.2) TYP  
7
8
(0.19) TYP  
A
A
2X  
3.9  
15  
SYMM  
4.2 0.1  
14  
1
12X 0.65  
0.35  
0.25  
14X  
0.45  
0.35  
PIN 1 ID  
14X  
0.1  
C A B  
(OPTIONAL)  
0.05  
C
4225087/B 01/2021  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.  
www.ti.com  
EXAMPLE BOARD LAYOUT  
DMT0014B  
VSON - 1 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
(1.6)  
14X (0.6)  
14X (0.3)  
SYMM  
1
14  
2X  
(1.85)  
12X (0.65)  
SYMM  
15  
(4.2)  
(0.69)  
TYP  
(
0.2) VIA  
TYP  
8
7
(R0.05) TYP  
(0.55) TYP  
(2.8)  
LAND PATTERN EXAMPLE  
EXPOSED METAL SHOWN  
SCALE:15X  
0.07 MAX  
ALL AROUND  
0.07 MIN  
ALL AROUND  
EXPOSED METAL  
EXPOSED METAL  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
METAL  
METAL UNDER  
SOLDER MASK  
NON SOLDER MASK  
DEFINED  
SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK DETAILS  
4225087/B 01/2021  
NOTES: (continued)  
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature  
number SLUA271 (www.ti.com/lit/slua271).  
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown  
on this view. It is recommended that vias under paste be filled, plugged or tented.  
www.ti.com  
EXAMPLE STENCIL DESIGN  
DMT0014B  
VSON - 1 mm max height  
PLASTIC SMALL OUTLINE - NO LEAD  
(1.47)  
15  
14X (0.6)  
1
14  
14X (0.3)  
(1.18)  
12X (0.65)  
SYMM  
(1.38)  
(R0.05) TYP  
METAL  
TYP  
8
7
SYMM  
(2.8)  
SOLDER PASTE EXAMPLE  
BASED ON 0.125 mm THICK STENCIL  
EXPOSED PAD 15  
77.4% PRINTED SOLDER COVERAGE BY AREA  
SCALE:20X  
4225087/B 01/2021  
NOTES: (continued)  
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate  
design recommendations.  
www.ti.com  
重要声明和免责声明  
TI“按原样提供技术和可靠性数据(包括数据表)、设计资源(包括参考设计)、应用或其他设计建议、网络工具、安全信息和其他资源,  
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保。  
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任:(1) 针对您的应用选择合适的 TI 产品,(2) 设计、验  
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Copyright © 2022,德州仪器 (TI) 公司  

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