TCAN11623-Q1_V01_技术文档

TCAN11623-Q1, TCAN11625-Q1

SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021

TCAN1162x-Q1 Automotive CAN FD System Basis Chip with Sleep Mode and LDO

Output

1 Features

3 Description

•

AEC Q100 (Grade 1) Qualified for automotive

applications

Meets the requirements of ISO 11898-2:2016

Functional Safety-Capable

– Documentation available to aid in functional

safety system design

Wide input operational voltage range

Integrated LDO for CAN transceiver supply

– 5-V LDO with 100 mA output current capability -

TCAN11625

The TCAN1162x-Q1 are high-speed controller area

network (CAN) system basis chips (SBC) that

meet the physical layer requirements of the ISO

11898-2:2016 high-speed CAN specification. The

TCAN1162x-Q1 supports both classical CAN and

CAN FD networks up to 8 megabits per second

(Mbps).

•

Both the TCAN11623-Q1 and TCAN11625-Q1 support

a wide input supply range and integrates some

form of an LDO output. The TCAN11625-Q1 has a

5-V LDO output (V_CCOUT) which supplies the CAN

transceiver voltage internally as well as additional

current externally. The TCAN11623-Q1 has a 3.3-V

LDO output (V_LDO3), supplied from the 5-V LDO,

supporting external loads.

– 3.3-V LDO with 70 mA output current capability

- TCAN11623

Classic CAN and CAN FD up to 8 Mbps

V_IOlevel shifting supports: 1.7 V to 5.5 V

Operating modes

•

– Normal mode

– Standby mode

– Low-power sleep mode

High-voltage INH output for system power control

Local wake-up support via the WAKE pin

Defined behavior when unpowered

– Bus and IO terminals are high impedance (no

load to operating bus or application)

Protection features:

The TCAN1162x-Q1 allows for system-level

reductions in battery current consumption by

selectively enabling the various power supplies that

may be present on a system via the INH output pin.

This allows an ultra-low-current sleep state where

power is gated to all system components except for

the TCAN1162x-Q1, while monitoring the CAN bus.

When a wake-up event is detected, the TCAN1162x-

Q1 initiates system start-up by driving INH high.

•

– ±58-V CAN bus fault tolerant

– Load dump support on V_SUP

– IEC ESD protection

– Under-voltage and over-voltage protection

– Thermal shutdown protection

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

TCAN11623-Q1

TCAN11625-Q1

VSON (14)

4.5 mm x 3.00 mm

– TXD dominant state timeout (TXD DTO)

Extra wide junction temperature support

Available in the leadless VSON (14) package

with wettable flank for improved automated optical

inspection (AOI) capability

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

•

EN

3.3V Voltage Regulator

(e.g. TPSxxxx)

V_BAT

Motor Driver

2 Applications

0.1ꢀF

10ꢀF

3.3kΩ

33kΩ

V_SUP

10

V_IO

V_LDO5

5

3

•

Advanced driver assistance system (ADAS)

Body electronics and lighting

Automotive infotainment and cluster

Hybrid, electric and powertrain systems

0.1nF

9

7

WAKE

CANH

V_IN

13

INH

TCAN11625

nSLP

TS

14

6

CAN FD

Controller

nRST

TXD

11

1

CANL

12

Optional:

Terminating

Node

RXD

4

Optional:

Filtering,

Transient and

ESD

2

GND

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TCAN11623-Q1, TCAN11625-Q1

SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021

www.ti.com

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Description (continued).................................................. 3

6 Pin Configurations and Functions (TCAN11625)..........4

7 Pin Configurations and Functions (TCAN11623)..........5

8 Specifications.................................................................. 6

8.1 Absolute Maximum Ratings........................................ 6

8.2 ESD Ratings............................................................... 6

8.3 ESD Ratings IEC Specification...................................6

8.4 Recomended Operating Conditions............................7

8.5 Thermal Information....................................................7

8.6 Power Supply Characteristics.....................................7

8.7 Electrical Characteristics.............................................9

8.8 Switching Characteristics..........................................11

8.9 Typical Characteristics..............................................13

9 Parameter Measurement Information..........................14

10 Detailed Description....................................................18

10.1 Overview.................................................................18

10.2 Functional Block Diagram.......................................18

10.3 Feature Description.................................................20

10.4 Device Functional Modes........................................25

11 Application Information.............................................. 36

11.1 Application Information Disclaimer..........................36

11.2 Typical Application.................................................. 36

11.3 Application Curves.................................................. 38

12 Power Supply Requirements......................................39

13 Layout...........................................................................40

13.1 Layout Guidelines................................................... 40

13.2 Layout Example...................................................... 40

14 Device and Documentation Support..........................42

14.1 Documentation Support.......................................... 42

14.2 Receiving Notification of Documentation Updates..42

14.3 Support Resources................................................. 42

14.4 Trademarks.............................................................42

14.5 Electrostatic Discharge Caution..............................42

14.6 Glossary..................................................................42

15 Mechanical, Packaging, and Orderable

Information.................................................................... 42

4 Revision History

Changes from Revision * (May 2021) to Revision A (November 2021)

Page

•

Changed the document status from Advanced Information to Production data................................................. 1

2

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5 Description (continued)

This allows an ultra-low-current sleep state in which power is gated to all system components except for the

TCAN1162x-Q1, which remains in a low-power state while monitoring the CAN bus. When a wake-up event is

detected, the TCAN1162x-Q1 initiates node start-up by driving INH high.

The TCAN1162x-Q1 supports an ultra low-power standby mode where the high-speed transmitter and normal

receiver are switched off and a low-power wake-up receiver enables remote wake-up via the ISO 11898-2:2016

defined wake-up pattern (WUP).

The TCAN1162x-Q1 includes internal logic level translation via the V_IOterminal to allow for interfacing directly to

1.8-V, 2.5-V, 3.3-V, or 5-V controllers. The transceiver includes many protection and diagnostic features including

undervoltage detection, over voltage detection, thermal shutdown (TSD), driver dominant timeout (TXD DTO),

and bus fault protection up to ±58-V.

The TCAN1162x-Q1 allows for system-level reductions in battery current consumption by selectively enabling

the various power supplies that may be present on a node via the INH output pin. This allows an ultra-low-

current sleep state in which power is gated to all system components except for the TCAN1162x-Q1, which

remains in a low-power state while monitoring the CAN bus. When a wake-up pattern is detected on the bus or

when a local wake-up is requested via the WAKE input, the TCAN1162x-Q1 initiates node start-up by driving INH

high.

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TCAN11623-Q1, TCAN11625-Q1

SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021

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6 Pin Configurations and Functions (TCAN11625)

TXD

1

2

3

4

5

6

7

14

13

12

11

10

9

nSLP

CANH

CANL

nRST

V_SUP

GND

V_CCOUT

RXD

V_IO

Thermal

Pad

TS

WAKE

NC

INH

8

Not to scale

Figure 6-1. DMT Package, 14 Pin (VSON), Top View

Table 6-1. Pin Functions

PINS

TYPE

DESCRIPTION

NAME

TXD

NO.

1

Digital

GND

CAN transmit data input, integrated pull-up

GND

V_CCOUT

RXD

V_IO

2

Ground connection

3

Supply

Digital

Supply

Digital

5-V LDO regulated output voltage pin and transceiver supply

CAN receive data output, tri-state when V_IO< UV_VIO

IO supply voltage

4

5

TS

6

Transceiver status

INH

7

High Voltage Inhibit pin to control system voltage regulators and supplies, high voltage

Internally connected, leave floating or connect to GND

High Voltage Local WAKE input terminal, high voltage

NC

8

—

WAKE

V_SUP

nRST

CANL

CANH

nSLP

9

10

11

12

13

14

Supply

Digital

Bus IO

Digital

High voltage supply from the battery

Reset input/output

Low level CAN bus input/output line

High level CAN bus input/output line

Sleep mode control input, integrated pull-down

Electrically connected to GND, connect the thermal pad to the printed circuit board (PCB)

ground plane for thermal relief

Thermal Pad

—

4

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SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021

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7 Pin Configurations and Functions (TCAN11623)

TXD

1

2

3

4

5

6

7

14

13

12

11

10

9

nSLP

GND

CANH

CANL

nRST

V_SUP

ꢀ

V_FLT

RXD

V_IO

Thermal

Pad

TS

WAKE

V_LDO3

INH

8

Not to scale

Figure 7-1. DMT Package, 14 Pin (VSON), Top View

Table 7-1. Pin Functions

PINS

TYPE

DESCRIPTION

NAME

TXD

NO.

1

Digital Input

GND

CAN transmit data input, integrated pull-up

Ground connection

GND

V_FLT

2

3

Supply

5-V LDO transceiver filter pin. Place a 10 µF capacitor on this pin to ground.

CAN receive data output, tri-state when V_IO< UV_VIO

IO supply voltage

RXD

V_IO

4

Digital Output

Supply

5

TS

6

Digital

Transceiver status

INH

7

High Voltage

Supply

Inhibit pin to control system voltage regulators and supplies, high voltage

3.3-V LDO regulated output voltage pin

Local WAKE input terminal, high voltage

High voltage supply from the battery

Reset input/output

V_LDO3

WAKE

V_SUP

nRST

CANL

CANH

nSLP

8

9

High Voltage

Supply

10

11

12

13

14

Digital

Bus IO

Low level CAN bus input/output line

Bus IO

High level CAN bus input/output line

Sleep mode control input, integrated pull-down

Digital

Thermal

Pad

Electrically connected to GND, connect the thermal pad to the printed circuit board (PCB) ground

plane for thermal relief

—

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SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021

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8 Specifications

8.1 Absolute Maximum Ratings

over operating virtual junction temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

-0.3

–0.3

–58

MAX

UNIT

V

V_SUP

Supply voltage range

42

V_FLT

Transceiver supply voltage

5 V regulated output

6

V

V_CCOUT

V_LDO3

6

V

3.3 V regulated output

4.5

V

V_IO

IO level shifting voltage range

CAN bus IO voltage range (CANH, CANL)

WAKE input pin voltage range

INH output pin voltage range

Logic input terminal voltage range

Logic output terminal voltage range

Logic output current

6

V

V_BUS

58

V

V_WAKE

V_INH

–18

42 and V_I≤ V_SUP+ 0.3

V

–0.3

42 and V_O≤ V_SUP+ 0.3

V

V_{(Logic_Input)}

V_{(Logic_Output)}

I_O(LOGIC)

I_O(INH)

6

8

6

V

mA

INH output current

Wake current if due to ground shifts V_(WAKE)≤ V_(GND)– 0.3 V, thus the

current into WAKE must be limited via an external serial resistor

I_O(WAKE)

3

mA

T_J

Operating virtual junction temperature range

Storage temperature

–40

-65

150

165

°C

T_STG

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

8.2 ESD Ratings

VALUE

UNIT

HBM classification level 3A for all

±4000

Human body model (HBM), per AEC

Q100-002⁽¹⁾

HBM classification level 3A for

V_SUP, WAKE, INH

±8000

±10000

±750

V_(ESD)

Electrostatic discharge

V

HBM classification level 3B for

global pins CANH & CANL

Charged-device model (CDM), per AEC Q100-011

CDM classification level C5 for all pins

(1) AEC-Q100-002 indicates that HBM stresses shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

8.3 ESD Ratings IEC Specification

VALUE

UNIT

CAN bus terminals (CANH & CANL) to

±8000

System level electro-static

discharge (ESD)⁽¹⁾

IEC 61000-4-2 (150pF, 330Ω)

unpowered contact discharge

GND

V_ESD

V_SUPand WAKE

±8000

–100

75

Pulse 1

V

Pulse 2

ISO 7637 ISO pulse transients⁽²⁾

ISO 7637-3 transient⁽³⁾

CAN bus terminals (CANH & CANL) to

GND, V_SUPand WAKE

V_TRAN

Pulse 3a

–150

100

Pulse 3b

DCC slow transient pulse

±30

(1) Tested according to IEC 62228-3 CAN Transceiver, Section 6.4; DIN EN 61000-4-2

(2) Tested according to IEC 62228-3 CAN Transceiver, Section 6.3; standard pulse parameters defined in ISO 7637-2

(3) Tested according to ISO 7637-3; electrical transient transmission by capacitive and inductive coupling via lines other than supply line

6

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8.4 Recomended Operating Conditions

MIN

5.5

1.7

–2

NOM

MAX UNIT

V_SUP

Supply voltage range

28

V

V_IO

IO supply voltage

5.5

V

I_OH(DO)

I_OL(DO)

I_O(INH)

C_VSUP

C_VCCOUT

C_FLT

Digital output terminal high level output current

Digital output terminal low level output current

INH output current

mA

µF

°C

2

1

V_SUPpin capacitance

0.1

V_CCOUTpin capacitance TCAN11625

Filter pin capacitance TCAN11623

V_LDO3pin capacitance TCAN11623

Thermal shutdown rising

10

C_LDO3

T_SDR

1

4.7

180

165

15

10

175

T_SDF

Thermal shutdown falling

170

T_HYS

Thermal shutdown hysterisis

8.5 Thermal Information

DMT (VSON)

THERMAL METRIC⁽¹⁾

UNIT

14 PINS

37.7

37.9

14.2

0.7

R_ΘJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_ΘJC(top)

R_ΘJB

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JB

14.2

4.9

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

8.6 Power Supply Characteristics

Over recomended operating conditions with T_J= -40°C to 150°C, unless otherwise noted. All typical values are taken at

25°C, V_SUP= 12 V, V_IO= 3.3 V and R_L= 60 Ω

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply Voltage and Current

TXD = 0 V, R_L= 60 Ω, C_L= open

See Figure 9-2

60

70

mA

Supply current

Bus biasing active: dominant

Transceiver only

TXD = 0 V, R_L= 50 Ω, C_L= open

See Figure 9-2

I_SUP

Supply current

Bus biasing active: recessive

Transceiver only

TXD = V_IO, R_L= 50 Ω, C_L= open

See Figure 9-2

3

255

150

50

mA

µA

Supply current TCAN11623

Standby mode

Bus biasing autonomous: inactive

5.5 V < V_SUP≤ 19 V

See Figure 9-2

I_SUP(STB)

I_SUP(SLP)

Supply current TCAN11625

Standby mode

Bus bias autonomous: inactive

5.5 V < V_SUP≤ 19 V

See Figure 9-2

Supply current

Sleep mode

Bus bias autonomous: inactive

nSLP = 0 V, 5.5 V < V_SUP≤ 19 V

T_A> 85℃

See Figure 9-2

Supply current

Sleep mode

Bus bias autonomous: inactive

nSLP = 0 V, 5.5 V < V_SUP≤ 19 V

T_A≤ 85℃

See Figure 9-2

40

Supply current

5.5 V < V_SUP≤ 28 V

See Figure 9-2

I_SUP(BIAS)

UV_SUPR

60

µA

V

Bus bias autonomous: active⁽¹⁾

Under voltage V_SUPthreshold rising

Ramp Up

4.05

4.42

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8.6 Power Supply Characteristics (continued)

Over recomended operating conditions with T_J= -40°C to 150°C, unless otherwise noted. All typical values are taken at

25°C, V_SUP= 12 V, V_IO= 3.3 V and R_L= 60 Ω

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

UV_SUPF

I_IO

Under voltage V_SUPthreshold falling

Ramp Down

3.9

4.25

V

IO Supply Current

Normal mode

RXD floating, TXD = 0 V

RXD floating, TXD = V_IO

nSLP = 0 V

150

12

µA

IO Supply Current - TCAN11625

Normal, or Standby

I_IO

IO Supply Current - TCAN11623

Normal, or Standby

12.5

IO Supply Current

Sleep mode (T_J≤ 125℃)

10

UV_IOR

Under voltage V_IOthreshold rising

Under voltage V_IOthreshold falling

Hysteresis voltage on UV_VIO

Ramp Up

1.4

1.25

80

1.65

V

UV_IOF

Ramp Down

1

V_HYS(UVIO)

40

160

mV

V_FLT/V_LDO3V_CCOUTCharacteristics

V_FLT

CAN regulator filter pin

V_SUP= 5.5 to 28 V

4.9

5.1

V

V_SUP= 5.5 to 18 V

I_L= 0 to 100 mA

TXD = V_IO

V_CCOUT

5 V regulated output

V_SUP= 5.65 to 18 V

I_L= 0 to 175 mA

TXD = V_IO

V_CCOUT

4.9

5.1

V

V_SUP= 5.65 to 18 V

I_L= 0 to 100 mA

TXD = 0 V; V_CANH= 0 V

V_CCOUT

5 V regulated output

Dropout voltage

5.1

650

3.4

V

mV

V

V_{CCOUT_DROP}

V_LDO3

5 V LDO, V_SUP– V_CCOUT, I_L= 125 mA

300

V_SUP= 5.5 to 18 V

I_LDO= 0 to 70 mA

3.3 V regulated output

3.2

TXD = 0 V; V_CANH= 0 V

∆V_{LDO3(∆VSUP)}

∆V_{CCOUT(∆VSUP)}

∆V_{LDO3(∆VSUPL)}

∆V_{CCOUT(∆VSUPL)}

UV_FLTR

Line regulation

V_SUP= 5.5 to 28 V, ΔV_LDO, I_LDO= 10 mA

V_SUP= 5.5 to 28 V, I_L= 10 mA, ΔV_CCOUT

I_LDO= 1 to 70 mA, V_SUP= 14 V, ΔV_LDO

I_L= 1 to 125 mA, V_SUP= 14 V, ΔV_CCOUT

Ramp Up

50

mV

V

Line regulation

Load regulation

50

Load regulation

50

Under voltage V_FLTthreshold rising

Under voltage V_FLTthreshold falling

Under voltage V_CCOUTthreshold rising

Under voltage V_CCOUTthreshold falling

Under voltage V_LDO3threshold rising

Under voltage V_LDO3threshold falling

Over voltage V_FLTthreshold rising

Over voltage V_FLTthreshold falling

Over voltage V_CCOUTthreshold rising

Over voltage V_CCOUTthreshold falling

Over voltage V_LDO3threshold rising

Over voltage V_LDO3threshold falling

Output current limit

4.6

4.45

4.6

4.75

UV_FLTF

Ramp Down

4.2

V

UV_VCCOUTR

UV_VCCOUTF

UV_LDO3R

Ramp Up

4.75

3.1

V

Ramp Down

4.45

2.9

V

Ramp Up

V

UV_LDO3F

Ramp Down

2.5

2.75

5.7

V

OV_FLTR

Ramp Up

6.15

3.93

V

OV_FLTF

Ramp Down

5.47

5.65

5.7

V

OV_CCOUTR

OV_CCOUTF

OV_LDO3R

Ramp Up

V

Ramp Down

5.65

3.8

V

Ramp Up

V

OV_LDO3F

Ramp Down

3.6

175

90

3.7

V

I_{L_VCCOUT}

I_{L_LDO3}

V_CCOUTshort to ground

V_LDO3short to ground

275

160

mA

Output current limit

V_RIP= 0.5 V_PP, Load = 10 mA, ƒ = 100 Hz,

C_O= 10 μF

PSRR_VCCOUT

PSRR_LDO3

Power supply rejection ripple rejection

60

37

dB

V_RIP= 0.5 V_PP, Load = 10 mA, ƒ = 100 Hz,

C_O= 4.7 μF

(1) After a valid wake-up the total I_SUPcurrent is the sum of I_SUP(STB)and I_SUP(BIAS)(I_SUP= I_SUP(STB)+ I_SUP(BIAS)

)

8

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8.7 Electrical Characteristics

Over recommended operating conditions with T_J= –40°C to 150°C, unless otherwise noted. All typical values are taken at

25°C, V_SUP= 12 V, V_IO= 3.3 V and R_L= 60 Ω

PARAMETER

CAN Driver Electrical Characteristics

Dominant output voltage

TEST CONDITIONS

MIN

TYP

MAX UNIT

CANH

CANL

2.75

0.5

2

4.5

2.25

3

V

TXD = 0 V, 50 ≤ R_L≤ 65 Ω, C_L= open, R_CM

=

Bus biasing active

V_O(D)

open

Dominant output voltage

See Figure 9-2

Bus biasing active

Recessive output voltage

Bus biasing active

TXD = V_IO, R_L= open (no load), R_CM= open

See Figure 9-2

V_O(R)

Driver symmetry

nSLP = V_IO, R_L= 60 Ω, C_SPLIT= 4.7 nF, C_L=

Bus biasing active

(V_O(CANH)+ V_O(CANL)) / V_CCOUT

(V_O(CANH)+ V_O(CANL)) / V_FLT

Open, R_CM= Open, TXD = 250 kHz, 1 Mhz,

2.5 MHz

See Figure 9-2

V_SYM

0.9

1.1

V/V

mV

DC Driver symmetry

Bus biasing active

V_CCOUT– V_O(CANH)– V_O(CANL)

V_{FLT –}V_O(CANH)– V_O(CANL)

nSLP = V_IO, R_L= 60 Ω, C_L= open

See Figure 9-2

V_{SYM_DC}

V_OD(DOM)

V_OD(REC)

–400

400

Differential output voltage

Bus biasing active

Dominant

nSLP =V_IO, TXD = 0 V, 50 Ω ≤ R_L≤ 65 Ω, C_L=

open

See Figure 9-2

CANH - CANL

1.5

1.4

1.5

3

3.3

5

V

Differential output voltage

Bus biasing active

Dominant

nSLP = V_IO, TXD = 0 V, 45 Ω ≤ R_L≤ 70 Ω, CL

= open

See Figure 9-2

CANH - CANL

Differential output voltage

Bus biasing active

Dominant

nSLP = V_IO, TXD = 0 V, R_L= 2240 Ω, C_L

open

See Figure 9-2

=

Differential output voltage

Bus biasing active

Bus biasing inactive

Recessive

nSLP = V_IO, TXD = V_IO, R_L= open Ω, C_L

CANH - CANL

open

See Figure 9-2

–50

50

mV

nSLP =0 V, TXD = V_IO

R_L= open (no load), C_L= open

See Figure 9-2

CANH

-0.1

-0.2

–75

0.1

0.2

V

Pin output voltage

Bus biasing inactive

V_O(INACT)

V_OD(STB)

I_OS(DOM)

I_OS(REC)

nSLP =0 V, TXD = V_IO

R_L= open (no load), C_L= open

See Figure 9-2

CANL

nSLP =0 V, TXD = V_IO

R_L= open (no load), C_L= open

See Figure 9-2

Differential output voltage

Bus biasing inactive

CANH - CANL

V

Short-circuit steady-state output current

Bus biasing active

nSLP = V_IO, TXD = 0 V

-15 V ≤ V_(CANH)≤ 40 V

See Figure 9-2 and Figure 9-8

mA

Dominant

Short-circuit steady-state output current

Bus biasing active

nSLP = V_IO,TXD = 0 V

-15 V ≤ V_(CANL)≤ 40 V

See Figure 9-2 and Figure 9-8

75

3

Dominant

Short-circuit steady-state output current

Bus biasing active

nSLP = V_IO, V_BUS= CANH = CANL

-27 V ≤ V_BUS≤ 42 V

–3

Recessive

See Figure 9-2 and Figure 9-8

CAN Receiver Electrical Characteristics

Receiver dominant state input voltage range

V_IT(DOM)

0.9

-3

8

V

Bus biasing active

nSLP = V_IO, -12 V ≤ V_CM≤ 12 V

See Figure 9-3 and Table 10-6

Receiver recessive state input voltage range

Bus biasing active

V_IT(REC)

0.5

Hysteresis voltage for input threshold

Bus biasing active

nSLP = V_IO

See Figure 9-3 and Table 10-6

V_HYS

80

-5

140

mV

V

V_DIFF(MAX)

V_DIFF(DOM)

V_DIFF(REC)

V_CM

Maximum rating of V_DIFF

10

8

Receiver dominant state input voltage range

Bus biasing inactive

1.150

V

nSLP = 0 V, -12 V ≤ V_CM≤ 12 V

See Figure 9-3 and Table 10-6

Receiver recessive state input voltage range

Bus biasing inactive

-3

0.4

12

V

nSLP = V_IO

See Figure 9-3 and Table 10-6

Common mode range

–12

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8.7 Electrical Characteristics (continued)

Over recommended operating conditions with T_J= –40°C to 150°C, unless otherwise noted. All typical values are taken at

25°C, V_SUP= 12 V, V_IO= 3.3 V and R_L= 60 Ω

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Power-off (unpowered) bus input leakage

current

I_OFF(LKG)

C_I

V_SUP= 0 V, CANH = CANL = 5 V

2.5

20

µA

pF

Input capacitance to ground (CANH or CANL)

TXD = V_IO

(1)

C_ID

R_ID

R_IN

Differential input capacitance⁽¹⁾

Differential input resistance

10

100

50

pF

kΩ

50

25

TXD = V_IO, nSLP = 5 V

-12 V ≤ V_CM≤ 12 V

Input resistance (CANH or CANL)

Input resistance matching:

[1 – R_IN(CANH)/ R_IN(CANL)] × 100%

R_IN(M)

V_(CANH)= V_(CANL)= 5 V

–1

1

%

TXD Input Characteristics

V_IH

High level input voltage

0.7

V_IO

µA

kΩ

µA

pF

V_IL

Low level input voltage

High level input leakage current

Low level input leakage current

Pull-up resistance

0.3

1

I_IH

TXD = V_IO= 5.5 V

–1

–130

40

0

I_IL

TXD = 0 V, V_IO= 5.5 V

–15

80

1

R_PU

I_LKG(OFF)

C_I

60

0

Unpowered leakage current

Input Capacitance

TXD = 5.5 V, V_SUP= V_IO= 0 V

–1

V_IN= 0.4 x sin(2 × π × 2 × 10⁶× t) + 2.5 V

5

RXD Output Characteristics

V_OH

High level output voltage

I_O= –2 mA.

I_O= 2 mA.

0.8

V_IO

kΩ

µA

V_OL

Low level output voltage

Pull-up resistance

0.2

80

5

R_PU

40

-5

60

I_LKG(OFF)

Unpowered leakage curret

RXD = 5.5 V, V_SUP= V_IO= 0 V

nSLP Input Characteristics

V_IH

High level input voltage

0.7

V_IO

µA

kΩ

µA

V_IL

Low level input voltage

0.3

130

1

I_IH

High level input leakage current

Low level input leakage current

Pull-down resistance

nSLP = V_IO= 5.5 V

50

–1

40

–1

I_IL

nSLP = 0 V, V_IO= 5.5 V

R_PD

I_LKG(OFF)

60

0

80

1

Unpowered leakage current

nSLP = 5.5 V, V_IO= 0 V

INH Output Characteristics

High level voltage drop INH with respect to

V_SUP

ΔV_H

I_INH= –6 mA

INH = 0 V

0.5

1

V

I_LKG(INH)

Sleep mode leakage current

–0.5

4

0.5

µA

WAKE Input Characteristics

V_IH

V_IL

High-level input voltage

V

Sleep mode

WAKE = 1 V

Low-level input voltage

Low level input leakage current

Input hysteresis

2

3

I_IL

µA

mV

V_HYS

800

0.8

1200

nRST Bidirectional Characteristics

V_IH

V_IL

High level input voltage

V_CCOUT

Low level input voltage

0.2 V_CCOUT

V_LDO3

V_IH

V_IL

High level input voltage

Low level input voltage

0.2 V_LDO3

0.2 V_CCOUT

0.2 V_LDO3

V_OL

I_IH

Low level output voltage (TCAN11625)

Low level output voltage (TCAN11623)

High level input leakage current

Pull-up resistance to V_LDO

I_O= 2 mA.

–1

0

1

µA

kΩ

R_PU

160

240

320

TS Output Characteristics

V_OHHigh-level output voltage

I_O= -2 mA

0.8

V_IO

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8.7 Electrical Characteristics (continued)

Over recommended operating conditions with T_J= –40°C to 150°C, unless otherwise noted. All typical values are taken at

25°C, V_SUP= 12 V, V_IO= 3.3 V and R_L= 60 Ω

PARAMETER

Low-level output voltage

Unpowered leakage current

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_OL

I_O= 2 mA

TS = 5.5 V, V_IO= 0 V

0.2

1

V_IO

µA

I_LKG(OFF)

–1

0

(1) Test according to ISO 11898-2:2003

8.8 Switching Characteristics

Over recomended operating conditions with T_J= -40°C to 150°C, unless otherwise noted. All typical values are taken at

25°C, V_SUP= 12 V, V_IO= 3.3 V and R_L= 60 Ω

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

Supply Switching Characteristics

C_FLT= 10 µF

C_VCCOUT= 10 µF

C_LDO3= 4.7 µF

See Figure 9-9

See Figure 9-10

t_{POWER_UP}

CAN supply power up time

1.8

4

ms

t_UV(SUP)

t_UV(FLT)

V_SUPfilter time (rising and falling)

4

25

µs

Undervoltage detection delay timeCAN active to CAN autonomous: active or inactive

Time for device to enter sleep

t_UV(LDO)

t_UVIO

V_LDOfilter time (rising and falling)

V_IOfilter time (rising and falling)

state reset state once UV_LDOis

reached

30

10

µs

8

12

Device Switching Characteristics

t_UVIO(SLP)Undervoltage detection delay time standby mode to sleep mode

t_UV(nRST)

200

350

50

1.8

2

ms

µs

ms

s

Undervoltage detection delay time nRST low

Bus time to meet filtered bus requirments for wakeup request

Bus wakeup timeout value

t_{WK_FILTER}

t_{WK_TIMEOUT}

t_SILENCE

0.5

0.8

See Figure 10-7

Time out for bus inactivity

0.9

4

1.2

5

t_INACTIVE

Hardware timer for failsafe and power up inactivity⁽¹⁾

3

min

Time from the start of a dominant-recessive-dominant sequence

until Vsym ≥ 0.1

Each phase: 6 μs

See Figure 9-12

t_BIAS

250

µs

us

ns

V_FLT> UV_FLT(R)

V_CCOUT> UV_VCCOUT(R)

V_IO> UV_IO(R)

t_CAN(ACTIVE)

Time from swtiching to CAN active mode to TS pin transitioning high

25

nSLP = V_IO

Total loop delay, driver input (TXD) to receiver output (RXD)

Recessive to dominant

t_PROP(LOOP1)

t_PROP(LOOP2)

t_nSLP(fltr)

100 160

R_L= 60 Ω, C_L= 100 pF, C_L(RXD)

15 pF

See Figure 9-6

=

Total loop delay, driver input (TXD) to receiver output (RXD)

Dominant to recessive

120 175

ns

µs

nSLP pin filter time

Sleep pin filter time

2.5

20

7.5

35

50

Low time required on nSLP to

enter sleep mode

t_SLP

Mode change time

t_{mode_slp_reset}

WUP or LWU event to INH asserted high, see

Driver Switching Characteristics

t_pHR

t_pLD

t_sk(p)

t_R

Propagation delay time, high TXD to driver recessive

20

15

35

40

10

40

45

70

20

ns

Propagation delay time, low TXD to driver dominant

Pulse skew (|t_pHR- t_pLD|)

R_L= 60 Ω, C_L= 100 pF, R_CM

open

See Figure 9-2

=

Differential output signal rise time

Differential output signal fall time

t_F

R_L= 60 Ω, C_L= open

See Figure 9-7, TXD = 0 V

t_{TXD_DTO}

Dominant timeout

1.2

3.8

ms

Receiver Switching Characteristics

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8.8 Switching Characteristics (continued)

Over recomended operating conditions with T_J= -40°C to 150°C, unless otherwise noted. All typical values are taken at

25°C, V_SUP= 12 V, V_IO= 3.3 V and R_L= 60 Ω

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

t_pRH

t_pDL

t_R

Propagation delay time, bus recessive input to high RXD

Propagation delay time, bus dominant input to RXD low output

Output signal rise time (RXD)

25

80 140

ns

20

50

8

110

C_L(RXD)= 15 pF

See Figure 9-3

t_F

Output signal fall time (RXD)

5

WAKE Characteristics

t_WAKETime required for INH pin to go high after an local wake event occurs on the WAKE pin

nRST Characteristics

40

µs

t_nRST

Minimum low time for reset

Input pulse width

Cold crank

15

20

1

µs

ms

t_nRST(cold)

t_nRST(warm)

Output pulse width

27

Warm crank

1.5

CAN FD Timing Characteristics

Bit time on CAN bus output pins with t_BIT(TXD)

=

435

155

80

530

210

140

530

215

140

ns

500 ns

R_L= 60 Ω, C_L= 100 pF

C_L(RXD)= 15 pF

Δt_REC= t_BIT(RXD)- t_BIT(BUS)

See Figure 9-6

Bit time on CAN bus output pins with t_BIT(TXD)

200 ns

t_BIT(BUS)

V_IO> 1.8V

Bit time on CAN bus output pins with t_BIT(TXD)

125 ns

Bit time on CAN bus output pins with t_BIT(TXD)

500 ns

435

155

80

R_L= 60 Ω, C_L= 100 pF

C_L(RXD)= 15 pF

Δt_REC= t_BIT(RXD)- t_BIT(BUS)

See Figure 9-6

Bit time on CAN bus output pins with t_BIT(TXD)

200 ns

t_BIT(BUS)

V_IO≤ 1.8V

Bit time on CAN bus output pins with t_BIT(TXD)

125 ns

Bit time on RXD output pins with t_BIT(TXD)= 500 ns

Bit time on RXD output pins with t_BIT(TXD)= 200 ns

Bit time on RXD output pins with t_BIT(TXD)= 125 ns

Receiver timing symmetry with t_BIT(TXD)= 500 ns

Receiver timing symmetry with t_BIT(TXD)= 200 ns

Receiver timing symetry with t_BIT(TXD)= 125 ns

400

120

80

550

220

135

40

ns

R_L= 60 Ω, C_L= 100 pF

C_L(RXD)= 15 pF

Δt_REC= t_BIT(RXD)- t_BIT(BUS)

See Figure 9-6

t_BIT(RXD)

R_L= 60 Ω, C_L= 100 pF

C_L(RXD)= 15 pF

Δt_REC= t_BIT(RXD)- t_BIT(BUS)

See Figure 9-6

-65

-45

-40

Δt_REC

15

10

(1) Timer is reset when the CAN bus changes states.

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8.9 Typical Characteristics

112

108

104

100

96

26

25.5

25

-40 C

30 C

150 C

-40 C

25 C

125 C

150 C

24.5

24

92

23.5

23

88

84

22.5

22

80

4

8

12

16

V_SUP(V)

20

24

C_LRXD= 15 pF

28

4

8

12

16

V_SUP(V)

20

24

28

R_L= 60 Ω

C_L= 100 pF

R_L= 60 Ω

Figure 8-1. t_PROP(LOOP1)over V_SUP

Figure 8-2. I_SUPover V_SUPSleep Mode

3

-40 C

50 C

150 C

2.75

2.5

2.25

2

1.75

1.5

4

6

8

10 12 14 16 18 20 22 24 26 28

V_SUP(V)

R_L= 60 Ω

Figure 8-3. V_OD(DOM)over V_SUP

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9 Parameter Measurement Information

CANH

TXD

R_L

C_L

CANL

Figure 9-1. I_SUPTest Circuit

R_CM

CANH

50%

TXD

R_L

C_L

V_OD

V_CM

V_CC

V_O(CANH)

t_pLD

t_pHR

90%

10%

0V

CANL

R_CM

0.9V

V_O(CANL)

V_OD

0.5V

t_R

t_F

Figure 9-2. Driver Test Circuit and Measurement

CANH

1.5V

0.9V

V_ID

I_O

RXD

0.5V

0V

V_ID

t_pDL

t_pRH

V_OH

V_O

C_{L_RXD}

CANL

90%

V_O(RXD)

50%

10%

V_OL

t_F

t_R

Figure 9-3. Receiver Test Circuit and Measurement

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UV_LDO5

(see NOTE A)

nRST

V_LDO5

(see NOTE A)

t_nRST(warm)

Figure 9-5. t_nRSTWarm Start

nRST

t_nRST(cold)

NOTE A: V_FLT& UV_FLTRfor TCAN11623.

Figure 9-4. t_nRSTCold Start

TXD

V_I

70%

t_LOOP2

30%

CANH

0V

TXD

5 x t_BIT(TXD)

t_BIT(TXD)

V_I

R_L

C_L

CANL

t_BIT(Bus)

nSLP

0V

900mV

500mV

RXD

V_DIFF

V_O

C_{L_RXD}

RXD

V_OH

70%

30%

V_OL

t_BIT(RXD)

Figure 9-6. Transmitter and Receiver Timing Behavior Test Circuit and Measurement

V_IH

CANH

TXD

0V

R_L

C_L

V_OD

V_OD(D)

CANL

0.9V

V_OD

0.5V

0V

t_{TXD_DTO}

Figure 9-7. TXD Dominant Timeout Test Circuit and Measurement

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200 ꢀs

I_OS

CANH

TXD

V_BUS

I_OS

CANL

V_BUS

0V

or

0V

V_BUS

Figure 9-8. Driver Short-Circuit Current Test and Measurement

V_SUP

4.5V

V_FLT

C_FLT= 10

F

V_SUP

0 V

TCAN11623

V_SUP

t_{POWER_UP}

C_VSUP

V_LDO3

C_LDO3= 4.7

V_LDO3

V_O

90%

F

0 V

Figure 9-9. TCAN11623 t_{POWER_UP}Timing Measurement

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V_SUP

4.5V

V_CCOUT

C_VCCOUT= 10

F

V_SUP

0 V

TCAN11625

V_SUP

t_{POWER_UP}

C_VSUP

V_CCOUT

90%

V_O

0 V

Figure 9-10. TCAN11625 t_{POWER_UP}Timing Measurement

V_IH(WAKE Input)

V_IL(WAKE Input)

V_WAKE

V_SUP

INH

0V

C_VSUP

OR

t_WAKE

TCAN1162x

t_WAKE

V_WAKE

INH = high

V_SUP-1V

INH

V_SUP-1V

INH

Figure 9-11. t_WAKEWhile Monitoring INH Output

Figure 9-12. Test Signal Definition for Bias Reaction Time Measurement

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10 Detailed Description

10.1 Overview

The TCAN1162x-Q1 are high speed controller area network (CAN) system basis chips (SBC) that meet the

physical layer requirements of the ISO 11898-2:2016 high speed CAN specification. The TCAN1162x-Q1

supports both classical CAN and CAN FD networks up to 8 megabits per second (Mbps).

Both the TCAN11623-Q1 and TCAN11625-Q1 support a wide input supply range and integrates some form of an

LDO output. The TCAN11625-Q1 has a 5-V LDO output (V_CCOUT) which supplies the CAN transceiver voltage

internally as well as additional current externally. The TCAN11623-Q1 has a 3.3-V LDO output (V_LDO3), supplied

from the 5-V LDO, supporting external loads.

The TCAN1162x-Q1 allows for system-level reductions in battery current consumption by selectively enabling

the various power supplies that may be present on a system via the INH output pin. This allows an ultra-low-

current sleep state where power is gated to all system components except for the TCAN1162x-Q1, while

monitoring the CAN bus. When a wake-up event is detected, the TCAN1162x-Q1 initiates system start-up by

driving INH high.

10.2 Functional Block Diagram

V_IO

V_SUP

10

V_LDO5V

V_CCOUT

3

5

V_IO

1

DOMINANT

TIME OUT

TXD

INH

V_SUP

13

12

CANH

CANL

7

9

V_SUP

Driver

WAKE

nSLP

TS

WAKE

14

6

CONTROL and MODE

LOGIC

OVER

TEMP

V_CCOUT

UNDER

VOLTAGE

11

nRST

RXD

High Speed Receiver

Low Power Receiver

V_IO

4

Logic Output

MUX

WUP

Detect

2

GND

Figure 10-1. TCAN11625-Q1

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V_IO

V_SUP

10

V_LDO5V

V_FLT

V_LDO3

8

3

5

V_IO

1

DOMINANT

TIME OUT

TXD

INH

V_SUP

13

CANH

V_LDO

3.3V

7

9

V_SUP

Driver

WAKE

nSLP

TS

WAKE

12

CANL

14

6

CONTROL and MODE

LOGIC

OVER

TEMP

V_LDO3

UNDER

VOLTAGE

11

nRST

RXD

High Speed Receiver

Low Power Receiver

V_IO

4

Logic Output

MUX

WUP

Detect

2

GND

Figure 10-2. TCAN11623-Q1

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10.3 Feature Description

10.3.1 V_SUPPin

This pin is connected to the battery supply. It provides the supply to the internal regulators that support the digital

core, the CAN transceiver, the output regulator, and the low power CAN receiver.

10.3.2 V_CCOUTPin

An internal LDO provides power for the integrated CAN transceiver and the V_CCOUToutput pin. The amount

of current that can be delivered externally is dependent upon the CAN transceiver requirements during normal

operation as well as the ambient operating temperature. When a CAN bus fault takes place that requires

additional current from the LDO, the total available current to external load components may be degraded.

During sleep mode the LDO is disabled and no current can be delivered. Once the device leaves sleep mode

and enters other active modes the LDO is enabled for normal operation. This pin requires a 10 μF external

capacitor as close to the pin as possible.

10.3.3 V_FLTPin

An internal LDO provides power for the integrated CAN transceiver. While in sleep mode the LDO is disabled.

Once the device leaves sleep mode and enters other active modes the LDO is enabled for normal operation.

This pin requires a 10 μF external capacitor as close to the pin as possible.

10.3.4 V_LDO3Pin

An internal LDO provides a 3.3 V output for supplying power to external devices. During sleep mode the LDO

is disabled and no current can be delivered. Once the device leaves sleep mode and enters other active modes

the LDO is enabled for normal operation. This pin requires a 4.7 μF external capacitor as close to the pin as

possible.

10.3.5 Digital Inputs and Outputs

The TCAN1162x-Q1 has a V_IOsupply that is used to set the digital input thresholds. The input thresholds are

ratio metric to the V_IOsupply using CMOS input levels, making them scalable for CAN controllers with digital IOs

from 1.7 V to 5.5 V. The TXD input is biased to the V_IOlevel to force a recessive input in case the pin floats. The

high level output voltage for the RXD and TS output pins is driven to the V_IOlevel as logic-high outputs.

10.3.5.1 TXD Pin

TXD is a digital signal, referenced to V_IO, from a CAN controller to the TCAN1162x-Q1.

10.3.5.2 RXD Pin

RXD is a digital signal, referenced to V_IO, from the TCAN1162x-Q1 to a CAN controller. This pin is only driven

once V_IOis present.

10.3.5.3 TS Pin

The transceiver status, TS, output pin is used to indicate to the status of the CAN transceiver to the controller.

When the TCAN1162x-Q1 is in normal mode with no TXD DTO fault the TS pin is driven high. The TS pin is

driven low signaling to the controller that the TCAN1162x-Q1 is not ready for normal operation.

The TS output will be driven low if the following conditions exist:

•

TXD driven dominant for t ≥ t_{TXD_DTO}

T_J≥ T_SDR

The TS output is tri-stated if the following conditions exist:

V_IO< UV_VIOF

The TCAN11625 TS output will be driven low if the following conditions exist:

•

V_LDO5< UV_LDO5F

V_LDO5> OV_LDO5R

The TCAN11623 TS output will be driven low if the following conditions exist:

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•

V_FLT< UV_VFLTF

V_LDO3< UV_LDO3F

V_LDO3> OV_LDO3R

V_FLT> OV_VFLTR

10.3.6 Digital Control and Timing

This device is a 14 pin CAN FD transceiver/SBC. Timings are all mixed signal and are covered at the device

electrical specification level including the small amounts of control logic for this device. All device mode control

is done via one digital input, nSTB or nSLP and through the use of timers and fault conditions internal to the

device.

10.3.7 V_IOPin

The V_IOpin provides the digital IO voltage to match the controller's IO voltage thus avoiding the requirements for

an ecternal level shifter. The integrated level shifter supports voltages from 1.7 V to 5.5 V providing the widest

range of controller support.

10.3.8 GND

GND is the ground pin and it must be connected to the PCB ground.

10.3.9 INH Pin

The TCAN1162x-Q1 inhibit (INH) output pin can be used to control the enable of system power management

devices allowing for a significant reduction in battery quiescent current consumption while the application is in

sleep mode. The INH pin has two states: driven high and high impedance. When the INH pin is driven high the

terminal shows V_SUPminus a diode voltage drop. In the high impedance state the output will be left floating. The

INH pin is high in the normal and standby modes and is low when in sleep mode. A 100 kΩ load can be added to

the INH output to ensure a fast transition time from the driven high state to the low state and to also force the pin

low when left floating.

This terminal should be considered a high-voltage logic terminal, not a power output thus should be used to drive

the EN terminal of the system’s power management device and not used as a switch for the power management

supply itself. This terminal is not reverse battery protected and thus should not be connected outside the system

module.

10.3.10 WAKE Pin

The WAKE pin is a high-voltage reverse-blocked input used for the local wake-up (LWU) function. This function

is explained further in Local Wake-Up (LWU) via WAKE Input Terminal section. The pin is defaulted to bi-

directional edge trigger, meaning a local wake-up (LWU) is recognize on either a rising or falling edge of WAKE

pin transition.

10.3.11 nRST Pin

The nRST is an bidirectional open drain low side driver with an integrated pull-up resistor to VCCOUT

(TCAN11625-Q1) or V_LDO3(TCAN11623-Q1). It can be pulled low by the device when placed in fail-safe mode.

During initial power-up of the device, a sleep mode to reset transition, a fail-safe mode to reset transition, or

an undervoltage event will be recognized as a cold crank reset condition. The nRST pin will be held low for

t_nRST(cold)allowing the MCU and peripheral devices to power-up correctly before data transmission begins.

To enter reset mode from normal mode, or standby mode the nRST must be pulled low for a minimum of time

of t_nRST. The TCAN1162x-Q1 recognizes this as a warm crank reset condition and holds the nRST pin low for

t_nRST(warm)

.

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nRST

CONTROL and MODE

LOGIC

Figure 10-3. nRST Circuit

10.3.12 CAN Bus Pins

These are the CAN high and CAN low, CANH and CANL, differential bus pins. These pins are connected to the

CAN transceiver and the low-voltage wake receiver.

10.3.13 Local Faults

10.3.13.1 TXD Dominant Timeout (TXD DTO)

While the CAN driver is in active mode a TXD DTO circuit prevents the local node from blocking network

communication in event of a hardware or software failure where TXD is held dominant longer than the time out

period t_{TXD_DTO}. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising edge is seen before

the time out constant of the circuit, t_{TXD_DTO}, expires the CAN driver is disabled releasing the bus lines to the

recessive level. This keeps the bus free for communication between other nodes on the network. The CAN driver

is re-activated on the next dominant to recessive transition on the TXD terminal, thus clearing the dominant time

out. The high-speed receiver and RXD terminal will reflect what is on the CAN bus during a TXD DTO fault. The

TS terminal in driven low during a TXD DTO fault.

Fault is repaired & transmission capability

restored

TXD fault stuck dominant: example PCB failure or bad software

t_{TXD_DTO}

TXD (driver)

Driver disabled freeing bus for other nodes

Normal CAN communication

Bus would be —stuck dominant“ blocking communication for the whole network but TXD DTO

prevents this and frees the bus for communication after the time t_{TXD_DTO}

.

CAN Bus Signal

t_{TXD_DTO}

Communication from other bus node(s)

Communication from repaired node

RXD (receiver)

Communication from local node

Communication from other bus node(s)

Communication from repaired local node

Figure 10-4. Timing Diagram for TXD DTO

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The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted

data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD)

for the worst case, where five successive dominant bits are followed immediately by an error frame. The

minimum transmitted data rate may be calculated using the minimum t_{TXD_DTO}time and the maximum number of

successive dominant bits (11 bits).

Minimum Data Rate = 11 bits / t_{TXD_DTO}= 11 bits / 1.2 ms = 9.2 kbps

(1)

10.3.13.2 Thermal Shutdown (TSD)

If the junction temperature of the TCAN1162x-Q1 exceeds the thermal shutdown threshold, T_J> T_SDR

,

the device transitions into fail-safe mode and disables the transceiver's transmitter and receiver blocking

transmission to and from the CAN bus. The TSD fault condition is cleared when the device junction temperature

falls below the thermal shutdown temperature threshold, T_J< T_SDF. If the fault condition that caused the TSD

fault is still present, the temperature may rise again and the device will enter thermal shutdown again. Prolonged

operation with a TSD fault conditions may affect device reliability.

10.3.13.3 Under/Over Voltage Lockout

The supply terminals implement undervoltage and over voltage detection circuitry. If an undervoltage is detected

the TCAN1162x-Q1 transitions into either reset or sleep mode depending on the undervoltage fault. An

undervoltage fault on V_IOcauses the SBC to transition into sleep mode while an undervoltage fault on the

integrated regulator causes the SBC to transition to reset mode. The SBC will remain in reset mode until the fault

condition on the regulator is cleared.

If the over voltage fault is detected the TCAN1162x-Q1 transitions into fail-safe mode. These mode changes

place the device in a known state which protect the system from unintended behavior. See Table 10-1

Table 10-1. Undervoltage / Over Voltage Lockout

Fault

UV_IO

TCAN11625

TCAN11623

Sleep mode

—

Sleep mode

UV_CCOUT

UV_FLT

Reset mode

—

Reset mode

—

UV_LDO3

OV_CCOUT

OV_FLT

—

Fail-safe mode

—

Fail-safe mode

OV_LDO3

10.3.13.4 Unpowered Devices

The device is designed to be an ideal passive or no load to the CAN bus if it is unpowered. The CANH and

CANL pins have low leakage currents when the device is un-powered so they present no load to the bus. This is

critical if some nodes of the network are unpowered while the rest of the of network remains in operation.

The logic terminals also have low leakage currents when the device is un-powered so they do not load down

other circuits which may remain powered.

10.3.13.5 Floating Terminals

The TCAN1162x-Q1 has internal pull-ups and pull-downs on critical pins to ensure a known operating behavior if

the pins are left floating.

The TXD pin is pulled up to V_IOwhich forces a recessive level if the pin floats. This internal bias should not be

relied upon by design but rather a fall-safe option. Special care needs to be taken when the devive is used with

a CAN controller that has open drain outputs. The device implements a weak internal pull-up resistor on the TXD

pin. The CAN bit timing for CAN FD data rates will require special consideration and the pull-up strength should

be considered carfully when using open drain outputs. An adequate external pull-up resistor must be used to

ensure that the TXD output of the CAN controller maintains adequate bit timing input to the CAN device.

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The nSLP pin is weakly pulled down which forces the device into the low-power sleep mode if the terminal is left

floating. See Table 10-2.

Table 10-2. Terminal Fail-Safe Biasing

TERMINAL

PULL-UP or PULL-DOWN

COMMENT

Weakly biases TXD toward recessive to prevent bus blockage or

TXD DTO triggering

TXD

Pull-up

Weakly biases the nSLP terminal towards low power sleep mode to

prevent excessive system power

nSLP

Pull-down

10.3.13.6 CAN Bus Short Circuit Current Limiting

The TCAN1162x-Q1 has several protection features that limit the short circuit current during dominant and

recessive when a CAN bus line is shorted. The device has TXD dominant state timeout which prevents

permanently having a higher short circuit current during a dominant state fault.

During CAN communication the bus switches between the dominant and recessive states, thus the short circuit

current may be viewed either as the current during each bus state or as a DC average current. The average

short circuit current should be used when considering system power for the termination resistors and common

mode choke. The percentage dominant is limited by the TXD dominant state timeout and CAN protocol which

has forced state changes and recessive bits such as bit stuffing, control fields, and interframe space. These

ensure that there is a minimum recessive time on the bus even if the data field contains a high percentage of

dominant bits.

The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short

circuit currents. The average short circuit current may be calculated using Equation 2.

I_OS(AVG)= %Transmit × [(%REC_Bits × I_{OS(SS)_REC}) + (%DOM_Bits × I_{OS(SS)_DOM})] + [%Receive × I_{OS(SS)_REC}

]

(2)

Where:

•

I_OS(AVG)is the average short circuit current

%Transmit is the percentage the node is transmitting CAN messages

%Receive is the percentage the node is receiving CAN messages

%REC_Bits is the percentage of recessive bits in the transmitted CAN messages

%DOM_Bits is the percentage of dominant bits in the transmitted CAN messages

I_{OS(SS)_REC}is the recessive steady state short circuit current

I_{OS(SS)_DOM}is the dominant steady state short circuit current

The short circuit current and possible fault cases of the network should be taken into consideration when sizing

the power ratings of the termination resistance and other network components.

10.3.13.7 Sleep Wake Error Timer

The sleep wake error (SWE) timer, t_INACTIVE, is a timer used to determine if specific external and internal

functions are working. The SWE timer starts when the device enters standby mode and only runs in standby

mode. A mode transistion stops the timer. If the timer times out while the device is in standby mode the RXD pin

will be pulled low to indicate an interrupt. The TCAN1162x-Q1 will transition to sleep mode.

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10.4 Device Functional Modes

The TCAN1162x-Q1 has six modes: normal, standby, sleep, reset, fail-safe, and off mode. Operating mode

selection is made via the nSLP input terminal in conjunction with supply conditions, temperature conditions, and

wake events.

V_LDO3< UV_LDO3

V_SUP< UV_SUPF

UV_LDO3

Or

Power Off

V_SUP> UV_SUPR

Reset

UV_FLT

nRST = high

T_J< T_SDF

&

V_FLT< OV_FLTF

&

V_LDO3< OV_LDO3F

nSLP = high &

V_IO> UV_IOR

1

T_J> T_SDR

Normal Mode³

1

Standby Mode

Fail-safe Mode

V_FLT> OV_FLTR

nSLP = low or

V_IO< UV_IOF

1

V_LDO3> OV_LDO3R

Wake-up event

nSLP = low for t > t_SLP

& nSLP was high at

some point since Reset

mode & V_IO> UV_IOF

2

t > t_INACTIVE

¹From any mode except sleep mode and off

²From standby mode

Sleep Mode

2

V_IO< UV_IOFfor t > t_UV(SLP)

³Normal mode is confirmed when the TS pin is high

Figure 10-5. TCAN11623 State Machine

Table 10-3. TCAN11623 Mode Overview

BLOCK

NORMAL

On

STANDBY

RESET

SLEEP

Off

FAIL-SAFE

Off

V_FLT

V_LDO3

On

Off

INH

Active

Off

Active

V_LDO3

Active

Low

Off

Low Power CAN RX

nRST

Active

Off

Active⁽¹⁾

V_LDO3

(1) In fail-safe mode wake-up events are ignored until all pending faults are cleared

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Reset event

V_SUP< UV_SUPF

Power Off

V_SUP> UV_SUPR

Reset

UV_CCOUT

nRST = high

T_J< T_SDF

&

V_CCOUT< OV_CCOUTF

nSLP = high &

V_IO> UV_IOR

1

T_J> T_SDR

Fail-safe Mode

Standby Mode

Normal Mode³

1

V_CCOUT> OV_CCOUTR

nSLP = low or

V_IO< UV_IOF

nSLP = low for t > t_SLP

& nSLP was high at

some point since reset

mode & V_IO> UV_IOF

Wake-up event

2

t > t_INACTIVE

¹From any mode except sleep mode and off

²From standby mode

Sleep Mode

2

V_IO< UV_IOFfor t > t_UV(SLP)

³Normal mode is confirmed when the TS pin is high

Figure 10-6. TCAN11625 State Machine

Table 10-4. TCAN11625 Mode Overview

BLOCK

V_CCOUT

NORMAL

On

STANDBY

RESET

SLEEP

Off

FAIL-SAFE

On

Off

INH

Active

Off

Active

V_CCOUT

Active

Low

Off

Low Power CAN RX

nRST

Active

Off

Active⁽¹⁾

V_CCOUT

(1) In fail-safe mode wake-up events are ignored until all pending faults are cleared.

10.4.1 Operating Mode Description

10.4.1.1 Normal Mode

This is the normal operating mode of the device. The CAN driver and receiver are fully operational and CAN

communication is bi-directional. The driver is translating a digital input on TXD to a differential output on CANH

and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD.

The t_INACTIVEtimer in not active in normal mode.

10.4.1.2 Standby Mode

Standby mode is a low power mode of the TCAN1162x-Q1 where the CAN transceiver is placed in the CAN

autonomous inactive state by asserting the nSLP pin low. In this mode the TS pin is driven low, the CAN

transmitter and receiver are switched off, the bus pins are biased to ground, and the transceiver cannot send or

receive data. While in standby mode the low power receiver actively monitors the CAN bus for a valid wake-up

pattern. If a valid wake-up pattern is received the CAN bus pins transition to the CAN autonomous active state

where CANH and CANL are internally biased to 2.5 V from the V_SUPpower rail. The reception of a valid wake-up

pattern generates a wake-up request by the CAN transceiver by latching the RXD output pin low. The WAKE pin

circuitry is active in standby mode and monitors the WAKE pin for either a high-to-low or low-to-high transition.

The INH pin is active in order to supply an enable to the system power supply.

The RXD output pin is asserted low while in standby mode if the a wake event or a fault is detected. Note that a

POR counts as a wake event and will also cause RXD to latch low.

In standby mode a fail-safe timer, t_INACTIVE, is enabled. The t_INACTIVEtimer add an additional layer of protection

by requiring the system controller to configure the TCAN1162x-Q1 to normal mode before it expires. This feature

forces the TCAN1162x-Q1 to transition to its lowest power mode, sleep mode, if the processor does not come up

properly.

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The TCAN11625 internal regulator, V_CCOUT, is active in standby mode.

The TCAN11623 internal regulators, V_FLTand V_LDO3, are active in standby mode.

Standby mode is not the lowest power mode of the device since the INH terminal and internal regulators are

active. This allows the rest of the system to operate normally.

10.4.1.3 Sleep Mode

Sleep mode is the lowest power mode of the TCAN1162x-Q1 where the CAN transceiver is placed in the CAN

autonomous inactive state by asserting the nSLP pin low for t > t_SLP. In sleep mode, the CAN transmitter

and receiver are switched off, the bus pins are biased to ground after t_SILENCEexpires, and the transceiver

cannot send or receive data. The INH pin is switched off in sleep mode causing any system power elements

controlled by INH to be switched off thus reducing system power consumption. While in sleep mode, the low

power receiver actively monitors the CAN bus for a valid wake-up pattern and the I_SUPcurrent is reduced to its

minimum level.

Sleep mode is entered if:

•

The nSLP pin is asserted low for t > t_SLP, there are no pending wake-up events, and V_IO> UV_VIOR

V_IO< UV_VIORfor t > t_UV(SLP)

•

SWE timer expires (see Sleep Wake Error Timer)

Sleep mode is exited if:

•

If a valid wake-up pattern (WUP) is received via the CAN bus pins

A local WAKE (LWU) event

A reset event occurs (goes to reset mode)

10.4.1.3.1 Remote Wake Request via Wake-Up Pattern (WUP)

The TCAN1162x-Q1 implements a low-power wake receiver in the standby and sleep mode that uses the

multiple filtered dominant wake-up pattern (WUP) defined in the ISO11898-2:2016 standard.

The wake-up pattern (WUP) consists of a filtered dominant bus, then a filtered recessive bus time followed by

a second filtered bus time. The first filtered dominant initiates the WUP and the bus monitor is now waiting on

a filtered recessive, other bus traffic do not reset the bus monitor. Once a filtered recessive is received, the bus

monitor is now waiting on a filtered dominant. The other bus traffic do not reset the bus monitor. Immediately

upon receiving of the second filtered dominant, the bus monitor recognizes the WUP and drives the RXD

terminal low, if a valid V_IOis present signaling to the controller the wake-up request. If a valid V_IOis not present

when the wake-up pattern is received the device drives the RXD output pin low once V_IO> UV_IOR

.

The WUP consists of:

•

A filtered dominant bus of at least t_{WK_FILTER}followed by

A filtered recessive bus time of at least t_{WK_FILTER}followed by

A second filtered dominant bus time of at least t_{WK_FILTER}

For a dominant or recessive to be considered “filtered”, the bus must be in that state for more than t_{WK_FILTER}

time. Due to variability in the t_{WK_FILTER}the following scenarios are applicable. Bus state times less than

t_{WK_FILTER(MIN)}are never detected as part of a WUP, and thus no wake request is generated. Bus state times

between t_{WK_FILTER(MIN)}and t_{WK_FILTER(MAX)}may be detected as part of a WUP, and a wake request may be

generated. Bus state times more than t_{WK_FILTER(MAX)}are always detected as part of a WUP, and thus a wake

request is generated. See Figure 10-7 for the timing diagram of the WUP.

The pattern and t_{WK_FILTER}time used for the WUP and wake request prevents noise and bus stuck dominant

faults from causing false wake requests while allowing any CAN or CAN FD message to initiate a wake request.

ISO11898-2:2016 has two sets of times for a short and long wake-up filter times. The t_{WK_FILTER}timing for the

TCAN1162x-Q1 has been picked to be within the min and max values of both filter ranges. This timing has been

chosen such that a single bit time at 500 kbps, or two back to back bit times at 1 Mbps triggers the filter in either

bus state.

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For an additional layer of robustness and to prevent false wake-ups, the device implements the t_{WK_TIMEOUT}

timer. For a remote wake-up event to successfully occur, the entire wake-up pattern must be received within the

timeout value. If a the full wake-up pattern is notreceived before the t_{WK_TIMEOUT}expires, then the internal logic

is reset and the device remains in sleep mode without waking up. The full pattern must then be transmitted again

within the t_{WK_TIMEOUT}window. See Figure 10-7.

Wake-Up Pattern (WUP) received in t < t_{WK_TIMEOUT}

Wake Request

Filtered

Dominant

Filtered

Dominant

Filtered

Recessive

Waiting for

Filtered

Dominant

Waiting for

Filtered

Recessive

Bus

Bus V_Diff

WUP Detect

Mode

≥ t_{WK_FILTER}

*

t_{INH_SLP_STB}

Sleep Mode

Standby Mode

*The RXD pin is only driven once V_IOis present.

Figure 10-7. Wake-Up Pattern (WUP) From Sleep Mode To Standby Mode

10.4.1.3.2 Local Wake-Up (LWU) via WAKE Input Terminal

The WAKE terminal is a bi-directional high-voltage reverse battery protected input which can be used for local

wake-up (LWU) requests via a voltage transition. A LWU event is triggered on either a low-to-high or high-to-low

transition since it has bi-directional input thresholds. The WAKE pin could be used with a switch to V_SUPor to

ground. If the terminal is unused, it should be pulled to V_SUPor ground to avoid unwanted parasitic wake-up

events.

Figure 10-8. WAKE Circuit Example

Figure 10-8 shows two possible configurations for the WAKE pin, a low-side and high-side switch configuration.

The objective of the series resistor, R_SERIES, is to protect the WAKE input of the device from over current

conditions that may occur in the event of a ground shift or ground loss. The minimum value of R_SERIEScan be

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calculated using the maximum supply voltage, V_SUPMAX, and the maximum allowable current of the WAKE pin,

I_IO(WAKE). R_SERIESis calculated using:

R_SERIES= V_SUPMAX/ I_IO(WAKE)

(3)

If the battery voltage never exceeds 42 V_DC, then the R_SERIESvalue is approximately 10 kΩ.

The R_BIASresistor is used to set the static voltage level of the WAKE input when the switch is not in use. When

the switch is in use in a high-side switch configuration, the R_BIASresistor in combination with the R_SERIESresistor

sets the WAKE pin voltage above the V_IHthreshold. The maximum value of R_BIAScan be calculated using

the maximum supply voltage, V_SUPMAX, the maximum WAKE threshold voltage V_IH, the maximum WAKE input

current I_IHand the series resistor value R_SERIES. R_BIASis calculated using:

R_BIAS< ((V_SUPMAX- V_IH) / I_IH) - R_SERIES

(4)

If the battery voltage never exceed 42 V_DC, then the R_BIASresistor value must be less than 650-kΩ.

The LWU circuitry is active in sleep modeand fail-safe mode.. If a valid LWU event occurs while the TCAN1162x-

Q1 is in sleep mode the device transitions to reset mode. If a valid LWU event occurs while the TCAN1162x-Q1

is in fail-safe mode the device transitions to reset mode given the other exit criteria from fail-safe mode have

been met. See the CAN Transceiver Modes section.

The WAKE circuitry is switched off normal mode.

WAKE

threshold

not

crossed

t

t_WAKE

t ≥ t_WAKE

wake-up

no wake-up

Wake

LWU Request

INH

RXD

Mode

Sleep Mode

Standby Mode

The RXD pin is only driven once V_IOis present.

Figure 10-9. LWU Request Rising Edge

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WAKE

threshold

not

t

t_WAKE

t ≥ t_WAKE

wake-up

no wake-up

crossed

Wake

LWU Request

INH

RXD

Mode

Sleep Mode

Standby Mode

The RXD pin is only driven once V_IOis present.

Figure 10-10. LWU Request Falling Edge

10.4.1.4 Reset Mode

Reset mode is a low power mode of the TCAN1162x-Q1 where the nRST pin is asserted low allowing the

controller to power up correctly. In this state the CAN transmitter and receiver are off, the bus pins are biased to

ground, and the transceiver cannot send or receive data.

While in reset mode the low power receiver actively monitors the CAN bus for a valid wake-up pattern. If a valid

wake-up pattern is received the CAN bus pins transition to the CAN autonomous active state where CANH and

CANL are internally biased to 2.5 V from the V_SUPpower rail. The reception of a valid wake-up pattern generates

a wake-up request by the CAN transceiver that is output to the RXD pin.

The TCAN1162x-Q1 will enter reset mode due to following conditions:

•

Power-on

nRST pulled low externally

The TCAN11625 will enter reset mode due to following conditions:

V_CCOUT< UV_VCCOUT

The TCAN11623 will enter reset mode due to following conditions:

V_FLT< UV_VFLT

•

The TCAN1162x-Q1 will enter reset mode upon clearing any of the following fault conditions and leaving fail-safe

mode:

•

T_J< T_SDF

Over voltage event

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10.4.1.5 Fail-safe Mode

Fail-safe mode is a low power mode in which the TCAN1162x-Q1 is in a protected state. While in fail-safe mode

the internal regulator (V_FLTV_CCOUT) is off, the INH pin is off, the reset pin is low, and the CAN transmitter and

receiver are off.

Fail-safe mode is entered if:

•

T_J> T_SDR

V_VCCOUT> OV_CCOUTR- TCAN11625

V_VFLT> OV_FLTR- TCAN11623

V_LDO3> OV_LDO3R- TCAN11623

Fail-safe mode is exited if all of the following criteria are met:

•

T_J< T_SDF

V_VCCOUT< OV_CCOUTF- TCAN11625

V_VFLT< OV_FLTF

V_LDO3> OV_LDO3F- TCAN11623

A valid wake-up event exists

If the fault condition is not cleared within t_INACTIVEthen the device will transition into it's lowest power mode,

sleep mode.

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10.4.2 CAN Transceiver

10.4.2.1 CAN Transceiver Operation

The TCAN1162x-Q1 CAN transverse has three modes of operation; CAN active, CAN autonomous active, and

CAN autonomous inactive.

10.4.2.2 CAN Transceiver Modes

The TCAN1162x-Q1 supports the ISO 11898-2:2016 CAN physical layer standard autonomous bus biasing

scheme. Autonomous bus biasing enables the transceiver to switch between CAN active, CAN autonomous

active, and CAN autonomous inactive which helps to reduce RF emissions.

CAN Active

CAN Transmitter: on

CAN Receiver: on

RXD: Mirrors CAN bus

CANH & CANL: V_FLT/2 (~2.5 V)

From any mode

V_SUP< UV_SUPF

T_J> T_SDR

CAN Off

CAN Transmitter: off

CAN Receiver: off

RXD: wake-up/high

CANH & CANL: floating

CAN Autonomous: Inactive

CAN Transmitter: off

CAN Receiver: off

RXD: wake-up/high

CANH & CANL: bias to GND

CAN Autonomous: Active

CAN Transmitter: off

CAN wake-up or (normal & (V_FLT< UV_FLTR) or (V_LDO3

UV_LDO3R) or V_IO< UV_VIOR

<

V_SUP> UV_SUPR

T_J< T_SDF

)

CAN Receiver: off

RXD: low signals wake-up¹

CANH & CANL: bias to 2.5 V from V_SUP

t > t_SILENCE& (fail-safe or standby or sleep)

¹Wake-up inactive in normal mode

Figure 10-11. TCAN11623 CAN Transceiver State Machine

CAN Active

CAN Transmitter: on

CAN Receiver: on

RXD: Mirrors CAN bus

CANH & CANL: V_CCOUT/2 (~2.5 V)

From any mode

V_SUP< UV_SUPF

T_J> T_SDR

CAN Off

CAN Transmitter: off

CAN Receiver: off

RXD: wake-up/high

CANH & CANL: floating

CAN Autonomous: Inactive

CAN Autonomous: Active

CAN Transmitter: off

CAN wake-up or (normal & (V_CCOUT< UV_CCOUTR) or (V_IO

UV_IOR))

<

CAN Transmitter: off

CAN Receiver: off

RXD: wake-up/high

V_SUP> UV_SUPR

T_J< T_SDF

CAN Receiver: off

RXD: low signals wake-up¹

CANH & CANL: bias to 2.5 V from V_SUP

t > t_SILENCE& (fail-safe or standby or sleep)

CANH & CANL: bias to GND

¹Wake-up inactive in normal mode

Figure 10-12. TCAN11625 CAN Transceiver State Machine

32

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10.4.2.2.1 CAN Off Mode

In CAN off mode the CAN transceiver is switched off and the CAN bus lines are truly floating. In this mode the

device presents no load to the CAN bus while preventing reverse currents from flowing into the device if the

battery or ground connection is lost.

The CAN off state is entered if:

•

T_J> T_SDR

V_SUP< UV_SUPF

The CAN transceiver switches between the CAN off state and CAN autonomous inactive mode if:

•

V_SUP> UV_SUPR

T_J< T_SDF

10.4.2.2.2 CAN Autonomous: Inactive and Active

When the CAN transceiver is in standby mode or sleep mode the CAN bias circuit is switched off and the

transceiver moves to the autonomous inactive state. In the autonomous inactive state the CAN pins are biased

to GND. When a valid wake-up event occurs the CAN bus is biased to 2.5 V. If the controller does not transition

the TCAN1162x-Q1 into normal mode before the t_SILENCEtimer expires, then the CAN biasing circuit is again

switched off and the CAN pins are biased to ground.

The CAN transceiver switches to the CAN autonomous mode if any of the following conditions are met:

•

The TCAN1162x-Q1 transitions from CAN off mode to CAN autonomous inactive

The TCAN1162x-Q1 transitions from normal mode to standby mode or fail-safe mode or sleep mode and t <

t_SILENCE

•

t > t_SILENCEand the TCAN1162x-Q1 transitions from normal mode to standby mode or fail-safe mode or sleep

mode

The TCAN1162x-Q1 transitions to reset mode

The CAN transceiver switches between the CAN autonomous inactive mode and CAN autonomous active mode

if:

•

A valid wake-up event

The TCAN1162x-Q1 transitions to normal mode and no undervoltage faults exist.

The CAN transceiver switches between the CAN autonomous active mode and CAN autonomous inactive mode

if:

•

t > t_SILENCEand the TCAN1162x-Q1 transitions to standby mode, sleep mode, or fail-safe mode.

10.4.2.2.3 CAN Active

When the TCAN1162x-Q1 is in normal mode the CAN transceiver is in active mode. The CAN driver and

receiver are fully operational and CAN communication is bi-directional. The CAN bias voltage in CAN active

mode is derived from:

•

V_CCOUT- TCAN11625

V_FLT- TCAN11623

The CAN transceiver switches between the CAN autonomous inactive or active mode and CAN active mode if:

The TCAN1162x-Q1 transitions to normal mode and no undervoltage faults exist.

•

The CAN transceiver blocks its transmitter and receiver after entering CAN active mode if the TXD pin is

asserted low before leaving standby mode. This prevents disruptions to CAN bus in the event that the TXD pin

has a TXD DTO fault.

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10.4.2.3 Driver and Receiver Function Tables

Table 10-5. Driver Function Table

BUS OUTPUTS

DEVICE MODE

TXD INPUTS⁽¹⁾

DRIVEN BUS STATE⁽²⁾

CANH

CANL

Low

High

Low

Dominant

Normal

Biased to V_CCOUT/2 (TCAN11625)

V_FLT/2 (TCAN11623)

High or Open

High impedance

Standby

Sleep

x

High impedance

Biased to GND

(1) x = irrelevant

(2) For bus states and typical bus voltages see Figure 10-13

Table 10-6. Receiver Function Table

CAN DIFFERENTIAL INPUTS

DEVICE MODE

BUS STATE

RXD TERMINAL

V_ID= V_CANH– V_CANL

V_ID≥ 0.9 V

Dominant

Indeterminate

Recessive

Open

Low

Indeterminate

High

0.5 V < V_ID< 0.9 V

V_ID≤ 0.5 V

Normal

Open (V_ID≈ 0 V)

V_ID≥ 1.15 V

High

Dominant

Indeterminate

Recessive

Open

0.5 V < V_ID< 1.15 V

V_ID≤ 0.4 V

High

Standby

Low if wake-up event persists

Open (V_ID≈ 0 V)

V_ID≥ 1.15 V

Dominant

Indeterminate

Recessive

Open

High

0.4 V < V_ID< 1.15 V

V_ID≤ 0.4 V

Low if wake-up event persists and V_IOis

present.

Tri-state if V_IOor V_SUPare not present

Sleep

Open (V_ID≈ 0 V)

10.4.2.4 CAN Bus States

The CAN bus has two logical states during operation: recessive and dominant. See Figure 10-13.

A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD

and RXD pins. A recessive bus state occurs when the bus is biased to one half of the CAN transceiver supply

voltage via the high resistance internal input resistors (R_IN) of the receiver and corresponds to a logic high on the

TXD and RXD pins.

A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a

dominant bit at the same time during arbitration, and in this case the differential voltage of the CAN bus will be

greater than the differential voltage of a single CAN driver. The TCAN1162x-Q1 CAN transceiver implements

low-power standby and sleep modes which enables a third bus state where the bus pins are biased to ground

via the high resistance internal resistors of the receiver.

34

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Standby Mode

Normal Mode

CANH

V_DIFF

CANL

Recessive

Dominant

Recessive

Time, t

Figure 10-13. Bus States

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11 Application Information

11.1 Application Information Disclaimer

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

11.2 Typical Application

EN

3.3V Voltage Regulator

(e.g. TPSxxxx)

Motor Driver

V_BAT

0.1ꢀF

10ꢀF

3.3kΩ

33kΩ

V_SUP

10

V_IO

V_LDO5

5

3

0.1nF

9

7

WAKE

CANH

V_IN

13

INH

TCAN11625

nSLP

TS

14

6

CAN FD

Controller

nRST

TXD

11

1

CANL

12

Optional:

Terminating

Node

RXD

4

Optional:

Filtering,

Transient and

ESD

2

GND

Figure 11-1. Typical Application

36

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EN

5V Voltage Regulator

(e.g. TPSxxxx)

Sensor or Second

CAN FD Controller

V_BAT

10

F

0.1

F

0.1

F

10 F

3.3k

33k

V_LDO3

V_SUP

10

V_IO

V_FLT

8

5

3

0.1nF

9

7

WAKE

INH

CANH

V_IN

13

TCAN11623

nSLP

TS

14

6

CAN FD

Controller

nRST

TXD

11

1

CANL

12

Optional:

Terminating

Node

RXD

4

Optional:

Filtering,

Transient and

ESD

2

GND

Figure 11-2. Typical Application

11.2.1 Design Requirements

11.2.1.1 Bus Loading, Length and Number of Nodes

A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3 m.

However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a

bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN1162x-Q1

Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO

11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loading

of the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE

J2284, SAE J1939, and NMEA 2000.

A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification the driver

differential output is specified with a bus load that can range from 50 Ω to 65 Ω where the differential output

must be greater than 1.5 V. The TCAN1162x-Q1 is specified to meet the 1.5-V requirement down to 50 Ω

and is specified to meet 1.4-V differential output at 45Ω bus load. The differential input resistance of the

TCAN1162x-Q1 is a minimum of 40 kΩ. If 100 TCAN1162x-Q1 devices are in parallel on a bus, this is equivalent

to a 400-Ω differential load in parallel with the nominal 60 Ω bus termination which gives a total bus load of

approximately 52 Ω. Therefore, the TCAN1162x-Q1 theoretically supports over 100 devices on a single bus

segment. However, for CAN network design margin must be given for signal loss across the system and cabling,

parasitic loadings, timing, network imbalances, ground offsets and signal integrity thus a practical maximum

number of nodes is often lower. Bus length may also be extended beyond 40 meters by careful system design

and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1 km

with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.

This flexibility in CAN network design is one of the key strengths of the various extensions and additional

standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility

the CAN network system designer must take the responsibility of good network design to ensure robust network

operation.

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11.2.2 Detailed Design Procedures

11.2.2.1 CAN Termination

Termination may be a single 120-Ω resistor at the end of the bus on either the cable or in a terminating node.

If filtering and stabilization of the common mode voltage of the bus is desired then split termination may used,

see Figure 11-3. Split termination improves the electromagnetic emissions behavior of the network by filtering

higher-frequency common-mode noise that may be present on the differential signal lines..

Standard Termination

Split Termination

CANH

R_TERM/2

R_TERM

TCAN Transceiver

C_SPLIT

R_TERM/2

CANL

Figure 11-3. CAN Bus Termination Concepts

11.3 Application Curves

3

-40 C

50 C

150 C

2.75

2.5

2.25

2

1.75

1.5

4

6

8

10 12 14 16 18 20 22 24 26 28

V_SUP(V)

R_L= 60 Ω

Figure 11-4. V_OD(D)over V_SUP

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12 Power Supply Requirements

The TCAN1162x-Q1 is designed to operate from a V_SUPinput supply voltage range between 5.5 V and 28 V.

The TCAN1162x-Q1 also has an output level shifting supply input, V_IO, designed for a range between 1.7 V and

5.5 V. Input supplies must be well regulated. A bypass capacitance, typically 100 nF, should be placed close

to the device V_SUPand V_IOsupply pins. This helps to reduce supply voltage ripple present on the outputs of

the switched-mode power supplies and also helps to compensate for the resistance and inductance of the PCB

power planes and traces.

The TCAN11625 integrates a 5-V LDO to supply the CAN transceiver as well as additional external loads. The

V_CCOUTpin requires a 10 µF capacitance.

The TCAN11623 integrates a 5-V LDO to supply the CAN transceiver and a 3.3-V LDO for additional external

loads. The V_FLTpin requires a 10 µF capacitance and the V_LDO3pin typically uses a capacitance value of 4.7uF.

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13 Layout

13.1 Layout Guidelines

Place the protection and filtering circuitry as close to the bus connector to prevent transients, ESD and noise

from propagating onto the board. The layout example provides information on components around the device

itself. Transient voltage suppression (TVS) device can be added for extra protection. The production solution can

be either bi-directional TVS diode or varistor with ratings matching the application requirements. This example

also shows optional bus filter capacitors.

Design the bus protection components in the direction of the signal path. Do not force the transient current

to divert from the signal path to reach the protection device. Use supply and ground planes to provide low

inductance.

Note

A high-frequency current follows the path of least impedance and not the path of least resistance.

Use at least two vias for supply and ground connections of bypass capacitors and protection devices to minimize

trace and via inductance.

•

Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver.

Bus termination: this layout example shows split termination. This is where the termination is split into two

resistors with the center or split tap of the termination connected to ground via capacitor. Split termination

provides common mode filtering for the bus. When bus termination is placed on the board instead of directly

on the bus, additional care must be taken to ensure the terminating node is not removed from the bus thus

also removing the termination.

13.2 Layout Example

CAN Controller

To V_IO

RES

CAN Controller

TXD

GND

V_FLT

RXD

V_IO

nSLP

CANH

CANL

nRST

V_SUP

RES

CAP

ESD

Connector

CAN Controller

To V_IO

RES

V_BAT

CAN Controller

Regulator EN

TS

WAKE

V_LDO3

RES

INH

CAP

CAN Controller

Figure 13-1. TCAN11623 Example Layout

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CAN Controller

To V_IO

RES

CAN Controller

TXD

GND

V_CCOUT

RXD

V_IO

nSLP

CANH

CANL

nRST

V_SUP

RES

CAP

ESD

Connector

CAN Controller

RES

To V_IO

V_BAT

CAN Controller

Regulator EN

TS

WAKE

NC

RES

INH

Figure 13-2. TCAN11625 Example Layout

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14 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,

generate code, and develop solutions are listed below.

14.1 Documentation Support

14.1.1 Related Documentation

14.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

14.3 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

14.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

14.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

14.6 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

42

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PACKAGE MATERIALS INFORMATION

www.ti.com

19-Dec-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TCAN11623DMTRQ1

TCAN11625DMTRQ1

VSON

DMT

14

3000

330.0

12.4

3.3

4.8

1.2

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Dec-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TCAN11623DMTRQ1

TCAN11625DMTRQ1

VSON

DMT

14

3000

367.0

35.0

Pack Materials-Page 2

GENERIC PACKAGE VIEW

DMT 14

3 x 4.5, 0.65 mm pitch

VSON - 0.9 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225088/A

www.ti.com

PACKAGE OUTLINE

DMT0014B

VSON - 1 mm max height

SCALE 3.200

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

A

B

PIN 1 INDEX AREA

4.6

4.4

0.1 MIN

(0.13)

1.0

0.8

SECTION A-A

SCALE 30.000

SECTION A-A

TYPICAL

C

SEATING PLANE

0.08 C

0.05

0.00

1.6 0.1

SYMM

EXPOSED

THERMAL PAD

(0.2) TYP

7

8

(0.19) TYP

A

2X

3.9

15

SYMM

4.2 0.1

14

1

12X 0.65

0.35

0.25

14X

0.45

0.35

PIN 1 ID

14X

0.1

C A B

(OPTIONAL)

0.05

C

4225087/B 01/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DMT0014B

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.6)

14X (0.6)

14X (0.3)

SYMM

1

14

2X

(1.85)

12X (0.65)

SYMM

15

(4.2)

(0.69)

TYP

(

0.2) VIA

TYP

8

7

(R0.05) TYP

(0.55) TYP

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225087/B 01/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DMT0014B

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.47)

15

14X (0.6)

1

14

14X (0.3)

(1.18)

12X (0.65)

SYMM

(1.38)

(R0.05) TYP

METAL

TYP

8

7

SYMM

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 15

77.4% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

4225087/B 01/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TCAN11623-Q1_V01
厂家：	TEXAS INSTRUMENTS
描述：	TCAN1162x-Q1 Automotive CAN FD System Basis Chip with Sleep Mode and LDO Output
文件：	总51页 (文件大小：2840K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TCAN11623-Q1_V01 [TI]

相关型号：

TCAN11623DMTRQ1

TCAN11625-Q1

TCAN11625DMTRQ1

TCAN1162DMTRQ1

TCAN1162X-Q1

TCAN1164-Q1

TCAN1164DMTRQ1

TCAN1164TDMTRQ1

TCAN1167-Q1

TCAN1167DMTRQ1

TCAN1462-Q1

TCAN1462DRBRQ1