TFP7401 [TI]

SPECIALTY CONSUMER CIRCUIT, PQFP100, TQFP-100;


型号：	TFP7401
厂家：	TEXAS INSTRUMENTS
描述：	SPECIALTY CONSUMER CIRCUIT, PQFP100, TQFP-100 商用集成电路
文件：	总7页 (文件大小：130K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SLDS126 – APRIL 2001

Mini-LVDS Intra-Panel Interface for Low

Power and Low EMI

Optional EEPROM Allows Fine Tuning in

Development and Production

Environments

Drives TI Mini-LVDS Source Drivers at 292

Mbps With a 146 MHz Clock

Narrow 4 Pair Differential Source Driver

Bus Minimizes Width of PCB

6-Bits LVDS Video System Interface

(FlatLinK )

Failure Detection of Input Clock With

Default Source Driver Control Generation

Support Both 2 Level and 3 Level Gate

Drivers

CMOS 3.3 V Technology

Ability to Drive SXGA+/UXGA TFT-LCD

System

description

This panel timing controller consists of FlatLink, mini-LVDS and a TFT-LCD timing controller. It resides on the

TFT-LCD module and provides interface timing control between graphics or video controllers and a TFT LCD

system. FlatLink, a low power, low EMI (electromagnetic Interference) LVDS interface, is used between this

controller and the host system. A mini-LVDS intra-panel interface is used between the timing controller and

source drivers.

Programmable outputs provide a mini-LVDS source driver and 2/3 level gate driver control. This timing controller

is configured via metal mask initialization value or an optional external serial EEPROM.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FlatLink is a trademark of Texas Instruments.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆ

ꢇ ꢈꢉ ꢊꢋ ꢌ ꢍ ꢈ ꢉꢊ ꢀ ꢁꢀ ꢎꢏ ꢐ ꢂꢊꢑ ꢒꢎ ꢀꢓ ꢔ ꢓ ꢑꢉ ꢏꢕ ꢑꢀ ꢖꢕ ꢎ ꢎꢒ ꢖ

ꢗꢓ ꢀ ꢘ ꢔ ꢓꢑ ꢓ ꢙꢎꢚꢐ ꢇ ꢊꢑ ꢐ ꢁꢎ ꢊꢀꢎ ꢓ ꢑꢛ

SLDS126 – APRIL 2001

pin assignment

TQFP PACKAGE

(TOP VIEW)

VSS

TP1

POL

VDD

VSS

TXVSS

LLV0P

LLV0M

TXVDD

LLV1P

LLV1M

TXVSS

LCLKP

LCLKM

TXVDD

LLV2P

LLV2M

TXVSS

LLV3P

LLV3M

TXVDD

LLV4P

LLV4M

TXVSS

VSS

RCLKIN

RCLKOUT1

RCLKOUT2

VDD

CPV

STVA

STVB

SCL

SDA

XAGING

VSS

VDD

CEXT

TEST

E UPDATE

VDDA

VSSA

VDD

PGM1

VSS

100

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅ ꢆ

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SLDS126 – APRIL 2001

system diagram

VDD

VSS

Panel Power

Supply

FlatLink

and

Serial

EEPROM

Mini-LVDS

Timing

Gray Scale

Reference

Controller

Reference Voltages

Mini-LVDS Bus (Left Half)

Mini-LVDS Bus (Right Half)

Mini-LVDS

Source

Driver

Mini-LVDS

Source

Driver

Mini-LVDS

Source

Driver

Mini-LVDS

Source

Driver

Start Pulse

Gate

Driver

1600 x 1200

TFT-LCD Array

Gate

Driver

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLDS126 – APRIL 2001

block diagram

(Data Pair)

SXGA+ : 4 Pair x 2

UXGA : 5 Pair x 2

ERXIN

3 Pair

1 Pair

Data

Alignment

Mini-LVDS

Transmitter

ERXCLK

(Clock Pair)

2 Pair

FlatLink

ORXIN

3 Pair

TP1, POL

Timing

Source Driver

Generator

Control Timings

ORXCLK 1 Pair

XRESET, CEXT,

ENVDET, PGM1,

XAGING, TEST,

STVA, STVB

CPV

Control

Logic

Fail-Safe

Circuit

Gate Driver

Control Timings

E UPDATE, R1,

RCLKIN,

RCLKOUT1,

RCLKOUT2

SCL

SDA

T1, T2

EEPROM

Serial

Interface

Power

Down

Detector

DC/DC

Converter

Control

detailed description

FlatLink receiver

The core of the FlatLink is TI’s original 82A LVDS receiver, which has three data channels for 18-bit color and

one clock channel. The receiver block supports up to dual LVDS bus.

data alignment and mini-LVDS transmitter

The data alignment block supports dual mini-LVDS bus configuration. The controller arranges pixel data and

distributes them to left half and right half drivers.

The mini-LVDS source drivers latch data on both positive and negative edges of the clock.

timing control

These blocks generate control to source drivers, gate drivers, and power supply. Both two and three level gate

drivers are supported.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLDS126 – APRIL 2001

detailed description (continued)

serial EEPROM interface

This block controls controller initialization. At power-up, the controller configures the internal programmable

registers with data from the EEPROM.

If there is no acknowledge signal of 7 bit device select code and 1 bit read/xwrite designator (indicating EEPROM

not present), internal ROM values are used to initialize the controller.

fail-safe circuit

The controller detects the off-spec control timing from the host. The controller has a self-oscillator circuit used

for the off-spec timing detection. If the off-spec condition is detected, this circuit generates the default video

stream and control timing to the source drivers and gate drivers. This function prevents biasing dc voltage to

the LCD panel.

pin description

system interface

SYMBOL

PIN COUNT

TYPE

FUNCTION

FlatLink data differential pair 0 input

ERX0P/M

LVDS Rx

ERX1P/M

FlatLink data differential pair 1 input

FlatLink data differential pair 2 input

FlatLink clock differential pair input

FlatLink data differential pair 0 input

FlatLink data differential pair 1 input

FlatLink data differential pair 2 input

FlatLink clock differential pair input

ERX2P/M

ERXCLKP/M

ORX0P/M

ORX1P/M

ORX2P/M

ORXCLKP/M

mini-LVDS source driver interface

SYMBOL

LLV0P/M

PIN COUNT

TYPE

FUNCTION

Left half mini-LVDS data differential pair 0

Left half mini-LVDS data differential pair 1

Left half mini-LVDS data differential pair 2

Left half mini-LVDS data differential pair 3

Left half mini-LVDS data differential pair 4

Left half mini-LVDS Clock differential pair

Right half mini-LVDS data differential pair 0

Right half mini-LVDS data differential pair 1

Right half mini-LVDS data differential pair 2

Right half mini-LVDS data differential pair 3

Right half mini-LVDS data differential pair 4

Right half mini-LVDS Clock differential pair

Horizontal syncronous output

LLV1P/M

LLV2P/M

LLV3P/M

LLV4P/M

LCLKP/M

RLV0P/M

RLV1P/M

RLV2P/M

RLV3P/M

RLV4P/M

RCLKP/M

TP1

Output

POL

Polarity inversion output

gate driver interface

SYMBOL

PIN COUNT

TYPE

Output

FUNCTION

Sift clock for gate driver

CPV

STVA, STVB

Start pulse output to gate driver

Gate driver output enable

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆ

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SLDS126 – APRIL 2001

pin description (continued)

EEPROM interface

SYMBOL

PIN COUNT

TYPE

I/O

FUNCTION

I C serial clock

SCL

SDA

I C serial data

I/O

control signal

SYMBOL

T1, T2

PIN COUNT

TYPE

output

Input

I/O

DC/DC converter control

Reset pin

XRESET

ENVDET

CEXT

Enable on-chip power down detector

Delay time control at power up

Self-oscillation for fail-safe circuit

Aging test mode pin

RCLKIN

RCLKOUT1

RCLKOUT2

XAGING

I/O

Input

I/O

E UPDATE

EEPROM update mode control

Mini-LVDS PLL low pass filter

Mini-LVDS output voltage control

Select default program 1 or 2

Test pin

Input

PGM1

TEST

power supply

SYMBOL

LVDSVDD

LVDSVSS

PLLVDD

PLLVSS

TXVDD

PIN COUNT

TYPE

Power

Ground

Power

Ground

Power

Ground

Power

Ground

Power

Ground

FUNCTION

FlatLink power

FlatLink ground

FlatLink PLL power

FlatLink PLL ground

Mini-LVDS power

Mini-LVDS ground

Mini-LVDS PLL power

Mini-LVDS PLL ground

Digital power

TXVSS

VDDA

VSSA

VDD

VSS

Digital ground

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its products to the specifications applicable at the time of sale in accordance with

TI’sstandardwarranty. TestingandotherqualitycontroltechniquesareutilizedtotheextentTIdeemsnecessary

to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except

those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

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Also see: Standard Terms and Conditions of Sale for Semiconductor Products. www.ti.com/sc/docs/stdterms.htm

Mailing Address:

Texas Instruments

Post Office Box 655303

Dallas, Texas 75265

TFP7401 [TI]

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TFPR-QTB1FA-2714-92-TR70