THS1031IPWR [TI]
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, GREEN, PLASTIC, TSSOP-28, Analog to Digital Converter;
| 型号： | THS1031IPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, GREEN, PLASTIC, TSSOP-28, Analog to Digital Converter 转换器 |
| 文件： | 总26页 (文件大小：359K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
28-PIN TSSOP/SOIC PACKAGE
(TOP VIEW)
10-Bit Resolution 30 MSPS
Analog-to-Digital Converter:
Configurable Input Functions:
– Single-Ended
– Single-Ended With Analog Clamp
– Single-Ended With Programmable Digital
Clamp
AGND
AV
DD
1
28
27
26
25
24
23
22
21
20
19
18
DV
AIN
V
2
DD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
3
REF
REFBS
4
REFBF
5
– Differential
MODE
6
Built-in Programmable Gain Amplifier
(PGA)
REFTF
7
REFTS
8
Differential Nonlinearity: ±0.3 LSB
Signal-to-Noise: 56 dB
CLAMPIN
CLAMP
REFSENSE
9
10
11
Spurious Free Dynamic Range: 60 dB
Adjustable Internal Voltage Reference
Straight Binary/2s Complement Output
Out-of-Range Indicator
I/O9 12
OVR 13
17 WR
16 OE
15 CLK
DGND 14
Power-Down Mode
description
The THS1031 is a CMOS, low power, 10-bit, 30 MSPS analog-to-digital converter (ADC) that can operate with
a supply range from 2.7 V to 3.3 V. The THS1031 has been designed to give circuit developers more flexibility.
The analog input to the THS1031 can be either single-ended or differential. This device has a built-in clamp
amplifier whose clamp input level can be selected from an external dc source or from an internal high-precision
10-bit digital clamp level programmable via an internal CLAMP register. A 3-bit PGA is included to maintain SNR
for small signal. The THS1031 provides a wide selection of voltage reference to match the user’s design
requirements. For more design flexibility, the internal reference can be bypassed to use an external reference
to suit the dc accuracy and temperature drift requirements of the application. The out-of-range output is used
to monitor any out-of-range condition in THS1031’s input range. The format of digital output can be coded in
either straight binary or 2s complement.
The speed, resolution, and single-supply operation of the THS1031 are suited for applications in set-top-box
(STB), video, multimedia, imaging, high-speed acquisition, and communications. The built-in clamp function
allows dc restoration of video signal and is suitable for video application. The speed and resolution ideally suit
charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and
camcorders. A wide input voltage range between REFBS and REFTS allows the THS1031 to be applied in both
imaging and communications systems
The THS1031I is characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
28-TSSOP (PW)
THS1031CPW
THS1031IPW
28-SOIC (DW)
THS1031CDW
THS1031IDW
0°C to 70°C
–40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
functional block diagram
Power
Down
CLAMP
DAC
10
CLAMPIN
WR
CTL
REG
SW2
CLAMP
SW1
BIN/2’S
3
AIN
Output
Buffers
I/O0 –
I/O9
SHA
PGA
A/D
REFTS
DAC
REF
REFBS
MODE
OVR
OE
DC
REF
SW3
Timing
Circuit
REFTF
REFBF
VBG
SW4
REFSENSE
V
REF
CLK
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
Terminal Functions
TERMINAL
NAME
AGND
AIN
AV
I/O
DESCRIPTION
NO.
1
I
I
I
I
I
I
I
I
Analog ground
Analog input
27
28
19
20
15
14
2
Analog supply
DD
CLAMP
CLAMPIN
CLK
HI to enable CLAMP mode, LO to disable CLAMP mode
Connect to an external analog clamp reference input.
Clock input
DGND
Digital ground
DV
Digital driver supply
DD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
3
4
5
6
7
8
9
10
11
12
Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4
Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8
Digital I/O bit 9 (MSB)
I/O
MODE
OE
23
16
13
25
24
18
22
21
26
17
I
Mode input
I
HI to the 3-state data bus, LO to enable the data bus
Out-of-range indicator
OVR
O
REFBS
REFBF
I
Reference bottom sense
I
Reference bottom decoupling
Reference sense
REFSENSE
REFTF
I
I
Reference top decoupling
REFTS
I
I/O
I
Reference top sense
V
REF
WR
Internal and external reference for ADC
Write strobe goes HI to write data value D0:D9 to the internal registers.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage: AV
to AGND, DV
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 6.5 V
DD
DD
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 0.3 V
AV to DV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6.5 to 6.5 V
DD
DD
Mode input MODE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to AV
Reference voltage input range REFTF, REFTB, REFTS, REFBS to AGND . . . . . . . . . –0.3 to AV
Analog input voltage range AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to AV
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
DD
DD
DD
DD
DD
DD
DD
DD
Reference input V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to AV
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to AV
REF
Reference output V
REF
Clock input CLK to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to AV
Digital input to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to DV
Digital output to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to DV
Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 150°C
Storage temperature range, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
STG
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
digital inputs
MIN NOM
MAX
UNIT
V
High-level input voltage, V
IH
2.4
Low-level input voltage, V
0.2 x DV
V
IL
DD
analog inputs
MIN NOM
MAX
REFTS
2
UNIT
Analog input voltage, V
I(AIN)
REFBS
V
V
V
V
V
Reference input voltage, V
Reference input voltage, V
Reference input voltage, V
1
I(VREF)
I(REFTS)
1
0
AV
DD
AV –1
DD
I(REFBS)
Clamp input voltage, V
REFBS
REFTS
I(CLAMPIN)
power supply
MIN NOM
2.7
2.7
MAX
UNIT
AV
DD
3
5.5
5.5
Supply voltage
Maximum sampling rate = 30 MSPS
V
DV
3
DD
REFTS, REFBS reference voltages (MODE = AV
)
DD
PARAMETER
MIN
TYP
MAX
AV
UNIT
V
REFTS
REFBS
Reference input voltage (top)
1
0
1
DD
Reference input voltage (bottom)
Differential input (REFTS – REFBS)
Switched input capacitance on REFTS
Switched input capacitance on REFBS
AV –1
DD
V
2
V
0.6
0.6
pF
pF
sampling rate and resolution
PARAMETER
MIN NOM
MAX
UNIT
MHz
Bits
Fs
5
30
Resolution
10
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
electrical characteristics, AV
input span from 0.5 V to 2.5 V, external reference, PGA = 1X, T = –40°C to 85°C (unless otherwise
noted)
= 3 V, DV
= 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AV , 2 V
DD
DD DD
A
analog inputs
PARAMETER
MIN
TYP
MAX
UNIT
V
V
I(AIN)
Analog input voltage
REFBS
REFTS
C
Switched input capacitance
Full power BW (–3 dB)
1.2
150
100
pF
I
FPBW
MHz
µA
DC leakage current (input = ±FS)
REFTF, REFBF reference voltages
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2
UNIT
Differential input (REFTF – REFBF)
1
1.3
2
V
AV
AV
AV
AV
AV
AV
AV
AV
AV
AV
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
1.5
2.5
2
1.7
3
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
Input common mode (REFTF + REFBF)/2
V
V
V
V
V
REF
V
REF
V
REF
V
REF
= 1 V
= 2 V
= 1 V
= 2 V
3
REFTF (MODE = AV
REFBF (MODE = AV
)
DD
2.5
3.5
1
0.5
2
)
DD
V
1.5
600
Input resistance between REFTF and REFBF
Ω
V
reference voltages
REF
PARAMETER
MIN
0.95
1.90
1
TYP
1
MAX
1.05
2.10
2
UNIT
V
Internal 1 V reference (REFSENSE = V
)
REF
Internal 2 V reference (REFSENSE = AV
)
2
V
SS
)
External reference (REFSENSE = AV
Reference input resistance
V
DD
18
kΩ
dc accuracy
PARAMETER
MIN
TYP
±1
MAX
±2
UNIT
LSB
LSB
INL
Integral nonlinearity
DNL
Differential nonlinearity
Offset error
±0.3
0.4
±1
1.4 %FSR
3.5 %FSR
Gain error
1.4
Missing code
No missing code assured
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
electrical characteristics, AV
input span from 0.5 V to 2.5 V, external reference, PGA = 1X, T = –40°C to 85°C (unless otherwise
noted) (continued)
= 3 V, DV
= 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AV , 2 V
DD
DD DD
A
dynamic performance (ADC and PGA)
PARAMETER
TEST CONDITIONS
MIN
TYP
9
MAX
UNIT
f = 3.5 MHz
8.2
f = 3.5 MHz, AV
f = 15 MHz
= 5 V
= 5 V
= 5 V
= 5 V
= 5 V
= 5 V
= 5 V
= 5 V
= 5 V
= 5 V
8.8
7.7
7.64
60
DD
ENOB
SFDR
THD
Effective number of bits
Bits
f = 15 MHz, AV
f = 3.5 MHz
DD
55
f = 3.5 MHz, AV
f = 15 MHz
63
DD
Spurious free dynamic range
Total harmonic distortion
Signal-to-noise
dB
dB
dB
dB
48
f = 15 MHz, AV
f = 3.5 MHz
52.4
DD
–58.2 –54.7
f = 3.5 MHz, AV
f = 15 MHz
–68.7
–47
–51.9
56
DD
f = 15 MHz, AV
f = 3.5 MHz
DD
51.2
51.1
f = 3.5 MHz, AV
f = 15 MHz
55
DD
SNR
53
f = 15 MHz, AV
f = 3.5 MHz
49.3
56
DD
f = 3.5 MHz, AV
f = 15 MHz
55
DD
SINAD Signal-to-noise and distortion
48.1
47.7
f = 15 MHz, AV
DD
PGA
PARAMETER
MIN
TYP
0.5
3
MAX
UNIT
Gain range (linear scale)
Gain step size (linear scale)
Gain error from nominal
Number of control bits
0.5
4
V/V
3%
Bits
clamp DAC
PARAMETER
MIN
TYP
10
MAX
UNIT
Resolution
Bits
DAC output range
REFBF
0.1
REFTF
Clamping analog output voltage range
Clamping analog output voltage error
AV –0.1
DD
V
– 40
+ 40
mV
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
electrical characteristics, AV
input span from 0.5 V to 2.5 V, external reference, PGA = 1X, T = –40°C to 85°C (unless otherwise
noted) (continued)
= 3 V, DV
= 3 V, Fs = 30 MSPS/50% duty cycle, MODE = AV , 2 V
DD
DD DD
A
clock
PARAMETER
MIN
33
TYP
MAX
UNIT
ns
t
t
t
t
Clock period
CK
CKH
CKL
d
Pulse duration, clock high
Pulse duration, clock high
Clock to data valid
Pipeline latency
15
16.5
16.5
ns
15
ns
25
ns
3
4
2
Cycles
ns
t
Aperture delay
(ap)
Aperture uncertainty (jitter)
ps
timing
PARAMETER
MIN
0
TYP
MAX
20
UNIT
ns
t
t
t
t
t
t
t
Output disable to high-Z output
Output enable to output valid
Output disable to write enable
Output disable to write enable
Write pulse
(PZ)
0
20
ns
(DEN)
(OEW)
(WOE)
(WP)
(DS)
12
12
15
5
ns
ns
ns
Input data setup time
ns
Input data hold time
5
ns
(DH)
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
30.6
94
MAX
45
UNIT
I
Operating supply current
AV
AV
AV
AV
= 3 V, MODE = AGND
mA
CC
DD
DD
DD
DD
= DV
= DV
= DV
= 3 V
135
DD
DD
DD
P
Power dissipation
mW
mW
D
= 5 V
160
3
P (STBY) Standby power
= 3 V, MODE = AGND
5
D
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
OE
(See Note A)
t
(WP)
t
t
(WOE)
(OEW)
WE
t
t
(DZ)
(DH)
(DS)
t
t
(DEN)
hi–Z
hi–Z
Output
Input
Output
I/O
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 1. Write Timing Diagram
Sample 2
Sample 3
Sample 1
Sample 5
Sample 4
Analog Input
t C
( K)
t
(CKL)
t
(CKH)
Input Clock
(See
Note A)
t
d
Pipeline Latency
Digital Output
Sample 1
Sample 2
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 2. Digital Output Timing Diagram
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
SAMPLING FREQUENCY
96
94
92
90
88
86
84
82
AV
DD
= DV
= 3.5 MHz
= 3 V
DD
F
in
T
= 25°C
A
5
10
15
20
25
30
f
– Sampling Frequency – MHz
s
Figure 3
EFFECTIVE NUMBER OF BITS
vs
TEMPERATURE
10.0
9.5
9.0
8.5
8.0
7.5
7
AV
= DV
= 3 V
DD
DD
= 3.5 MHz
F
F
in
= 30 MSPS
s
–40
–15
10
35
60
85
Temperature – °C
Figure 4
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
FREQUENCY
10.0
9.5
9.0
8.5
8.0
7.5
7
AV
DD
= DV
= 3.5 MHz
= 3 V
DD
F
in
T
= 25°C
A
5
10
15
20
25
30
f
– Sampling Speed – MSPS
s
Figure 5
EFFECTIVE NUMBER OF BITS
vs
FREQUENCY
10.0
9.5
9.0
8.5
8.0
7.5
7
AV
DV
= 5 V,
= 3 V
= 3.5 MHz
= 25°C
DD
DD
F
T
A
in
5
10
15
20
25
30
f
– Sampling Speed – MSPS
s
Figure 6
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
vs
FREQUENCY
10.00
9.50
9.00
8.50
8.00
7.50
7.00
AV
DD
= DV = 5 V,
DD
F
= 3.5 MHz
in
T
= 25°C
A
5
10
15
20
25
30
f
– Sampling Speed – MSPS
s
Figure 7
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
1.0
AV
DD
s
= 3 V, DV
= 30 MSPS
= 3 V
DD
0.8
0.6
F
0.4
0.2
–0.0
–0.2
–0.4
–0.6
–0.8
–1
0
128
256
384
512
640
768
896
1024
Input Code
Figure 8
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
TYPICAL CHARACTERISTICS
INTEGRAL NONLINEARITY
vs
INPUT CODE
2.0
1.5
AV
DV
= 3 V
= 3 V
= 30 MSPS
DD
DD
F
s
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0
128
256
384
512
640
768
896
1024
Input Code
Figure 9
FFT
vs
FREQUENCY
0
–20
AV
DD
= 3 V
= 3 V
DV
DD
F
= 3.5 MHz
in
–40
–60
–80
–100
–120
–140
0
1.5
3
4.5
6
7.5
9
10.5
12
13.5
15
f –Frequency – MHz
Figure 10
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
Table 1. Mode Selection
INPUT
SPAN
MODE
PIN
REFSENSE
PIN
VREF
PIN
REFTS
PIN
REFBS
PIN
MODES
ANALOG INPUT
FIGURE
AIN
AIN
AIN
AIN
AIN
AIN
AIN
AIN
1 V
2 V
AV
AV
AV
Short together
AGND
AGND
AGND
AGND
8, 15
9, 16
DD
DD
DD
AGND
Short together
Short together to R
a
Top/bottom
1+R /R
Mid R & R
10, 15, 16
10, 15, 16
8, 14
a
b
a
b
External V
1 V
AV /2
DD
AV
DD
External
NC
REF
AV /2
DD
Short together
AGND NC
Mid R & R
2 V
AV /2
DD
9, 14
Short together to the
common mode voltage
Center span
1+R /R
AV /2
DD
R
a
10, 14
11, 14
a
b
a
b
V
REF
AV /2
DD
AV
DD
External
External
reference
Voltage within supply
(REFTS–REBS) = 2 V max
AIN
2 V max
AGND
See Note 1
AGND
See Note 1
12, 13
AIN is input 1
REFTS & REFBS
are shorted
1 V
2 V
AV /2
DD
Short together
Differential
Short together AV /2
DD
17
AV /2
DD
NC
V
REF
AV /2
DD
AV
External
together for input 2
DD
NOTE 1: In external reference mode, V
can be available for external use with CENTER SPAN setup.
REF
reference operations
V
-pin reference
REF
The voltage reference sources on the V
pin are controlled by the REFSENSE pin as shown in Table 2.
REF
Table 2. V
Reference Selection
REF
REFSENSE
AGND
AV
V
REF
2 V
The internal reference is disabled and an external reference should be connected to V
pin if mode = AV /2
REF DD
DD
Short to V
1 V
REF
Connect to R /R
1+R /R
a b
a
b
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
reference operations (continued)
1-V reference: The internal reference may be set to 1 V by connecting REFSENSE to V
.
REF
THS1031
ADC/DAC
REF
+
_
V
REF
= 1 V
+
–
VBG
REFSENSE
AGND
Figure 11. V
1-V Reference Mode
REF
2-V reference: The internal reference may be set to 2 V by connecting REFSENSE to AGND.
THS1031
ADC/DAC
REF
+
_
V
REF
= 2 V
+
–
VBG
REFSENSE
AGND
Figure 12. V
2-V Reference Mode
REF
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
reference operations (continued)
External divider: The internal reference can be set to a voltage between 1 V and 2 V by adding external
resistors.
THS1031
ADC/DAC
REF
+
_
V
REF
= 1 + (Ra/Rb)
+
–
VBG
Ra
REFSENSE
Rb
AGND
Figure 13. V
External Divider Reference Mode
REF
External reference: The internal reference may be overridden by using an external reference. This
condition is met by connecting REFSENSE to AV
and an external reference circuit to the V
pin.
DD
REF
THS1031
ADC/DAC
REF
+
_
V
REF
= External
+
–
VBG
REFSENSE
AV
DD
AGND
Figure 14. V
External Reference Mode
REF
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
reference operations (continued)
ADC reference
The MODE pin is used to select the reference source for the ADC.
Internal ADC Reference: Connect the MODE pin to AV
to use the reference source for ADC generated
DD
on the V
pin. (See V
REFERENCE described in Table 2) such that (REFTF–REFBF) = V
and
REF
REF
REF
(REFTF+REFBF)/2 is set to a voltage for optimum operation of the ADC (near AV /2).
DD
External ADC Reference: To supply an external reference source to the ADC, connect the MODE pin to
AGND. An external reference source should be connected to REFTF/REFTS and REFBF/REFBS.
MODE =AGNDclosesinternalswitchestoallowaKelvinconnectionthroughREFTS/REFBS, anddisables
the on-chip amplifiers which drive on to the ADC references. Differential input is not supported
analog input mode
single-ended input
The single-ended input can be configured to work with either an external ADC reference or internal ADC
reference.
External ADC Reference Mode: A single-ended analog input is accepted at the AIN pin where the input
signal is bounded by the voltages on the REFTS and REFBS pins. Figure 15 shows an example of applying
external reference to REFTS and REFBS pins in which REFTS is connected to the low-impedance 2-V
source and REFBS is connected to the low-impedance 2-V source. REFTS and REFBS may be driven to
any voltage within the supply as long as the difference (REFTS – REFBS) is between 1 V and 2 V as
specified in Table 2. Figure 16 shows an example of external-reference using a Kelvin connection to
eliminate line voltage drop errors.
2 V
1 V
THS1031
AIN
SHA
PGA
A/D
REFTS
2 V
1 V
REFBS
MODE
SW3
REFTF
0.1 µF
0.1 µF
0.1 µF
10 µF
REFBF
Figure 15. External ADC Reference Mode
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
analog input mode(continued)
REFTF
REFBF
THS1031
SHA
AIN
PGA
A/D
REFTS
REFBS
MODE
0.1
µF
SW3
REFTF
REFT
0.1 µF
0.1 µF
10 µF
0.1 µF
REFBF
REFB
0.1 µF
Figure 16. Kelvin Connection With External ADC Reference Mode
InternalADCReferenceModeWithExternalInputCommonMode:Theinputcommonmodeissupplied
to pins REFTS and REFBS while connected together. The input signal should be centered around this
common mode with peak-to-peak input equal to the voltage on the V
pin. Input can be either dc-coupled
REF
or ac-coupled to the same common mode voltage (Figure 17) or any other voltage within the input voltage
range.
2 V
1 V
THS1031
AIN
SHA
PGA
A/D
REFTS
1.5 V
REFBS
MODE
AV
DD
REFTF
ADC
REF
0.1 µF
10 µF
0.1 µF
V
REF
+
_
– +
1 V
REFBF
0.1 µF
REFSENSE
Figure 17. External Input Common Mode
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
analog input mode(continued)
Internal ADC Reference Mode With Common Mode Input V
/2: The input common mode is set to
REF
V
/2byconnectingREFTStoV
andREFBStoAV .TheinputsignalatAINwillswingbetweenV
REF
REF
SS REF
and AV
.
SS
2 V
THS1031
AIN
1 V
SHA
PGA
A/D
REFTS
1.5 V
REFBS
MODE
AV
DD
REFTF
ADC
REF
0.1 µF
10 µF
V
REF
0.1 µF
+
– +
1 V
_
REFBF
0.1 µF
REFSENSE
Figure 18. Common Mode Input V
/2 With 1-V Internal Reference
REF
2 V
0 V
THS1031
SHA
AIN
PGA
A/D
REFTS
REFBS
MODE
AV
DD
REFTF
ADC
REF
0.1 µF
0.1 µF
10 µF
+
_
– +
1 V
V
REF
REFBF
0.1 µF
REFSENSE
Figure 19. Common Mode Input V
/2 With 2-V Internal Reference
REF
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
analog input mode(continued)
differential input
In this mode, the first differential input is applied to the AIN pin and the second differential input is applied to the
common point where REFTS and REFBS are tied together. The common mode of the input should be set to
AV /2 as shown in Figure 20. The maximum magnitude of the differential input signal should be equal to V
.
DD
REF
V
REF
THS1031
SHA
AIN
AV /2
DD
PGA
A/D
REFTS
REFBS
MODE
AV
DD
REFTF
V
REF
is either internal or external
ADC
REF
V
REF
0.1 µF
10 µF
0.1 µF
REFBF
0.1 µF
Figure 20. Differential Input
digital input mode
The THS1031 contains 4 registers: two CLAMP registers, a CONTROL register, and a TEST register. The TEST
register is reserved for test purposes. Binary data can be written into the CLAMP and CONTROL registers via
I/O0–I/O9 by inserting an active-low write strobe to the WR input pin and an active-low signal to the OE input
pin. This will disable the ADC’s output bus. The two MSBs of each register are address bits. For example, set
bit 9 and bit 8 to 00 to select the clamp register 1. Set bit 9 and bit 8 to 01 to select the clamp register 2.
clamp registers
The internal digital clamp circuit uses a 10-bit DAC to convert the 10-bit digital value into the analog clamp level
in which the clamp register 1 contains 8 LSBs of DAC(7:0). The clamp register 2 contains two MSBs of the
DAC(9:8). DAC(9:8) (Default = 00): For clamping purpose, the entire range of voltage reference V
is divided
REF
into 4 quarters which can be selected by bit 0 (DAC8) and bit 1 (DAC9) in the clamp register 2. The user can
clamp to any of 256-dc levels within each quarter determined by the 8-bit content of the clamp register 1.
Figure 21 shows how the DACs 10-bit digital input map to the analog clamping range from 0 V to V
.
REF
Clamp Register 1
9
0
8
0
7
6
5
4
3
2
1
0
DAC7
DAC6
DAC5
DAC4
DAC3
DAC2
DAC1
DAC0
Clamp Register 2
9
0
8
1
7
6
5
4
3
2
1
0
X
X
X
X
X
X
DAC9
DAC8
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
digital input mode (continued)
REFTF
DAC (9:0)
1111111111
•
•
•
1100000000
1011111111
3/4 (REFTF – REFBF)
1/2 (REFTF – REFBF)
1/4 (REFTF – REFBF)
•
•
•
1000000000
0111111111
•
•
•
0100000000
0011111111
•
•
•
0000000000
REFBF
Figure 21. Digital Clamp Input Range
control register
9
1
8
0
7
6
5
4
3
2
1
0
X
Clamp Disable
Bin/2’s Output
INT/EXT Clamp
Power Down
PGA2
PGA1
PGA0
Clamp Disable: (Default = 0) Set bit 6 to 1 to disable the internal clamp amplifier for power savings.
BIN/2s Output: (Default is straight binary) Set bit 5 to 0 to set the output data format to straight binary or
set bit 5 to1 to set the output data format to 2s complement.
INT/EXT Clamp: (Default = 0) Set bit 4 of the CONTROL register to 0 to select the external analog clamp
or set bit 4 to 1 to select the internal digital clamp whose clamp level is defined in the clamp register
described above.
Power Down: (Default = 0) Set bit 3 of the CONTROL register to 1 to power down the THS1031.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
digital input mode (continued)
PGA(2–0):(Default=001)3-bitgainforprogrammablegainamplifiercanbesetasindicatedinthefollowing
table:
PGA[2–0]
000
GAIN
0.5
001
Unity gain
1.5
010
011
2.0
100
2.5
101
3.0
110
3.5
111
4.0
test register (reserved)
9
1
8
1
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
digital output mode
3-State Output: The digital outputs can be set to high-impedance state by applying a Hi logic to the OE
pin.
Output Format: Defined by bit 5 of the CONTROL register. The output format is straight binary if bit 5 set
to 0. The output format is 2s complement if bit 5 is set to 1. The default format is straight binary.
clamp operation
The THS1031 ADC features an internal clamp circuit for dc restoration of video or ac coupled signals. The clamp
input level can come from either an external source or an internal digital clamp circuit containing a 10-bit DAC
and clamp register.
External Clamp Input: To enable the external clamp input source, use the default state on power up or
write a 0 to bit 4 of the PGA/CONTROL register. This will connect the switch SW2 to the CLAMPIN pin. The
clamp amplifier will then servo the voltage at the AIN pin to be equal to the clamp voltage applied at the
CLAMPIN pin. After the desired clamp level is attained, the switch SW1 is opened by taking CLAMP back
to logic low. Ignoring the droop caused by the input bias current, the input capacitor CIN will hold the DC
voltage at AIN constant until the next clamp interval. The input resistor RIN has a minimum recommended
value of 10 W, to maintain the closed-loop stability of the clamp amplifier.
Internal Programmable Digital Clamp Input: The THS1031 ADC features a programmable digital clamp
circuit to set more precise clamping level to 1-LSB accuracy for dc restoration of video or ac coupledsignals.
Figure 22 shows the internal clamp circuitry and the external control signals needed for the digital clamp
operation. To enable the digital clamp input source, write a 1 to bit 4 of the CONTROL register which will
connect the switch SW2 to the output of the 10-bit clamp DAC. In the CLAMP register, bit 0 to bit 7 are used
to set the clamp level input to the 10-bit DAC and bit 6–7 are used to select one of 4 equal clamping voltage
sub-ranges as described in the description of CLAMP REGISTER for digital input mode. The clamp
amplifier will then servo the voltage at the AIN pin to be equal to the clamp voltage applied at the CLAMPIN
pin. After the desired clamp level is attained, the switch SW1 is opened by taking CLAMP back to logic low.
Ignoring the droop caused by the input bias current, the input capacitor CIN will hold the dc voltage at AIN
constant until the next clamp interval. The input resistor RIN has a minimum recommended value of 10 W,
to maintain the closed-loop stability of the clamp amplifier.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
clamp operation (continued)
Clamp and Droop Analysis
16–Bit DAC
CLAMPIN
CLAMP
SW2
Control
Register
+
–
SW1
C1
R1
AIN
S/H
Figure 22. Clamp Operation
Clamp Acquisition Time: Figure 22 shows the basic operation of the clamp circuit in which the ac input
signal is passed through an RC coupler.
The acquisition time when the switch is closed will equal a: T(acq) = C .R ln(Vc/Ve)(Eq.1)
i
i
In case of composite video, typical input Ri = 20 Ω. In a video clamping application, the droop is a critical
parameter and thus the input capacitor should be sized to allow sufficient acquisition time of clamp voltage at
AIN within the CLAMP interval, but also to minimize droop between clamping intervals. Typically, C = 1µF
i
By applying equation 1 above, the following examples apply to an NTSC composite video signal:
The acquisition time needed to clamp 1-V input level to black level (0.340 Vdc ) is about 130 µs.
The acquisition time needed to clamp 2-V input level to the white level (1 Vdc) is about 140 µs.
The acquisition time needed to clamp 3-V input level to the sync level (0.288 Vdc) is about 160 µs.
droop
The voltage droop is the voltage change across the input capacitor C by the bias current as follows:
i
dV
Ibias Ci (t)
where t = elapsed time between clamping intervals
The bias current depends on the sampling rate. For a sampling rate of 30 MSPS and a typical input capacitance
of 1 pF, the input resistance is
Rs = 1/(Cs.Fs) = 1/(1 pFx30 MHz) = 33 kΩ
For 1-V input range and clamping period = 64 µs, the max bias current will equal I
dV = (15 µA/1 µF)(64 µs) = 0.96 mV
= 0.5 V/33 kΩ = 15 µA:
= 0.5 V/33 kΩ = 15 µA:
= 1.0 V/33 kΩ = 30 µA
bias
bias
For 1-V input range and clamping period = 64 µs, the max bias current will equal I
dV = (15 µA/1 µF)(64 µs) = 0.96 mV
For 2-V input range and clamping period = 64 µs, the max bias current will equal I
bias
dV = (30 µA/1 µF)(64 µs) = 1.9 mV
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
clamp operation (continued)
requirements
For a single direct source of NTSC video,
The initial clamp acquisition time needs to be between 130 µs and 160 µs to set the input dc level within
1 mV accuracy.
The clamp pulse at CLAMP is recommended to be 2 µs (typ).
The droop voltage needs to be compensated within one clamping period of 64 µs for 1 V and 2 V. Input
ranges are 1 mV and 1.9 mV respectively which are less than 1 LSB.
power management
Upon power up, the THS1031 is put in the default mode. In the default mode, the PGA (PGA bypass) and the
clamp DAC are powered down which adds to the device’s flexibility. The users need not incur the penalty of
having to provide power for a certain section if it is not necessary to their design.
Whenbit3ofPGA/controlregisterissetto1, theentiredeviceispowereddown. TheADCwillwake-upin400 ns
(typ) after the bit 3 is reset.
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.293 (7,45)
Gage Plane
0.010 (0,25)
1
8
0°–8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
28
DIM
0.410
0.510
0.610
0.710
A MAX
A MIN
(10,41) (12,95) (15,49) (18,03)
0.400
0.500
0.600
0.700
(10,16) (12,70) (15,24) (17,78)
4040000/C 07/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 2000, Texas Instruments Incorporated
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