THS4302RGTTG4 [TI]
2.4GHz 宽带固定增益放大器 | RGT | 16 | -40 to 85;
| 型号： | THS4302RGTTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.4GHz 宽带固定增益放大器 | RGT | 16 | -40 to 85 放大器 运算放大器 放大器电路 |
| 文件： | 总23页 (文件大小：586K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
WIDEBAND FIXED-GAIN AMPLIFIER
FEATURES
APPLICATIONS
•
•
•
•
•
•
•
Wideband Signal Processing
Wireless Transceivers
IF Amplifier
ADC Preamplifier
DAC Output Buffers
Test, Measurement, and Instrumentation
Medical and Industrial Imaging
•
Fixed-Gain Closed-Loop Amplifier
•
Multiple Gain Options
– THS4302: 5 V/V (14 dB)
Wide Bandwidth: 2.4 GHz
High Slew Rate: 5500 V/µs
Low Total Input Referred Noise: 2.8 nV/√Hz
Low Distortion
•
•
•
•
– HD3: -86 dBc at 30 MHz
– HD3: -81 dBc at 70 MHz
– IMD3: -88 dBc at 100 MHz
– OIP3: 39 dBm at 100 MHz
– IMD3: -73 dBc at 300 MHz
– OIP3: 32 dBm at 300 MHz
High Output Drive: ±180 mA
Power Supply Voltage: 3 V or 5 V
DESCRIPTION
The THS4302 device is a wideband, fixed-gain ampli-
fier that offers high bandwidth, high slew rate, low
noise, and low distortion. This combination of specifi-
cations enables analog designers to transcend cur-
rent performance limitations and process analog sig-
nals at much higher speeds than previously possible
with closed-loop, complementary amplifier designs.
This device is offered in a 16-pin leadless package
and incorporates a power-down mode for quiescent
power savings.
•
•
APPLICATION CIRCUIT
V
S+
SMALL SIGNAL FREQUENCY RESPONSE
16
+
FB
14
12
10
22 µF
47 pF
0.1 µF
30.1 Ω
R
f
8
6
R
g
_
+
50 Ω Source
V
O
V
R
V
= 200 mV
= 100 Ω
= 5 V
O
V
I
4
2
0
THS4302
L
100 Ω
S
49.9 Ω
V
S-
10 M
100 M
1 G
10 G
f - Frequency - Hz
FB
+
22 µF
47 pF
0.1 µF
30.1 Ω
FB = Ferrite Bead
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2005, Texas Instruments Incorporated
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATING
over operating free-air temperature range unless otherwise noted
(1)
UNIT
Supply voltage, VS
6 V
Input voltage, VI
±VS
200 mA
Output current, IO
Continuous power dissipation
See Dissipation Rating Table
150°C
Maximum junction temperature, TJ
Maximum junction temperature, continuous operation, long term reliability, TJ
Storage temperature range, Tstg
(2)
125°C
-65°C to 150°C
300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) The absolute maximum temperature under any condition is limited by the constraints of the silicon process. Stresses above these
ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not
implied.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
RECOMMENDED OPERATING CONDITIONS
MIN
±1.5
3
MAX
±2.5
5
UNIT
V
Dual supply
Supply voltage, VCC (VS+ and VS-
)
Single supply
Common-mode input voltage range
VS- +1
VS+ -1
V
PACKAGE DISSIPATION RATINGS
POWER RATING(2)
A ≤ 25°C TA = 25°C
3.16 1.65 W
PACKAGE
ΘJC(°C/W)
ΘJA(°C/W)(1)
T
RGT (16)(3)
2.4
39.5
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long
term reliability.
(3) The THS4302 device may incorporate a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which can permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally enhanced package.
AVAILABLE OPTIONS
INTERNAL FIXED GAIN
RESISTOR VALUES (+5)
TRANSPORTATION MEDIA,
QUANTITY
PACKAGED DEVICES
PACKAGE TYPE(1)
RG
RF
THS4302RGTT
THS4302RGTR
Tape and Reel, 250
Tape and Reel, 3000
Leadless (RGT-16)
50 Ω
200 Ω
(1) The PowerPAD is electrically isolated from all other pins.
2
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
PIN ASSIGNMENTS
RGT PACKAGE
TOP VIEW
16 15 14 13
1
2
3
4
12
11
10
9
V
S−
V +
S
6
7
8
5
V
OUT
NC = No connect
ELECTRICAL CHARACTERISTICS
THS4302 (Gain = +5 V/V) Specifications: VS = 5 V, RL = 100 Ω, (unless otherwise noted)
TYP
OVERTEMPERATURE
MIN/
UNITS TYP/
MAX
PARAMETER
TEST CONDITIONS
0°C to
70°C
-40°C
to 85°C
25°C
25°C
AC PERFORMANCE
Small signal bandwidth
Gain bandwidth product
Full-power bandwidth
Slew rate
G = +5, VO = 200 mVRMS
2.4
12
GHz
GHz
MHz
V/µs
Typ
Typ
Typ
Min
G = +5, VO = 2 Vpp
875
5500
G = +5, VO = 2 V Step
Harmonic distortion
RL = 100 Ω
-66
-75
-81
-85
-88
dBc
dBc
dBc
dBc
dBc
Second harmonic distortion
Third harmonic distortion
Typ
Typ
G = +5, VO = 1 VPP,
f = 70 MHz
RL = 1 kΩ
RL = 100 Ω
RL = 1 kΩ
VO = 1 VPP envel-
ope, 200 kHz tone
spacing
fc = 100 MHz
Third order intermoduation (IMD3)
Third order output intercept (OIP3)
Typ
Typ
fc = 300 MHz
-73
dBc
fc = 100 MHz
fc = 300 MHz
39
32
2.8
16
dBm
dBm
VO = 1 VPP, 200 kHz
tone spacing
Total input referred noise
Noise figure
f = 1 MHz
nV/√Hz
dB
Typ
Typ
DC PERFORMANCE
5
5
2
4.95
5.05
4.25
4.95
5.05
5.25
±20
13
4.95
5.05
5.25
±20
15
V/V
V/V
Min
Max
Max
Typ
Max
Typ
Voltage gain
VI = ±50 mV, VCM = 2.5 V
Input offset voltage
VCM = 2.5 V
VCM = 2.5 V
VCM = 2.5 V
VCM = 2.5 V
mV
Average offset voltage drift
Input bias current
µV/°C
µA
7
10
Average bias current drift
±55
±55
nA/°C
3
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
ELECTRICAL CHARACTERISTICS (continued)
THS4302 (Gain = +5 V/V) Specifications: VS = 5 V, RL = 100 Ω, (unless otherwise noted)
TYP
OVERTEMPERATURE
MIN/
UNITS TYP/
MAX
PARAMETER
TEST CONDITIONS
0°C to
70°C
-40°C
to 85°C
25°C
25°C
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
Input resistance
0.5/4.5
60
1/4
52
1.1/3.9 1.2/3.8
50 50
V
Min
Min
Typ
Max
VCM = 2 V to 3 V
dB
MΩ
pF
Noninverting input
Noninverting input
1.6
1
Input capacitance
OUTPUT CHARACTERISTICS
Output voltage swing
1/4
180
180
0.2
1.1/3.9 1.2/3.8 1.2/3.8
V
Min
Min
Min
Typ
Output current (sourcing)
Output current (sinking)
Output impedance
RL = 5 Ω
RL = 5 Ω
f = 10 MHz
170
170
165
165
160
160
mA
mA
Ω
POWER SUPPLY
Operating voltage
5
5.5
42
32
54
65
5.5
46
29
52
64
5.5
48
26
51
62
V
Max
Max
Min
Min
Min
Maximum quiescent current
Minimum quiescent current
37
37
60
75
mA
mA
dB
dB
Power supply rejection ratio (PSRR +) VS+ = 5 V to 4.5 V, VS- = 0 V
Power supply rejection ratio (PSRR -)
POWER-DOWN CHARACTERISTICS
Maximum power-down current
Power-on voltage threshold
Power-down voltage threshold
Turnon time delay, td(on)
VS+ = 5 V, VS- = 0 V to 0.5 V
PD = 0 V
0.8
1.1
1.1
6
1.0
1.5
0.9
1.1
1.2
mA
V
Max
Min
Max
Typ
Typ
Typ
Typ
V
50% of final value
50% of final value
µs
µs
kΩ
Ω
Turnoff time delay, td(off)
5
Input impedance
100
250
Output impedance
f = 100 kHz
4
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
TYPICAL CHARACTERISTICS
Table of Graphs (5 V)
FIGURE
1
S-Parameter vs Frequency
Small signal frequency response
2
Large signal frequency response
3
Slew rate vs Output voltage
4
Harmonic distortion vs Frequency
5, 6, 7, 8
9
Harmonic distortion vs Output voltage swing
Second-order intermodulation distortion vs Frequency
Second-order intercept point vs Frequency
Third order intermodulation distortion vs Frequency
Third-order intercept point vs Frequency
Voltage and current noise vs Frequency
Settling time
10
11
12
13
14
15, 16
17
Quiescent current vs Supply voltage
Output voltage vs Load resistance
Capacitive load frequency response
Gain vs Case temperature
18
19
20
Rejection ratios vs Frequency
21
Rejection ratios vs Case temperature
Common-mode rejection ratio vs Input common-mode range
Input offset voltage vs Case temperature
Positive input bias current vs Case temperature
Small signal transient response
22
23
24
25
26
Large signal transient response
27
Overdrive recovery
28
Closed-loop output impedance vs Frequency
Power-down quiescent current vs Supply voltage
Power-down output impedance vs Frequency
Turnon and turnoff delay times
29
30
31
32
Power-down S-Parameter vs Frequency
33
Table of Graphs (3 V)
FIGURE
34
Small signal frequency response
Large signal frequency response
Slew rate vs Output voltage
35
36
Output voltage vs Load resistance
Capacitive load frequency response
Gain vs Case temperature
37
38
39
S - Parameter vs Frequency
40
Input offset voltage vs Case temperature
Positive input bias current vs Case temperature
Overdrive recovery
41
42
43
5
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
Typical Test Data
S-Parameter (Measured using standard THS4302EVM, edge number 6443548, with VS = 5 V in a 50-Ω test system)
Frequency MHz
1
S11 (dB)
-55.86328
-55.75781
-53.0293
S11 (Ang)
-3.728516
-4.832764
-29.01563
-82.44141
-97.42188
-105.9063
-111.1133
-114.2891
-114.4297
-113.9727
-113.5313
-116
S21 (dB)
14.10889
14.11621
14.11035
14.16309
14.34766
14.38428
14.42041
14.39209
14.40918
14.38477
14.38184
14.35645
14.36035
14.3208
S21 (Ang)
-0.093384
-0.109863
-0.350189
-1.682312
-4.422119
-7.657471
-10.49512
-13.63135
-17.17871
-19.34375
-23.08594
-25.62305
-28.69922
-32.48047
-34.17773
-39.5918
S12 (dB)
-96.26953
-98.18359
-78.10156
-61.82813
-56.37891
-54.44336
-53.72852
-53.55273
-53.94727
-54.23828
-55.13281
-56.33594
-58.48828
-63.26367
-67.62109
-68.02734
-55.4082
S12 (Ang)
20.78809
-120.6758
121.2148
75
S22 (dB)
-70.32422
-65.65234
-52.01953
-45.27539
-31.04981
-26.75098
-25.3418
S22 (Ang)
122.5
2
97.16016
73.91406
142.0391
115.4414
98.26172
85.07031
77.09766
72.94531
70.63281
72.0625
10
50
-42.92383
-37.35156
-35.64258
-33.27344
-32.18945
-30.92578
-30.29492
-29.11816
-28.44141
-27.50977
-26.51856
-26.01856
-24.03613
-21.97559
-20.40137
-18.70313
-15.14893
-12.66602
-11.48975
-11.68311
100
61.26367
53.0957
34.22656
31.70508
21.56934
19.45508
16.29395
14.38232
12.0708
3.492187
27.33594
172.2422
171.0703
168.8125
163.1016
152.5313
139.7109
112.5
150
200
250
-24.14844
-23.53613
-22.99512
-22.13379
-21.45215
-20.56641
-19.71094
-19.2959
300
350
400
450
71.90234
74.21094
74.85938
75.58984
77.79297
77.22266
76.04297
73.89063
65.77734
55.74414
40.24414
31.3877
500
-114.082
-112.25
550
600
-113.6719
-115.8984
-117.4922
-120.7305
-123.4023
-134.7031
-149.0625
-168.9922
-169.8203
14.30713
14.23242
14.1665
700
-17.80078
-15.81494
-14.38965
-12.91406
-9.994141
-7.968018
-6.750977
-7.211182
800
-47.05664
-51.92969
-57.80078
-75.02344
-88.4375
900
14.11133
14.06006
13.93872
13.74683
12.97827
12.18066
-50.38477
-46.64453
-40.19141
-35.73438
-31.94531
-34.46094
1000
1250
1500
1750
2000
-110.2852
-123.043
84.83984
6
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
TYPICAL THS4302 CHARACTERISTICS (5 V)
S-PARAMETER
vs
FREQUENCY
SMALL SIGNAL FREQUENCY
RESPONSE
LARGE SIGNAL FREQUENCY
RESPONSE
16
14
12
10
16
14
12
10
8
10
0
V
= 5 V
S
50 Ω
50 Ω
−
+
−10
S22
50 Ω
50 Ω
−20 Source
−30
−40
8
6
4
2
0
S11
−50
−60
6
S12
R
= 100 Ω
= 200 mV
= 5 V
L
−70
R
= 100 Ω
= 2 V
= 5 V
L
4
V
V
O
S
V
V
O
S
−80
2
−90
−100
0
1 M
10 M
100 M
1 G
10 G
10 M
100 M
1 G
10 G
100 k
1 M
10 M
100 M
1 G
10 G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 1.
Figure 2.
Figure 3.
SLEW RATE
vs
OUTPUT VOLTAGE
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
−50
−60
−50
−60
−70
−80
−90
7000
6000
5000
4000
3000
2000
1000
0
R = 1 kΩ
L
R
V
V
= 100 Ω
= 1 V
PP
= 5 V
R
V
= 100 Ω
= 5 V
L
L
V
V
= 1 V
= 5 V
O
S
PP
O
S
S
−70
Fall
HD2
HD3
−80
Rise
HD2
−90
HD3
−100
−110
−100
−110
10
100
1
0
0.5
1
1.5
2
2.5
1
10
100
f − Frequency − MHz
f − Frequency − MHz
V
− Output Voltage − V
O
PP
Figure 4.
Figure 5.
Figure 6.
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
vs
vs
FREQUENCY
FREQUENCY
−50
−55
−60
−65
−70
−75
−80
−85
−90
−50
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
−50
−60
−70
−80
R
V
= 100 Ω
R
V
= 100 Ω
= 5 V
L
L
R
V
V
= 1 kΩ
L
= 2 V
= 5 V
O
PP
S
= 2 V
HD2, f = 64 MHz
O
S
PP
V
S
= 5 V
HD3, f = 64 MHz
HD2, f = 4 MHz
HD3
HD2
HD2
−90
HD3
HD3, f = 4 MHz
1.5
−100
10
100
1
0
0.5
1
2
2.5
1
10
100
f − Frequency − MHz
f − Frequency − MHz
V
− Output Voltage Swing − V
O
PP
Figure 7.
Figure 8.
Figure 9.
7
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
TYPICAL THS4302 CHARACTERISTICS (5 V) (continued)
SECOND-ORDER
INTERMODULATION DISTORTION
vs
SECOND-ORDER
OUTPUT INTERCEPT POINT
vs
THIRD-ORDER
INTERMODULATION DISTORTION
vs
FREQUENCY
FREQUENCY
FREQUENCY
−50
100
95
90
85
80
75
70
65
−50
−55
−60
−65
−70
−75
−80
−85
Test data
+2.5V
measurement
point
R
= 100 Ω
= 5 V
L
50 Source
49.9
−55
−60
−65
−70
−75
−80
−85
50 Test
V
S
Equipment
F2 − F1
49.9
200 kHz Tone Spacing
49.9
−2.5V
V
= 2 V
PP
O
Envelope
Tone Spacing = 200 kHz
To 50-Ω Load, Add 3dB to
Refer To Amplifier Output
V
= 1 V
O
PP
F2 + F1
Envelope
V
= 5 V
S
R
= 100 Ω
= 1 V Envelope
PP
L
−90
−95
60
55
50
−90
−95
V
O
F2 − F1
V
= 0.5 V
PP
O
Tone Spacing = 200 kHz
F2 + F1
Envelope
−100
−100
0
50 100 150
200
250
300
0
50
100
150
200
250
300
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 10.
Figure 11.
Figure 12.
THIRD-ORDER
OUTPUT INTERCEPT POINT
VOLTAGE AND CURRENT NOISE
vs
vs
FREQUENCY
FREQUENCY
SETTLING TIME
3.25
3
43
41
39
37
35
33
31
29
100
100
Test data
+2.5V
−2.5V
measurement
point
Rising Edge
50 Source
49.9
50 Test
Equipment
49.9
49.9
R
L
= 100 Ω
2.75
f= 1 MHz
= 5 V
V
S
10
10
2.5
R
V
= 100 Ω
= 5 V
V
= 1 V
PP
L
O
I
Envelope
n
S
2.25
Falling Edge
V
n
Tone Spacing = 200 kHz
To 50-Ω Load, Add 3dB to
Refer To Amplifier Output
2
27
25
1
1
1.75
100
1 k
10 k
100 k
1 M
10 M
0
100
200
300
400
500
0.2
0
0.2
0.4
0.6
0.8
1
1.2
f − Frequency − Hz
t − Time − ns
f − Frequency − MHz
Figure 13.
Figure 14.
Figure 15.
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
SETTLING TIME
4
50
45
40
35
30
25
20
15
10
5
5
Rising Edge
3.75
4.5
T
= 85°C
A
3.5
4
T
A
= 25°C
= −40°C
3.25
3.5
3
2.75
2.5
R
L
= 100 Ω
T
A
3
f= 1 MHz
= 5 V
V
= 5 V
S
V
S
2.5
T
A
= −40 to 85°C
2.25
2
2
1.5
1.75
1.5
1.25
1
Falling Edge
1
0.5
0
0
0.2
0
0.2 0.4 0.6 0.8
t − Time − ns
1
1.2 1.4 1.6
1
10
100
1000
2.5
3
3.5
4
4.5
5
R
L
− Load Resistance − Ω
V
− Supply Voltage − V
S
Figure 16.
Figure 17.
Figure 18.
8
THS4302
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SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
TYPICAL THS4302 CHARACTERISTICS (5 V) (continued)
GAIN
REJECTION RATIOS
vs
CAPACITIVE LOAD
FREQUENCY RESPONSE
vs
CASE TEMPERATURE
FREQUENCY
14.02
14
70
1
R
C
= 24.9 Ω,
(ISO)
= 10 pF
0.5
PSRR+
60
50
40
30
L
0
−0.5
−1
V
= 5 V
S
CMRR
13.98
13.96
R
C
= 8 Ω,
= 100 pF
(ISO)
L
−1.5
−2
20
10
0
R
= 12.1 Ω,
= 47 pF
(ISO)
C
L
13.94
13.92
−2.5
−3
V
= 5 V
V
= 5 V
1 M
S
S
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
10 M
100 M
1 G
100 k
10 M
100 M
1 G
f − Frequency − Hz
Case Temperature − °C
f − Frequency − Hz
Figure 19.
Figure 20.
Figure 21.
REJECTION RATIOS
vs
CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
80
75
70
65
6
70
PSRR−
V
= 5 V
S
60
50
40
5
4
3
2
CMMR
60
55
30
20
PSRR+
50
10
V
2
= 5 V
S
1
0
45
40
V
= 5 V
S
0
−10
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
1
3
4
5
−40−30−20−10
0
10 20 30 40 50 60 70 80 90
V
− Input Common-Mode Voltage Range − V
Case Temperature − °C
ICR
Case Temperature − °C
Figure 22.
Figure 23.
Figure 24.
POSITIVE INPUT BIAS CURRENT
vs
SMALL SIGNAL TRANSIENT
RESPONSE
LARGE SIGNAL TRANSIENT
RESPONSE
CASE TEMPERATURE
12
10
2.65
4
3.5
3
V
= 5 V
S
2.6
2.55
2.5
8
6
4
2
0
2.5
R
= 100 Ω
L
Input t /t = 60 ps
r
f
2
V
= 5 V
2.45
2.4
S
R
L
= 100 Ω
Input t /t = 60 ps
r
f
1.5
V
= 5 V
S
1
2.35
0
2
4
6
8
10 12 14 16 18 20
10 12 14 16 18 20
0
2
4
6
8
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
t − Time − ns
Case Temperature − °C
Figure 25.
Figure 26.
Figure 27.
9
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
TYPICAL THS4302 CHARACTERISTICS (5 V) (continued)
POWER-DOWN QUIESCENT
CURRENT
OUTPUT IMPEDANCE
vs
vs
OVERDRIVE RECOVERY
FREQUENCY
SUPPLY VOLTAGE
5.5
5
100
10
1200
1100
1000
900
800
700
600
500
400
300
200
3
V
= 5 V
S
T
A
= 85°C
4.5
T
A
= 25°C
2.75
4
3.5
3
T
A
= −40°C
2.5
2.25
2
2.5
2
1.5
1
1
0.5
0
100
0
−0.5
0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
2.5 2.75 3 3.25 3.5 3.75
4 4.25 4.5 4.75 5
10 M
100 M
1 G
10 G
t − Time − µs
f − Frequency − Hz
V
− Supply Voltage − V
S
Figure 28.
Figure 29.
Figure 30.
POWER-DOWN OUTPUT
IMPEDANCE
vs
POWER-DOWN S-PARAMETER
TURNON AND TURNOFF TIMES
DELAY TIME
vs
FREQUENCY
FREQUENCY
80
1000
10
0
3
2
1
V
= 5 V and 3 V
S
S22
70
60
50
40
30
20
10
R
G
R
F
−10
−20
−30
C
−
+
0
50 Ω
50 Ω
50 Ω
Source
50 Ω
−1
−40
−50
−60
−70
−80
S11
S12
100
−2
−3
−4
−5
−6
R
V
= 100 Ω
= 5 V
L
S
V
= 5 V
S
0
−90
−10
10
100 k
−100
−15
0
15
30
45
60
75
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
10 G
t − Time − µs
f − Frequency − Hz
f − Frequency − Hz
Figure 31.
Figure 32.
Figure 33.
10
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
TYPICAL THS4302 CHARACTERISTICS (3 V)
SLEW RATE
vs
OUTPUT VOLTAGE
SMALL SIGNAL
FREQUENCY RESPONSE
LARGE SIGNAL
FREQUENCY RESPONSE
16
14
12
10
4000
3500
3000
2500
2000
1500
1000
500
16
14
12
Fall
10
8
8
6
Rise
6
R
= 100 Ω
= 100 mV
= 3 V
L
R
= 100 Ω
= 0.5 V
= 3 V
L
4
4
2
0
V
V
O
S
V
V
O
S
R
V
= 100 Ω
= 3 V
L
2
0
S
0
100 k
1 M
10 M 100 M
1 G
10 G
100 k
1 M
10 M
100 M 1G
10 G
0
0.25
0.5
0.75
1
1.25
1.5
f − Frequency − Hz
f − Frequency − Hz
V
− Output Voltage − V
O
Figure 34.
Figure 35.
Figure 36.
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
GAIN
vs
CAPACITIVE LOAD
FREQUENCY RESPONSE
CASE TEMPERATURE
14.04
14.02
14
2.25
1
V
T
A
= 3 V
= −40 to 85°C
R
C
= 24.9 Ω,
S
(ISO)
= 10 pF
V
= 3 V
S
0.5
L
2
0
1.75
−0.5
−1
R
C
= 8 Ω,
13.98
13.96
1.5
(ISO)
= 100 pF
L
−1.5
−2
1.25
1
R
(ISO)
= 12.1 Ω,
= 47 pF
C
L
13.94
13.92
−2.5
−3
R
= 100 Ω,
= 5 V
L
V
S
0.75
10 M
100 M
1 G
−40−30−20−10
0
10 20 30 40 50 60 70 80 90
10
100
1000
1
f − Frequency − Hz
Case Temperature − °C
R
L
− Load Resistance − Ω
Figure 37.
Figure 38.
Figure 39.
S-PARAMETER
vs
FREQUENCY
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
POSITIVE INPUT BIAS CURRENT
vs
CASE TEMPERATURE
12
10
10
4
V = 3 V
S
R
R
G
F
0
C
3.5
−10
−
+
S22
50 Ω
50 Ω
3
V
= 3 V
S
−20
50 Ω
Source
50 Ω
V
= 3 V
8
6
4
S
−30
−40
2.5
2
−50
S11
1.5
−60
−70
−80
S12
1
0.5
0
2
0
−90
−100
1 M
10 M
100 M
1 G
10 G
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
f − Frequency − Hz
Case Temperature − °C
Case Temperature − °C
Figure 40.
Figure 41.
Figure 42.
11
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
TYPICAL THS4302 CHARACTERISTICS (3 V) (continued)
OVERDRIVE RECOVERY
3
1.75
1.625
1.5
2.75
2.5
2.25
2
1.75
1.5
1.25
1
1.375
0.75
V
= 3 V
0.5
0.25
0
S
1.25
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t − Time − µs
Figure 43.
12
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
APPLICATION INFORMATION
generator. The 50-Ω series resistor at the VO terminal
in addition to the 50-Ω load impedance of the test
equipment, provides a 100-Ω load. The total 100-Ω
load at the output, combined with the 250-Ω total
feedback network load, presents the THS4302 with
an effective output load of 71 Ω for the circuit of
Figure 44.
High-Speed Operational amplifiers
The THS4302 fixed-gain operational amplifier set new
performance levels, combining low distortion, high
slew rates, low noise, and a gain bandwidth in excess
of 2 GHz. To achieve the full performance of the
amplifier, careful attention must be paid to
printed-circuit board layout and component selection.
INTERNAL FIXED RESISTOR VALUES
In addition, the devices provide a power-down mode
with the ability to save power when the amplifier is
inactive.
DEVICE
GAIN (V/V)
Rf
Rg
THS4302
+5
200
50
V
S+
Applications Section Contents
•
•
•
•
•
•
Wideband, Noninverting Operation
Single Supply Operation
Saving Power With Power-Down Functionality
Driving an ADC With the THS4302
Driving Capacitive Loads
Power Supply Decoupling Techniques and
Recommendations
Board Layout
+
FB
22 µF
47 pF
0.1 µF
30.1 Ω
R
f
R
g
50-Ω Source
_
+
V
O
V
I
THS4302
•
•
100 Ω
49.9 Ω
Printed-Circuit Board Layout Techniques for
Optimal Performance
V
S−
•
•
•
•
•
PowerPAD Design Considerations
PowerPAD PCB Layout Considerations
Thermal Analysis
Design Tools
Evaluation Fixtures and Application Support
Information
FB
+
22 µF
47 pF
0.1 µF
30.1 Ω
FB = Ferrite Bead
Figure 44. Wideband, Noninverting
Gain Configuration
•
•
Additional Reference Material
Mechanical Package Drawings
SINGLE SUPPLY OPERATION
WIDEBAND, NONINVERTING OPERATION
The THS4302 is designed to operate from a single
3-V to 5-V power supply. When operating from a
single power supply, care must be taken to ensure
the input signal and amplifier are biased appropriately
to allow for the maximum output voltage swing. The
circuits shown in Figure 45 demonstrate methods to
configure an amplifier in a manner conducive for
single supply operation.
The THS4302 is a fixed-gain voltage feedback oper-
ational amplifier, with power-down capability,
designed to operate from a single 3-V to 5-V power
supply.
Figure 44 is the noninverting gain configuration used
to demonstrate the typical performance curves. Most
of the curves were characterized using signal sources
with 50-Ω source impedance, and with measurement
equipment presenting a 50-Ω load impedance. In
Figure 44, the 49.9-Ω shunt resistor at the VIN
terminal matches the source impedance of the test
13
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach 50% of the nominal quiescent
current. The time delays are on the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
V
S+
+
FB
22 µF
47 pF
0.1 µF
30.1 Ω
R
f
APPLICATION CIRCUITS
R
g
50-Ω Source
*2.5 V
_
+
Driving an Analog-to-Digital Converter With the
THS4302
V
O
THS4302
V
I
100 Ω
The THS4302 amplifier can be used to drive high-
performance analog-to-digital converters. Two
example circuits are presented below.
49.9 Ω
*2.5 V
The first circuit uses a wideband transformer to
convert a single-ended input signal into a differential
signal. The amplified signal from the output of the
THS4302 is fed through a low-pass filter, via an
isolation resistor and an ac-coupling capacitor, to the
transformer.
FB = Ferrite Bead
* = Low Impedance
Figure 45. DC-Coupled Single Supply Operation
Saving Power With Power-Down Functionality
For applications without signal content at dc, this
method of driving ADCs is useful. Where dc infor-
mation content is required, the THS4500 family of
fully differential amplifiers may be applicable.
The THS4302 features a power-down pin (PD) which
lowers the quiescent current from 37 mA down to
800 µA, ideal for reducing system power.
The power-down pin of the amplifier defaults to the
positive supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the negative rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and given in the specification tables. Above the
Enable Threshold Voltage, the device is on. Below
the Disable Threshold Voltage, the device is off.
Behavior in between these threshold voltages is not
specified.
V
S+
+
FB
22 µF
47 pF
0.1 µF
30.1 Ω
R
f
R
g
50-Ω Source
_
+
*2.5 V
THS4302
V
I
49.9 Ω
*2.5 V
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
0.1 µF
R
ISO
24.9 Ω
IN
16.5 Ω
ADS5422
14-Bit, 63 Msps
FB = Ferrite Bead
* = Low Impedance
IN CM
24.9 Ω
Figure 46. Driving an ADC Via a Transformer
The second circuit depicts single-ended ADC drive.
While not recommended for optimum performance
using converters with differential inputs, satisfactory
performance can sometimes be achieved with single-
ended input drive. An example circuit is shown here
for reference.
14
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
devices can easily cause this value to be exceeded.
Always consider this effect carefully, and add the
recommended series resistor as close as possible to
the THS4302 output pin (see Board Layout
Guidelines).
V
S+
+
FB
22 µF
47 pF
0.1 µF
30.1 Ω
The criterion for setting this R(ISO) resistor is a
maximum bandwidth, flat frequency response at the
load.
R
f
R
g
50-Ω Source
_
+
1
*2.5 V
THS4302
R
C
= 24.9 Ω,
(ISO)
= 10 pF
0.5
0
V
I
L
49.9 Ω
*2.5 V
-0.5
-1
R
(ISO)
= 8 Ω,
C
= 100 pF
L
FB = Ferrite Bead
* = Low Impedance
-1.5
-2
0.1 µF
R
ISO
R
= 12.1 Ω,
(ISO)
C
IN
= 47 pF
L
68 pf
ADS807
16.5 Ω
-2.5
-3
12-Bit,
53 Msps
V
= 5 V
S
CM
IN
10 M
100 M
f - Frequency - Hz
1 G
1.82 kΩ
0.1 µF
Figure 48. Driving Capacitive Loads
#IMPLIED. For best performance, high-speed
ADCs should be driven differentially. See
the THS4500 family of devices for more
information.
Power Supply Decoupling Techniques and
Recommendations
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of per-
formance.
Figure 47. Driving an ADC With a Single-Ended
Input
Driving Capacitive Loads
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading.
Often, the capacitive load is the input of an A/D
converter, including additional external capacitance,
which may be recommended to improve A/D linearity.
High-speed amplifiers like the THS4302 can be
susceptible to decreased stability and closed-loop
response peaking when a capacitive load is placed
directly on the output pin. When the amplifier's
open-loop output resistance is considered, this
capacitive load introduces an additional pole in the
signal path that can decrease the phase margin.
When the primary considerations are frequency re-
sponse flatness, pulse response fidelity, or distortion,
the simplest and most effective solution is to isolate
the capacitive load from the feedback loop by
inserting a series isolation resistor between the
amplifier output and the capacitive load.
1. Place decoupling capacitors as close to the
power supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply. Inductance in series
with the bypass capacitors will degrade perform-
ance. Note that a narrow lead or trace has about
0.8 nH of inductance for every millimeter of
length. Each printed-circuit board (PCB) via also
has between 0.3 and 0.8 nH depending on length
and diameter. For these reasons, it is rec-
ommended to use a power supply trace about the
width of the package for each power supply lead
to the capacitors, and 3 or more vias to connect
the capacitors to the ground plane.
2. Placement priority should put the smallest valued
capacitors closest to the device.
3. Solid power planes can lead to PCB resonances
when they are not properly terminated to the
ground plane over the area and along the per-
imeter of the power plane by high frequency
capacitors. Doing so ensures that there are no
power plane resonances in the needed frequency
range. Values used are in the range of 2 pF - 50
pF, depending on the frequencies to be
suppressed, with numerous vias for each. Using
The Typical Characteristics show the recommended
isolation resistor vs capacitive load and the resulting
frequency response at the load. Parasitic capacitive
loads greater than 2 pF can begin to degrade the
performance of the THS4302. Long PC board traces,
unmatched cables, and connections to multiple
15
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
0402 or smaller component sizes is rec-
ommended. An approximate expression for the
resonant frequencies associated with a length of
one of the power plane dimensions is given in the
following equation. Note that a power plane of
arbitrary shape can have a number of resonant
frequencies. A power plane without distributed
capacitors and with active parts near the center
of the plane usually has n even (≥ 2) due to the
BOARD LAYOUT
Printed-Circuit Board Layout Techniques for
Optimal Performance
Achieving optimum performance with a high fre-
quency amplifier like the THS4302 requires careful
attention to board layout parasitics and external
component types.
half wave resonant nature of the plane.
Recommendations that optimize performance include:
n (44GHz mm)
1. Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. However,
if using a transmission line at the I/O, then place
the matching resistor as close to the part as
possible. Except for when transmission lines are
used, parasitic capacitance on the output and the
noninverting input pins can react with the load
and source impedances to cause unintentional
band limiting. To reduce unwanted capacitance, a
window around the signal I/O pins should be
opened in all of the ground and power planes
around those pins. Otherwise, ground planes and
power planes (if used) should be unbroken else-
where on the board, and terminated as described
in the Power Supply Decoupling section.
frequencyres
[
ȏ
where:
frequency = the approximate power plane resonant
res
frequencies in GHz
= the length of the power plane dimensions in
ȏ
millimeters
n = an integer (n > 1) related to the mode of the oscillation
For guidance on capacitor spacing over the area
of the ground plane, specify the lowest resonant
frequency to be tolerated, then solve using the
equation above, with n = 2. Use this length for
the capacitor spacing. It is recommended that a
power plane, if used, be either small enough, or
decoupled as described, so that there are no
resonances in the frequency range of interest. An
alternative is to use a ferrite bead outside the
op-amp, high-frequency bypass capacitors to
decouple the amplifier, and mid- and
high-frequency bypass capacitors, from the
power plane. When a trace is used to deliver
power, its approximate self-resonance is given by
the equation above, substituting the trace length
for power plane dimension.
2. Minimize the distance (< 0.25”) from the
power supply pins to high frequency 0.1-µF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. Note that each millimeter of a line,
that is narrow relative to its length, has ~ 0.8 nH
of inductance. The power supply connections
should always be decoupled with the rec-
ommended capacitors. If not properly decoupled,
distortion performance is degraded. Larger
(6.8-µF to 22-µF) decoupling capacitors, effective
at lower frequency, should also be used on the
main supply lines, preferably decoupled from the
amplifier and mid- and high-frequency capacitors
by a ferrite bead. See the Power Supply Decoup-
ling Techniques section. The larger caps may be
placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board. A very low induct-
ance path should be used to connect the in-
verting pin of the amplifier to ground. A minimum
of 5 vias as close to the part as possible is
recommended.
4. Bypass capacitors, because they have
a
self-inductance, resonate with each other. To
achieve optimum transfer characteristics through
2 GHz, it is recommended that the bypass
arrangement employed in the prototype board be
used. The 30.1-Ω resistor in series with the
0.1-µF capacitor reduces the Q of the resonance
of the lumped parallel elements including the
0.1-µF and 47-pF capacitors, and the power
supply input of the amplifier. The ferrite bead
isolates the low-frequency 22-µF capacitor and
power plane from the remainder of the bypass
network.
5. By removing the 30.1-Ω resistor and ferrite bead,
the frequency response characteristic above 400
MHz may be modified. However, bandwidth, dis-
tortion, and transient response remain optimal.
6. Recommended values for power supply decoup-
ling include a bulk decoupling capacitor (22 µF),
a ferrite bead with a high self-resonant frequency,
a mid-range decoupling capacitor (0.1 µF) in
3. Careful selection and placement of external
components preserves the high frequency
performance of the THS4302. Resistors should
be a low reactance type. Surface-mount resistors
work best and allow a tighter overall layout.
Axially-leaded parts do not provide good high
frequency performance, because they have ~0.8
series with
a
30.1-Ω resistor, and
a
high-frequency decoupling capacitor (47 pF).
16
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
nH of inductance for every mm of current path
length. Again, keep PC board trace length as
short as possible. Never use wirewound type
resistors in a high frequency application. Because
the output pin and inverting input pin are the most
sensitive to parasitic capacitance, always position
the terminating resistors, if any, as close as
possible to the noninverting and output pins.
Even with a low parasitic capacitance shunting
the external resistors, excessively high resistor
values can create significant time constants that
can degrade performance. Good axial metal-film
or surface-mount resistors have approximately
0.2 pF in shunt with the resistor.
A 50-Ω environment is normally not necessary on
board as long as the lead lengths are short, and
in fact, a higher impedance environment im-
proves distortion as shown in the distortion ver-
sus load plots. Uncontrolled impedance traces
without double termination results in reflections at
each end, and hence, produces PCB resonances.
It is recommended that if this approach is used,
the trace length be kept short enough to avoid
resonances in the band of interest. For guidance
on useful lengths, use equation (1) given in the
Power Supply Decoupling Techniques section for
approximate resonance frequencies vs trace
length. This relation provides an upper bound on
the resonant frequency, because additional ca-
pacitive coupling to the trace from other leads or
the ground plane causes extra distributed loading
and slows the signal propagation along the trace.
4. Connections to other wideband devices on
the board may be made with short direct
traces or through onboard transmission lines.
For short connections, consider the trace and the
input to the next device as a lumped capacitive
load. Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and set RISO from the
plot of recommended RISO vs Capacitive Load.
Low parasitic capacitive loads (<4 pF) may not
need an RISO because THS4302 amplifiers are
nominally compensated to operate with a 2-pF
parasitic load. Higher parasitic capacitive loads
without an RISO are allowed as the signal gain
increases (increasing the unloaded phase mar-
gin). If a long trace is required, and the 6-dB
signal loss intrinsic to a doubly-terminated trans-
mission line is acceptable, implement a matched
impedance transmission line using microstrip or
stripline techniques (consult an ECL design hand-
book for microstrip and stripline layout tech-
niques). With a characteristic board trace im-
pedance defined based on board material and
trace dimensions, a matching series resistor into
the trace from the output of the THS4302 is used
as well as a terminating shunt resistor at the input
of the destination device. Remember also that the
terminating impedance is the parallel combination
of the shunt resistor and the input impedance of
the destination device: this total effective im-
pedance should be set to match the trace im-
pedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a
long trace can be series-terminated at the source
end only. Treat the trace as a capacitive load in
this case, and set the series resistor value as
shown in the plot of RISO vs Capacitive Load. This
does not preserve signal integrity as well as a
doubly terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
5. Socketing a high-speed part like the THS4302
is not recommended. The additional lead length
inductance and pin-to-pin capacitance introduced
by the socket creates an extremely troublesome
parasitic network, which can make it almost
impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the THS4302 onto the board.
PowerPAD™ DESIGN CONSIDERATIONS
The THS4302 is available in a thermally enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe on which the
die is mounted [see Figure 49(a) and Figure 49(b)].
This arrangement results in the lead frame being
exposed as a thermal pad on the underside of the
package [see Figure 49(c)]. Because this thermal pad
has direct thermal contact with the die, excellent
thermal performance can be achieved by providing a
good thermal path away from the thermal pad.
The PowerPAD package allows both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also
be soldered to a copper area underneath the pack-
age. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the heretofore awkward mechan-
ical methods of heatsinking.
17
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This resistance makes the
soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the IC
PowerPAD package should make their connec-
tion to the internal ground plane, with a complete
connection around the entire circumference of the
plated-through hole.
DIE
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 49. Views of Thermally Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
6. The top-side solder mask should leave the ter-
minals of the package and the thermal pad area
with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
0.144
0.049
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
0.012
Pin 1
0.0095
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This results in a part
that is properly installed.
0.015
0.144
0.0705
0.0195
0.010
vias
The next consideration is the package constraints.
The two sources of heat within an amplifier are
quiescent power and output power. The designer
should never forget about the quiescent heat gener-
ated within the device, especially multi-amplifier de-
vices. Because these devices have linear output
stages (Class AB), most of the heat dissipation is at
low output voltages with high output currents.
0.032
0.030
0.0245
Top View
Figure 50. PowerPAD PCB Etch and Via Pattern
The other key factor when dealing with power dissi-
pation is how the devices are mounted on the PCB.
The PowerPAD devices are extremely useful for heat
dissipation. But, the device should always be
soldered to a copper plane to fully use the heat
dissipation properties of the PowerPAD. The SOIC
package, on the other hand, is highly dependent on
how it is mounted on the PCB. As more trace and
PowerPAD™ PCB LAYOUT
CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as
shown in Figure 50. There should be etch for the
leads as well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad.
They holes should be 13 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
copper area is placed around the device,
ΘJA
decreases and the heat dissipation capability in-
creases. For a single package, the sum of the RMS
output currents and voltages should be used to
choose the proper package.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. They help dissipate the heat generated by
the IC. These additional vias may be larger than
the 13-mil diameter vias directly under the ther-
mal pad. They can be larger because they are
not in the thermal pad area to be soldered, so
that wicking is not a problem.
THERMAL ANALYSIS
The THS4302 device does not incorporate automatic
thermal shutoff protection, so the designer must take
care to ensure that the design does not violate the
absolute maximum junction temperature of the de-
vice. Failure may result if the absolute maximum
junction temperature of 150° C is exceeded.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
18
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
The thermal characteristics of the device are dictated
by the package and the PC board. For a given ΘJA,
maximum power dissipation for a package can be
calculated using the following formula.
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to consider not only quiescent power dissi-
pation, but also dynamic power dissipation. Often
maximum power is difficult to quantify because the
signal pattern is inconsistent, but an estimate of the
RMS power dissipation can provide visibility into a
possible problem.
Tmax–TA
qJA
PDmax
+
where:
P
is the maximum power dissipation in the amplifier (W).
Dmax
T
is the absolute maximum junction temperature (°C).
max
DESIGN TOOLS
T is the ambient temperature (°C).
A
θ
= θ + θ
JA
JC CA
θ
is the thermal coefficient from the silicon junctions to
Evaluation Fixtures and Application Support
Information
JC
the case (°C/W).
is the thermal coefficient from the case to ambient air
θ
CA
Texas Instruments is committed to providing its cus-
tomers with the highest quality of applications sup-
port. To support this goal, an evaluation board has
been developed for the THS4302 operational ampli-
fier. The evaluation board is available and easy to
use allowing for straight-forward evaluation of the
device. This evaluation board can be obtained by
ordering through the Texas Instruments Web site,
www.ti.com, or through your local Texas Instruments
Sales Representative. A schematic for the evaluation
board with default component values is shown in
Figure 52. Unpopulated footprints are shown to pro-
vide insight into design flexibility
(°C/W).
(1)
The THS4302 is offered in a 16-pin leadless MSOP
with PowerPAD. The thermal coefficient for the
MSOP PowerPAD package is substantially improved
over the traditional packages. Maximum power
dissipation levels are depicted in the graph below.
The data for the RGT package assumes a board
layout that follows the PowerPAD layout guidelines
referenced above and detailed in the PowerPAD
application notes in the Additional Reference Material
section at the end of the data sheet.
7
Computer simulation of circuit performance using
SPICE is often useful when analyzing the perform-
ance of analog circuits and systems. This is particu-
larly true for video and RF amplifier circuits where
parasitic capacitance and inductance can have a
major effect on circuit performance. A SPICE model
for the THS4500 family of devices is available
through the Texas Instruments web site (www.ti.com).
The Product Information Center (PIC) is available for
design assistance and detailed product information.
These models do a good job of predicting small
signal ac and transient performance under a wide
variety of operating conditions. They are not intended
to model the distortion characteristics of the amplifier,
nor do they attempt to distinguish between the
package types in their small signal ac performance.
Detailed information about what is and is not modeled
is contained in the model file itself.
6
16-Pin RGT Package
5
4
3
2
1
0
-40
-20
0
20
40
60
80
T
- Ambient Temperature - °C
A
θ
T
= 39.5°C/W for 16-Pin MSOP (RGT)
= 150°C, No Airflow
JA
J
Figure 51. Maximum Power Dissipation vs
Ambient Temperature
19
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
V
S+
FB2
J3
C2
C9
C6
*
+
C4
0.1 µF
47 pF
22 µF
R5
12 11 10
9
30.1 Ω
13
14
R
f
NC
8
7
6
5
R
g
_
+
R2
J2
J1
V
O
49.9 Ω
R3
*
PD
U1
V
I
J6
16
R4
49.9 Ω
C1
1
2
3
4
1 µF
C7
*
C8
V
S-
C5
0.1 µF
47 pF
J4
FB1
R4
30.1 Ω
C3
22 µF
+
* = Not populated
Figure 52. Typical THS4302 EVM Circuit Configuration
Figure 53. THS4302EVM Layout
(Top Layer and Silkscreen Layer)
Figure 54. THS4302EVM
Board Layout
(Ground Layers 2 and 3)
Figure 55. THS4302EVM
Board Layout
(Bottom Layer)
20
THS4302
www.ti.com
SLOS403G–OCTOBER 2002–REVISED JANUARY 2005
Table 1. BILL OF MATERIALS - THS4302RGT EVM
REFERENCE
DESIGNATOR
PCB
QUANTITY
MANUFACTURER'S
PART NUMBER
ITEM
DESCRIPTION
SMD SIZE
1
2
3
4
5
6
7
8
Bead, ferrite, 3 A, 80 Ω
1206
D
FB1, FB2
C2, C3
C1
2
2
1
2
2
2
2
1
(Steward) HI1206N800R-00
(AVX) TAJD226K025R
Cap. 22 µF, tantalum, 25 V, 10%
Cap. 1 µF, ceramic, 25 V, Y5V
Open
0805
0402
0402
0603
0402
0603
(AVX) 08053G105ZAT2A
C6, C7
C8, C9
C4, C5
R4, R5
R3
Cap. 47 pF, ceramic, 50 V, NPO
Cap. 0.1 µF, ceramic, 16 V, X7R
Resistor, 30.1Ω , 1/16 W, 1%
Open
(AVX) 04025A470JAT2A
(AVX) 0603YC104KAT2A
(KOA) RK73H1E30R1F
(Phycomp)
9C06031A49R9FKRFT
9
Resistor, 49.9 Ω, 1/16 W, 1%
0603
R1, R2
2
10
11
12
13
14
15
16
17
Jack, banana receptance, 0.25” dia. hole
Test point, red
J3, J4, J5
J6
3
1
1
2
1
4
4
1
(HH Smith) 101
(Keystone) 5000
Test point, black
TP1
(Keystone) 5001
Connector, edge, SMA PCB jack
IC THS4302
J1, J2
U1
(Johnson) 142-0701-801
(TI) THS4302RGT
(Keystone) 1808
Standoff, 4-40 hex, 0.625” length
Screw, phillips, 4-40, 0.250”
Board, printed-circuit
SHR-0440-016-SN
(TI) EDGE # 6443548 Rev. C
ADDITIONAL REFERENCE MATERIAL
•
•
PowerPAD Made Easy, application brief (SLMA004)
PowerPAD Thermally Enhanced Package, technical brief (SLMA002)
21
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device
THS4302RGTR
THS4302RGTRG4
THS4302RGTT
Status (1)
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGT
16
16
16
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
QFN
RGT
RGT
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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