THS6002IDWPRG4 [TI]
Dual Differential Line Driver/Receiver 20-SO PowerPAD;
| 型号： | THS6002IDWPRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Dual Differential Line Driver/Receiver 20-SO PowerPAD 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总45页 (文件大小：1265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
DWP PACKAGE
(TOP VIEW)
D
D
ADSL Differential Line Driver and Receiver
Driver Features
− 140 MHz Bandwidth (−3dB) With
25-Ω Load
− 315 MHz Bandwidth (−3dB) With
100-Ω Load
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
−
V
−
CC
CC
D1 OUT
D2 OUT
V
+
V
+
CC
CC
D1 IN+
D1 IN−
R1 IN−
R1 IN+
D2 IN+
D2 IN−
R2 IN−
R2 IN+
− 1000 V/µs Slew Rate, G = 2
− 400 mA Output Current Minimum Into
25-Ω Load
V
+
− −72 dB 3rd Order Harmonic Distortion at
CC
V
+
CC
R1 OUT
R2 OUT
f = 1 MHz, 25-Ω Load, and 20 V
O(PP)
V
−
CC
V
−
CC
D
Receiver Features
− 330 MHz Bandwidth (−3dB)
− 900 V/µs Slew Rate at G = 2
− −76 dB 3rd Order Harmonic Distortion at
f = 1 MHz, 150-Ω Load, and 20 V
O(PP)
D
D
D
Wide Supply Range 4.5 V to 16 V
Cross Section View Showing PowerPAD
Available in the PowerPAD Package
Improved Replacement for AD816 or
EL1501
D
Evaluation Module Available
description
The THS6002 contains two high-current, high-speed drivers and two high-speed receivers. These drivers and
receivers can be configured differentially for driving and receiving signals over low-impedance lines. The
THS6002 is ideally suited for asymmetrical digital subscriber line (ADSL) applications where it supports the
high-peak voltage and current requirements of that application. Both the drivers and the receivers are current
feedback amplifiers designed for the high slew rates necessary to support low total harmonic distortion (THD)
in ADSL applications. Separate power supply connections for each driver are provided to minimize crosstalk.
HIGH-SPEED xDSL LINE DRIVER/RECEIVER FAMILY
THD
f = 1 MHz
(dB)
V
BW
(MHz)
SR
(V/µs)
I
O
(mA)
n
DEVICE
DRIVER RECEIVER 5 V
5 V
15 V
(nV/√Hz)
THS6002
THS6012
THS6022
THS6062
THS7002
•
•
•
•
•
•
•
•
•
•
•
140
140
210
100
70
1000
1300
1900
100
−62
−65
−66
−72
−84
500
500
250
90
1.7
1.7
1.7
1.6
2.0
•
•
•
•
•
•
100
25
CAUTION: The THS6002 provides ESD protection circuitry. However, permanent damage can still occur if this device is subjected
to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance degradation or loss
of functionality.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
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Copyright 1999, Texas Instruments Incorporated
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ꢛ ꢟ ꢜ ꢛꢔ ꢕꢩ ꢗꢖ ꢚ ꢢꢢ ꢠꢚ ꢘ ꢚ ꢙ ꢟ ꢛ ꢟ ꢘ ꢜ ꢤ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ
ꢆ ꢇꢈꢉ ꢆ ꢊ ꢋ ꢋ ꢌꢍ ꢌꢎꢀ ꢊ ꢈꢉ ꢉꢊ ꢎ ꢌ ꢆꢍ ꢊ ꢏꢌ ꢍꢂ ꢈꢎꢆ ꢍꢌ ꢐꢌꢊꢏ ꢌꢍꢂ
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
description (continued)
The THS6002 is packaged in the patented PowerPAD package. This package provides outstanding thermal
characteristics in a small footprint package, which is fully compatible with automated surface mount assembly
procedures. The exposed thermal pad on the underside of the package is in direct contact with the die. By simply
soldering the pad to the PWB copper and using other thermal outlets, the heat is conducted away from the
junction.
AVAILABLE OPTIONS
PACKAGED DEVICE
PowerPAD PLASTIC
SMALL OUTLINE
(DWP)
T
A
EVALUATION
MODULE
†
0°C to 70°C
THS6002CDWP
THS6002IDWP
THS6002EVM
−40°C to 85°C
†
The DWP packages are available taped and reeled. Add an R suffix to the
device type (i.e., THS6002CDWPR)
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V
CC+
CC−
Input voltage, V (driver and receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
CC
I
Output current, I (driver) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mA
O
Output current, I (receiver) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
O
Differential input voltage, V (driver and receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
ID
Continuous total power dissipation at (or below) T = 25°C (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 W
A
Operating free air temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
A
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 125°C
stg
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The THS6002 incorporates a PowerPad on the underside of the chip. This acts as a heatsink and must be connected to a thermal
dissipation plane for proper power dissipation. Failure to do so can result in exceeding the maximum junction temperature, which could
permanently damage the device. See the Thermal Information section of this document for more information about PowerPad
technology.
recommended operating conditions
MIN
4.5
9
TYP
MAX
16
UNIT
Split supply
Single supply
C suffix
Supply voltage, V
CC+
and V
CC−
V
32
0
70
Operating free-air temperature, T
°C
A
I suffix
−40
85
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
functional block diagram
Driver 1
3
2
V
+
CC
4
5
D1 IN+
+
D1 OUT
_
D1 IN−
1
V
V
−
+
CC
Driver 2
18
CC
17
16
+
D2 IN+
D2 IN−
19
20
D2 OUT
_
V
CC
−
Receiver 1
8
9
V
CC
+
7
6
+
_
R1 IN+
R1 IN−
R1 OUT
10
13
V
−
CC
Receiver 2
V
CC
+
14
15
+
_
R2 IN+
R2 IN−
12
11
R2 OUT
V
CC
−
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
DRIVER
electrical characteristics, V
= 15 V, R = 25 Ω, R = 1 kΩ, T = 25°C (unless otherwise noted)
CC
L
F
A
†
PARAMETER
TEST CONDITIONS
Split supply
Single supply
MIN
4.5
9
TYP
MAX
16.5
33
UNIT
V
CC
Power supply operating range
V
3
to
−2.8
3.2
to
−3
V
CC
V
CC
V
CC
V
CC
=
5 V
Single ended
Differential
R
R
= 25 Ω
V
V
L
L
11.8
to
−11.5
12.5
to
−12.2
=
=
=
15 V
5 V
V
O
Output voltage swing
6
to
−5.6
6.4
to
−6
= 50 Ω
23.6
to
−23 −24.4
25
to
15 V
V
V
=
=
5 V
3.6
3.7
13.5
2
CC
V
V
Common-mode input voltage range
V
ICR
15 V
13.4
CC
T
= 25°C
5
7
A
Input offset voltage
V
V
=
=
5 V or 15 V
5 V or 15 V,
mV
IO
CC
T
A
= full range
= full range
= 25°C
Input offset voltage drift
T
A
20 µV/°C
CC
T
A
1.5
4
Differential input offset voltage
V
V
=
=
5 V or 15 V
5 V or 15 V,
mV
CC
T
A
= full range
= full range
= 25°C
5
Differential input offset voltage drift
T
A
10 µV/°C
CC
T
A
3
4
9
µA
12
Negative
T
A
= full range
= 25°C
T
A
10
µA
12
I
IB
Input bias current
Positive
V
CC
=
5 V or 15 V
T
A
= full range
= 25°C
T
A
1.5
8
µA
11
Differential
T
A
= full range
= 5 Ω
V
V
=
=
5 V,
R
R
500
500
800
1.5
5
CC
L
L
I
I
Output current (see Note 2)
mA
mA
O
15 V,
= 25 Ω
400
62
CC
Short-circuit output current (see Note 2)
Open loop transresistance
OS
V
V
=
=
5 V
CC
MΩ
15 V
CC
Common-mode rejection ratio
70
CMRR
V
CC
=
5 V or 15 V,
T
A
= full range
dB
dB
Differential common-mode rejection ratio
100
Crosstalk
Driver to driver
V = 200 mV,
I
f = 1 MHz
−62
†
Full range is 0°C to 70°C for the THS6002C and −40°C to 85°C for the THS6002I.
NOTE 2: A heat sink is required to keep the junction temperature below absolute maximum when an output is heavily loaded or shorted. See
absolute maximum ratings and Thermal Information section.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂ ꢃꢄ ꢄꢅ
ꢆꢇꢈ ꢉ ꢆꢊ ꢋꢋ ꢌꢍ ꢌꢎꢀ ꢊꢈ ꢉ ꢉ ꢊꢎꢌ ꢆꢍꢊ ꢏꢌ ꢍꢂ ꢈꢎꢆ ꢍꢌ ꢐꢌ ꢊ ꢏꢌ ꢍ ꢂ
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
DRIVER
electrical characteristics, V
(continued)
= 15 V, R = 25 Ω, R = 1 kΩ, T = 25°C (unless otherwise noted)
CC
L
F
A
†
PARAMETER
TEST CONDITIONS
MIN
−68
−65
−64
−62
TYP
MAX
UNIT
T
= 25°C
−74
A
V
=
=
5 V
dB
CC
T
A
= full range
= 25°C
PSRR
Power supply rejection ratio
T
−72
A
V
CC
15 V
dB
T
A
= full range
C
R
R
Differential input capacitance
Input resistance
1.4
300
13
pF
kΩ
Ω
I
I
Output resistance
Open loop
O
T
= 25°C
8.5
10
12
13
15
A
V
=
=
5 V
CC
CC
T
A
= full range
= 25°C
I
Quiescent current
mA
CC
T
A
11.5
V
15 V
T
A
= full range
†
Full range is 0°C to 70°C for the THS6002C and −40°C to 85°C for the THS6002I.
operating characteristics, V
= 15 V, R = 25 Ω, R = 1 kΩ, T = 25°C (unless otherwise noted)
CC
L
F
A
PARAMETER
TEST CONDITIONS
MIN
TYP
1000
70
MAX
UNIT
V/µs
ns
SR
Differential slew rate
Settling time to 0.1%
V
O
= 20 V
,
G = 2
G = 2
(PP)
t
s
0 V to 10 V Step,
V
= 20 V,R = 4 kΩ,
O(PP)
G = 5,
F
THD
Total harmonic distortion
Input voltage noise
−62
1.7
dBc
f = 1 MHz
V
=
5 V or 15 V,
5 V or 15 V,
f = 10 kHz,
Single-ended
CC
G = 2,
V
n
nV/√Hz
Positive (IN+)
Negative (IN−)
11.5
16
V
CC
G = 2
=
f = 10 kHz,
pA/√Hz
I
n
Input noise current
V
V
=
=
5 V
90
110
140
MHz
MHz
V = 200 mV, G = 1,
CC
I
R
= 680 Ω
15 V
110
F
CC
V = 200 mV, G = 2,
I
V
CC
V
CC
V
CC
=
=
=
15 V
15 V
15 V
120
315
265
MHz
MHz
MHz
R
= 620 Ω
F
Small-signal bandwidth (−3 dB)
V = 200 mV, G = 1,
I
F
BW
R
= 820 Ω,
R = 100 Ω
L
V = 200 mV, G = 2,
I
F
R
= 560 Ω,
R = 100 Ω
L
V
V
=
=
5 V
30
40
V = 200 mV, G = 1,
CC
I
Bandwidth for 0.1 dB flatness
MHz
MHz
R
= 680 Ω
15 V
F
CC
Full power bandwidth (see Note 3)
V
O
= 20 V
(PP)
16
V
CC
V
CC
V
CC
V
CC
=
=
=
=
5 V
0.04%
0.05%
0.07°
0.08°
G = 2,
NTSC,
A
Differential gain error
Differential phase error
D
R
= 150 Ω, 40 IRE
15 V
5 V
L
G = 2,
NTSC,
φ
D
R
= 150 Ω, 40 IRE
15 V
L
NOTE 3: Full power bandwidth = slew rate/2πV
peak
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢄ ꢅ
ꢆ ꢇꢈꢉ ꢆ ꢊ ꢋ ꢋ ꢌꢍ ꢌꢎꢀ ꢊ ꢈꢉ ꢉꢊ ꢎ ꢌ ꢆꢍ ꢊ ꢏꢌ ꢍꢂ ꢈꢎꢆ ꢍꢌ ꢐꢌꢊꢏ ꢌꢍꢂ
ꢑ
ꢑ
SLOS202E− JANUARY 1998− REVISED MARCH 2007
RECEIVER
electrical characteristics, V
= 15 V, R = 150 Ω, R = 1 kΩ, T = 25°C (unless otherwise noted)
CC
L
F
A
†
PARAMETER
TEST CONDITIONS
MIN
4.5
9
TYP
MAX
16.5
33
UNIT
Split supply
Single supply
V
V
V
Power supply operating range
V
CC
V
V
V
V
=
=
=
=
5 V
3
3.3
12.8
3.7
CC
CC
CC
CC
Output voltage swing
Single ended
V
V
O
15 V
5 V
12.4
3.6
13.4
Common-mode input voltage range
ICR
15 V
13.5
1
T
= 25°C
4
6
A
Single ended
T
A
= full range
= 25°C
V
IO
Input offset voltage
V
CC
=
5 V or 15 V
mV
T
A
1.5
4
Differential
T
A
= full range
5
Single ended
Differential
20
10
8
Input offset voltage drift
V
V
=
=
5 V or 15 V
5 V or 15 ,
µV/°C
CC
T
= 25°C
2
3.5
1.5
A
Negative
Positive
CC
T
A
= full range
= 25°C
10
9
T
A
I
Input bias current
V
=
=
5 V or 15 V
5 V or 15 V
µA
IB
CC
CC
T
A
= full range
= 25°C
11
8
T
A
Differential
V
T
A
= full range
= 25 Ω
10
V
V
=
=
5 V
R
R
95
85
CC
L
L
I
I
Output current (see Note 2)
mA
mA
O
15 V
= 150 Ω
80
60
CC
Short-circuit output current (see Note 2)
Open loop transresistance
R
= 25 Ω
110
1.5
5
OS
L
V
=
=
5 V
CC
CC
MΩ
V
15 V
Single ended
Differential
70
CMRR Common-mode rejection ratio
Crosstalk (receiver to receiver)
V
CC
=
5 V or 15 V,
T
A
= full range
dB
dB
100
V = 200 mV,
I
f = 1 MHz
−67
−74
T
A
= 25°C
−66
−63
−65
−62
V
=
=
5 V
CC
CC
T
A
= full range
= 25°C
PSRR
Power supply rejection ratio
dB
T
A
−72
V
15 V
T
A
= full range
R
C
R
Input resistance
300
1.4
10
kΩ
pF
Ω
I
Differential input capacitance
Output resistance
I
Open loop
O
†
Full range is 0°C to 70°C for the THS6002C and −40°C to 85°C for the THS6002I.
NOTE 2: A heat sink is required to keep junction temperature below absolute maximum when an output is heavily loaded or shorted. See absolute
maximum ratings and Thermal Information section.
6
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ꢑ
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
RECEIVER
electrical characteristics, V
(continued)
= 15 V, R = 150 Ω, R = 1 kΩ, T = 25°C (unless otherwise noted)
CC
L
F
A
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
5.5
7.5
7
UNIT
T
= 25°C
4.2
A
V
=
=
5 V
CC
T
A
= full range
= 25°C
I
Quiescent current
mA
CC
T
5
A
V
CC
15 V
T
A
= full range
9
†
Full range is 0°C to 70°C for the THS6002C and −40°C to 85°C for the THS6002I.
operating characteristics, V
= 15 V, R = 150 Ω, R = 1 kΩ, T = 25°C (unless otherwise noted)
CC
L
F
A
PARAMETER
TEST CONDITIONS
MIN
TYP
900
50
MAX
UNIT
V/µs
ns
SR
Differential slew rate
Settling time to 0.1%
V
= 10 V
,
G = 2
G = 2
O
(PP)
t
s
10 V Step,
V
= 20 V,
R = 510 Ω,
F
O(PP)
G = 5,
THD
Total harmonic distortion
Input voltage noise
−68
1.7
dBc
f =1 MHz
V
CC
G = 2
=
5 V or 15 V
f = 10 kHz,
V
n
nV/√Hz
Positive (IN+)
Negative (IN−)
11.5
16
V
=
5 V or 15 V,
f = 10 kHz,
CC
G = 2
pA/√Hz
I
n
Input current noise
V
V
=
=
5 V
270
300
300
330
V = 200 mV,
G = 1,
G = 2,
G = 1,
CC
I
MHz
MHz
R
= 560 Ω
15 V
F
CC
Small-signal bandwidth (−3 dB)
V = 200 mV,
I
F
V
CC
=
15 V
285
BW
R
= 430 Ω
V
V
=
=
5 V
20
25
V = 200 mV,
CC
I
F
Bandwidth for 0.1 dB flatness
MHz
MHz
R
= 560 Ω
15 V
CC
Full power bandwidth (see Note 3)
V
O
= 20 V
(PP)
14
V
CC
V
CC
V
CC
V
CC
=
=
=
=
5 V
0.09%
0.1%
0.13°
0.16°
40 IRE,
= 150 Ω,
G = 2,
NTSC
A
Differential gain error
Differential phase error
D
R
15 V
5 V
L
40 IRE,
= 150 Ω,
G = 2,
NTSC
φ
D
R
15 V
L
NOTE 3: Full power bandwidth = slew rate/2πV
peak
7
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
PARAMETER MEASUREMENT INFORMATION
1 kΩ
1 kΩ
1 kΩ
1 kΩ
−
+
−
+
Driver 1
Driver 2
V
O
V
O
V
I
V
I
25 Ω
25 Ω
50 Ω
50 Ω
Figure 1. Driver Input-to-Output Crosstalk Test Circuit
1 kΩ
1 kΩ
1 kΩ
1 kΩ
−
+
−
+
Receiver 1
Receiver 2
V
O
V
O
V
I
V
I
150 Ω
150 Ω
50 Ω
50 Ω
Figure 2. Receiver Input-to-Output Crosstalk Test Circuit
R
R
F
G
15 V
−
Driver
V
O
+
V
I
R
25 Ω
L
50 Ω
−15 V
Figure 3. Driver Test Circuit, Gain = 1 + (R /R )
F
G
R
R
F
G
15 V
−
Receiver
V
O
V
I
+
R
150 Ω
L
50 Ω
−15 V
Figure 4. Receiver Test Circuit, Gain = 1 + (R /R )
F
G
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢑ
ꢑ
SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Supply current
Driver and Receiver
Driver and Receiver
Driver and Receiver
Driver and Receiver
Driver
vs Supply voltage
vs Frequency
5
6
Input voltage noise
Input current noise
vs Frequency
6
Closed-loop output impedance
vs Frequency
7
vs Supply voltage
vs Supply voltage
vs Load resistance
vs Load resistance
vs Free-air temperature
vs Free-air temperature
vs Free-air temperature
vs Free-air temperature
vs Free-air temperature
vs Free-air temperature
vs Frequency
8
Peak-to-peak output voltage swing
Peak-to-peak output voltage
Input offset voltage
Receiver
31
Driver
9
Receiver
32
Driver
10
V
IO
Receiver
33
Driver
11
I
IB
Input bias current
Receiver
34
Driver
12
CMMR Common-mode rejection ratio
Input-to-output crosstalk
Receiver
35
Driver
13
Receiver
vs Frequency
36
Driver-to-receiver crosstalk
Receiver-to-driver crosstalk
vs Frequency
14
vs Frequency
37
Driver
vs Free-air temperature
vs Free-air temperature
vs Free-air temperature
vs Free-air temperature
vs Frequency
15
PSSR
Power supply rejection ratio
Supply current
Receiver
Driver
38
16
I
CC
Receiver
Driver
39
17, 18
40, 41
19 − 22
23
Normalized frequency response
Receiver
Driver
vs Frequency
Normalized output response
Single-ended output distortion
Output distortion
vs Frequency
Driver
vs Output voltage
vs Output voltage
Receiver
42
Small and large signal frequency response
Receiver
43, 44
24, 25
26, 27
45, 46
47, 48
24, 25
26, 27
45, 46
47, 48
28 − 30
49 − 51
DC input offset voltage
Number of 150-Ω loads
DC input offset voltage
Number of 150-Ω loads
DC input offset voltage
Number of 150-Ω loads
DC input offset voltage
Number of 150-Ω loads
Driver
Differential gain
Receiver
Driver
Differential phase
Receiver
Driver
Output step response
Receiver
9
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
DRIVER AND RECEIVER
SUPPLY CURRENT
vs
DRIVER AND RECEIVER
INPUT VOLTAGE AND CURRENT NOISE
vs
SUPPLY VOLTAGE
FREQUENCY
12
11
10
9
100
10
1
100
10
1
V
T
A
=
15 V
CC
= 25°C
Driver
8
7
6
5
I
I
Noise
Noise
n−
n+
Receiver
4
3
2
T
R
= 25°C
= 1 kΩ
A
F
V
n
Noise
1
0
Gain = +1
5
6
7
8
9
10
11 12 13 14 15
10
100
1k
10k
100k
V
CC
− Supply Voltage − V
f − Frequency − Hz
Figure 5
Figure 6
DRIVER AND RECEIVER
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
200
100
V
R
=
15 V
CC
F
= 1 kΩ
Gain = 2
T
V
= 25°C
A
10
1
= 1 V
I(PP)
Receiver
Driver
0.1
V
O
1 kΩ
1 kΩ
1 kΩ
−
+
V
I
THS6002
1000
0.01
50 Ω
V
I
Z
=
− 1
o
)
(
V
O
0.001
100k
1M
10M
100M
500M
f − Frequency − Hz
Figure 7
10
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ꢑ
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
DRIVER
DRIVER
PEAK-TO-PEAK OUTPUT VOLTAGE SWING
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
vs
SUPPLY VOLTAGE
LOAD RESISTANCE
15
10
15
10
5
V
=
15 V
5 V
CC
V
=
CC
5
0
T
R
= 25°C
= 1 kΩ
A
F
0
Gain = 1
V
=
5 V
−5
−10
−15
CC
−5
−10
−15
T
R
R
= 25°C
= 1 kΩ
= 25 Ω
A
F
L
V
CC
=
15 V
Gain = 1
5
6
7
8
9
10
11 12 13 14 15
10
100
1000
V
CC
− Supply Voltage − V
R
− Load Resistance − Ω
L
Figure 8
Figure 9
DRIVER
DRIVER
INPUT OFFSET VOLTAGE
vs
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
2
1
5
4
3
G = 1
= 1 kΩ
ꢀꢁꢁ ꢂꢃꢄ ꢅ ꢆꢁ ꢇ
V
I
= 15 V
CC
IB+
G = 1
R
F
R
= 1 kΩ
F
V
= 5 V
V
CC
=
5 V
CC
IB+
0
I
−1
−2
−3
2
1
0
V
CC
= 15 V
V
I
=
5 V
V
I
=
15 V
80
CC
IB−
CC
IB−
−4
−5
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 10
Figure 11
11
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ꢑ
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
DRIVER
DRIVER
INPUT-TO-OUTPUT CROSSTALK
vs
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
FREQUENCY
80
75
70
0
−10
−20
−30
−40
V
R
R
= 15 V
= 1 kΩ
= 25 Ω
CC
F
L
Gain = 2
V = 200 mV
I
See Figure 1
V
=
15 V
5 V
CC
Driver 1 = Output
Driver 2 = Input
−50
−60
−70
V
=
CC
1 kΩ
65
60
1 kΩ
1 kΩ
−
+
V
O
V
I
Driver 1 = Input
Driver 2 = Output
1 kΩ
−80
−90
−40 −20
0
20
40
60
80
100k
1M
10M
f − Frequency − Hz
100M
500M
T
A
− Free-Air Temperature − °C
Figure 12
Figure 13
DRIVER
DRIVER-TO-RECEIVER CROSSTALK
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREE-AIR TEMPERATURE
0
−10
−20
−30
−40
95
90
85
80
75
V
R
=
15 V
CC
F
G = 1
= 1 kΩ
= 1 kΩ
R
F
Gain = 2
V = 200 mV
I
See Figures 1 and 2
Receiver 2 = Output
Driver 2 = Input
V
= 15 V
CC
Receiver 1 = Output
Driver 1 = Input
V
CC
= 5 V
−50
−60
−70
V
CC
= −5 V
Receiver 1 = Output
Driver 2 = Input
V
CC
= −15 V
70
65
Receiver 2 = Output
Driver 1 = Input
−80
−90
100k
1M
10M
100M
500M
−40 −20
0
20
40
60
80
100
f − Frequency − Hz
T
A
− Free-Air Temperature − °C
Figure 14
Figure 15
12
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ꢑ
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
DRIVER
DRIVER
SUPPLY CURRENT
vs
NORMALIZED FREQUENCY RESPONSE
vs
FREQUENCY
FREE-AIR TEMPERATURE
2
1
13
12
10
8
R
= 300 Ω
F
V
CC
= 15 V
0
−1
−2
−3
V
CC
= 5 V
R
= 510 Ω
= 750 Ω
F
R
F
R
= 1 kΩ
6
F
−4
−5
−6
4
V
=
15 V
CC
V = 200 mV
I
R
= 25 Ω
L
2
0
Gain = 1
= 25°C
−7
−8
T
A
100
1M
10M
100M
500M
−40 −20
0
20
40
60
80
100
f − Frequency − Hz
T
A
− Free-Air Temperature − °C
Figure 16
Figure 17
DRIVER
DRIVER
NORMALIZED FREQUENCY RESPONSE
NORMALIZED OUTPUT RESPONSE
vs
vs
FREQUENCY
FREQUENCY
2
1
R
= 200 Ω
R
= 360 Ω
L
F
1
0
0
−1
−2
−3
−4
−1
−2
R
= 100 Ω
L
−3
−4
−5
R
= 50 Ω
L
R
= 470 Ω
F
R
= 25 Ω
L
−5
−6
−7
R
= 620 Ω
−6
−7
F
V
V
R
= 15 V
= 200 mV
= 25 Ω
CC
in
L
V
R
=
15 V
CC
F
−8
= 1 kΩ
Gain = 2
= 25°C
Gain = 1
V = 200 mV
I
−8
−9
−9
R
= 1 kΩ
F
T
A
−10
100K
1M
10M
100M
500M
100k
1M
10M
100M
500M
f − Frequency − Hz
f − Frequency − Hz
Figure 18
Figure 19
13
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ꢑ
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
DRIVER
DRIVER
NORMALIZED OUTPUT RESPONSE
NORMALIZED OUTPUT RESPONSE
vs
vs
FREQUENCY
FREQUENCY
1
3
R
= 620 Ω
F
0
−1
−2
−3
−4
2
1
R
= 820 Ω
F
0
−1
−2
R
= 1 kΩ
F
R
R
= 25 Ω
L
= 200 Ω
= 100 Ω
−5
−6
−7
−3
−4
−5
L
R
L
R
= 50 Ω
L
V
R
=
15 V
V
=
15 V
R = 100 Ω
L
CC
F
CC
= 1 kΩ
Gain = 2
V = 200 mV
Gain = 1
V = 200 mV
−8
−9
−6
−7
I
I
100k
1M
10M
f − Frequency − Hz
100M
500M
100k
1M
10M
100M
500M
f − Frequency − Hz
Figure 20
Figure 21
DRIVER
DRIVER
NORMALIZED OUTPUT RESPONSE
SINGLE-ENDED OUTPUT DISTORTION
vs
vs
FREQUENCY
OUTPUT VOLTAGE
0
3
V
R
R
= 15 V
= 4 kΩ
= 25 Ω
CC
F
L
R
= 430 Ω
F
−10
−20
−30
−40
2
1
f = 1 MHz
Gain = 5
0
−1
−2
R
= 620 Ω
F
−50
−60
−70
2nd Harmonic
R
= 1 kΩ
F
−3
−4
−5
−6
V
R
=
15 V
CC
L
= 100 Ω
3rd Harmonic
15
−80
−90
Gain = 2
V = 200 mV
I
100k
1M
10M
f − Frequency − Hz
100M
500M
0
5
10
20
V
− Output Voltage − V
O(PP)
Figure 22
Figure 23
14
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ꢑ
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
DRIVER
DIFFERENTIAL GAIN AND PHASE
vs
DC INPUT OFFSET VOLTAGE
0.05
0.10
0.08
0.06
0.04
0.02
V
R
R
= 15 V
= 150 Ω
= 1 kΩ
CC
L
F
Gain
0.04
0.03
0.02
0.01
0
f = 3.58 MHz
Gain = 2
40 IRE Modulation
Phase
0
0.7
−0.7 −0.5
−0.3 −0.1
0.1
0.3
0.5
DC Input Offset Voltage − V
Figure 24
DRIVER
DIFFERENTIAL GAIN AND PHASE
vs
DC INPUT OFFSET VOLTAGE
0.05
0.10
0.08
0.06
0.04
0.02
V
R
R
= 5 V
= 150 Ω
= 1 kΩ
CC
L
F
0.04
0.03
0.02
0.01
0
f = 3.58 MHz
Gain = 2
40 IRE Modulation
Gain
Phase
0
0.7
−0.7 −0.5
−0.3 −0.1
0.1
0.3
0.5
DC Input Offset Voltage − V
Figure 25
15
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ꢑ
ꢑ
SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
DRIVER
DIFFERENTIAL GAIN AND PHASE
vs
NUMBER OF 150-Ω LOADS
0.15
0.25
0.20
0.15
0.10
V
R
=
15 V
CC
F
= 1 kΩ
Gain = 2
0.12
0.09
0.06
0.03
0
f = 3.58 MHz
40 IRE Modulation
100 IRE Ramp
Phase
Gain
0.05
0
1
2
3
4
5
6
7
8
Number of 150-Ω Loads
Figure 26
DRIVER
DIFFERENTIAL GAIN AND PHASE
vs
NUMBER OF 150-Ω LOADS
0.15
0.25
0.20
0.15
0.10
V
R
=
5 V
CC
F
= 1 kΩ
Gain = 2
0.12
0.09
0.06
0.03
0
f = 3.58 MHz
40 IRE Modulation
100 IRE Ramp
Gain
0.05
0
Phase
6
1
2
3
4
5
7
8
Number of 150-Ω Loads
Figure 27
16
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
DRIVER OUTPUT
10 V STEP RESPONSE
DRIVER OUTPUT
400 mV STEP RESPONSE
8
6
400
300
200
100
0
4
2
0
−2
−4
−100
−200
V
=
15 V
CC
V
=
15 V
CC
Gain = 2
R
R
Gain = 2
R
R
= 25 Ω
= 1 kΩ
L
F
= 25 Ω
= 1 kΩ
L
F
t /t = 5 ns
r f
−6
−8
−300
−400
t /t = 300 ps
r f
See Figure 3
See Figure 3
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
t − Time − ns
t − Time − ns
Figure 28
Figure 29
DRIVER OUTPUT
20 V STEP RESPONSE
16
12
8
V
=
15 V
CC
Gain = 5
R
R
= 25 Ω
= 2 kΩ
L
F
t /t = 5 ns
r f
See Figure 3
4
0
−4
−8
−12
−16
0
50 100 150 200 250 300 350 400 450 500
t − Time − ns
Figure 30
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
RECEIVER
RECEIVER
PEAK-TO-PEAK OUTPUT VOLTAGE SWING
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
vs
SUPPLY VOLTAGE
LOAD RESISTANCE
15
10
15
10
5
T
R
= 25°C
= 1 kΩ
A
F
V
=
15 V
5 V
CC
Gain = 1
V
=
CC
5
0
0
−5
−10
−15
V
=
5 V
−5
−10
−15
CC
T
R
R
= 25°C
= 1 kΩ
= 150 Ω
A
F
L
V
CC
=
15 V
Gain = 1
5
6
7
8
9
10
11 12 13 14 15
10
100
R − Load Resistance − Ω
L
1000
V
CC
− Supply Voltage − V
Figure 31
Figure 32
RECEIVER
RECEIVER
INPUT OFFSET VOLTAGE
vs
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.5
0
5
4
3
G = 1
G = 1
R = 1 kΩ
F
R
= 1 kΩ
F
V
I
=
15 V
5 V
V
CC
=
5 V
CC
IB+
−0.5
V
CC
IB+
=
I
−1
2
1
0
V
CC
= 15 V
V
I
= 15 V
CC
IB−
V
I
= 5 V
CC
IB−
−1.5
−2
−40 −20
0
20
40
60
80
100
−40 −20
0
20
40
60
80
100
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 33
Figure 34
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
RECEIVER
COMMON-MODE REJECTION RATIO
vs
RECEIVER
INPUT-TO-OUTPUT CROSSTALK
vs
FREE-AIR TEMPERATURE
FREQUENCY
85
80
75
70
65
0
−10
−20
−30
−40
V
R
R
= 15 V
= 1 kΩ
= 150 Ω
CC
F
L
Gain = 2
V = 200 mV
I
ꢀꢁꢁ ꢂꢃꢄ ꢅ ꢆꢁ ꢇ
V
=
15 V
Receiver 1 = Output
Receiver 2 = Input
CC
−50
−60
−70
V
=
5 V
CC
1 kΩ
1 kΩ
1 kΩ
−
+
V
O
V
I
Receiver 1 = Input
Receiver 2 = Output
60
55
1 kΩ
−80
−90
−40 −20
0
20
40
60
80
100
100k
1M
10M
100M
500M
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 35
Figure 36
RECEIVER
POWER SUPPLY REJECTION RATIO
RECEIVER-TO-DRIVER CROSSTALK
vs
vs
FREE-AIR TEMPERATURE
FREQUENCY
95
90
85
80
75
0
−10
−20
−30
−40
V
R
=
15 V
CC
F
G = 1
= 1 kΩ
= 1 kΩ
R
F
Gain = 2
Receiver 2 = Input
Driver 2 = Output
V
CC
= 15 V
Receiver 1 = Input
Driver 1 = Output
V
CC
= 5 V
−50
−60
−70
V
= −15 V
CC
Receiver 1 = Input
Driver 2 = Output
V
= −5 V
CC
70
65
−80
−90
Receiver 2 = Input
Driver 1 = Output
−40 −20
0
20
40
60
80
100
100k
1M
10M
100M
500M
f − Frequency − Hz
T
A
− Free-Air Temperature − °C
Figure 37
Figure 38
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
RECEIVER
SUPPLY CURRENT
vs
RECEIVER
NORMALIZED OUTPUT RESPONSE
vs
FREE-AIR TEMPERATURE
FREQUENCY
7
6
3
V
R
=
15 V
CC
L
= 150 Ω
2
1
Gain = 1
V = 200 mV
I
R
= 360 Ω
F
V
=
15 V
5 V
CC
5
0
−1
−2
4
3
2
V
=
CC
R
= 510 Ω
= 750 Ω
F
−3
−4
−5
R
F
R
= 1 kΩ
F
1
0
−6
−7
−40 −20
0
20
40
60
80
100
100k
1M
10M
100M
500M
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 39
Figure 40
RECEIVER
RECEIVER
NORMALIZED OUTPUT RESPONSE
OUTPUT DISTORTION
vs
vs
FREQUENCY
OUTPUT VOLTAGE
0
−10
−20
−30
−40
1
0
V
R
R
= 15 V
= 510 Ω
= 150 Ω
CC
F
L
f = 1 MHz
Gain = 5
−1
−2
−3
−4
R
= 360 Ω
= 510 Ω
= 620 Ω
F
F
R
F
R
−50
−60
−70
−5
−6
−7
2nd Harmonic
R
= 1 kΩ
F
V
R
=
15 V
CC
L
−80
−90
= 150 Ω
3rd Harmonic
15
Gain = 2
V = 200 mV
−8
−9
I
−100
100k
1M
10M
f − Frequency − Hz
100M
500M
0
5
10
20
V
− Output Voltage − V
O(PP)
Figure 41
Figure 42
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
RECEIVER
RECEIVER
SMALL AND LARGE SIGNAL
FREQUENCY RESPONSE
SMALL AND LARGE SIGNAL
FREQUENCY RESPONSE
−3
−6
3
0
V = 500 mV
I
V = 500 mV
I
−9
−3
V = 250 mV
I
V = 250 mV
I
−12
−15
−18
−21
−24
−6
−9
V = 125 mV
I
V = 125 mV
I
−12
−15
−18
V = 62.5 mV
I
V = 62.5 mV
I
V
=
15 V
V
=
15 V
CC
CC
R
R
= 510 Ω
= 150 Ω
R
R
= 390 Ω
= 150 Ω
F
L
F
L
−27
−30
−21
−24
Gain = 1
Gain = 2
100k
1M
10M
100M
500M
100k
1M
10M
100M
500M
f − Frequency − Hz
f − Frequency − Hz
Figure 43
Figure 44
RECEIVER
DIFFERENTIAL GAIN AND PHASE
vs
DC INPUT OFFSET VOLTAGE
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.20
V
R
R
= 15 V
= 150 Ω
= 1 kΩ
CC
L
F
Gain
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
f = 3.58 MHz
Gain = 2
40 IRE Modulation
Phase
0.01
0
0.02
0
−0.7 −0.5
−0.3 −0.1
0.1
0.3
0.5
0.7
DC Input Offset Voltage − V
Figure 45
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
RECEIVER
DIFFERENTIAL GAIN AND PHASE
vs
DC INPUT OFFSET VOLTAGE
0.10
V
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
=
5 V
CC
L
F
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
R
R
= 150 Ω
= 1 kΩ
f = 3.58 MHz
Gain = 2
40 IRE Modulation
Gain
0.01
0
0.02
0
Phase
0.5
−0.7 −0.5
−0.3 −0.1
0.1
0.3
0.7
DC Input Offset Voltage − V
Figure 46
RECEIVER
DIFFERENTIAL GAIN AND PHASE
vs
NUMBER OF 150-Ω LOADS
0.25
0.20
0.15
0.10
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
R
=
15 V
CC
F
= 1 kΩ
Gain = 2
f = 3.58 MHz
40 IRE Modulation
100 IRE Ramp
Gain
Phase
0.05
0
1
2
3
4
5
6
7
8
Number of 150-Ω Loads
Figure 47
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
RECEIVER
DIFFERENTIAL GAIN AND PHASE
vs
NUMBER OF 150-Ω LOADS
0.25
0.20
0.15
0.10
0.05
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
R
=
5 V
CC
F
= 1 kΩ
Gain = 2
f = 3.58 MHz
40 IRE Modulation
100 IRE Ramp
Phase
Gain
0
8
1
2
3
4
5
6
7
Number of 150-Ω Loads
Figure 48
RECEIVER OUTPUT
400-mV STEP RESPONSE
RECEIVER OUTPUT
10-V STEP RESPONSE
400
300
200
100
0
9
7
5
3
1
−100
−200
−1
−3
Gain = +2
Gain = +2
R
R
= 150 Ω
= 1 kΩ
L
F
R
R
= 150 Ω
= 1 kΩ
L
F
t /t = 300 ps
r f
t /t = 5 ns
−300
−400
−5
−7
r f
See Figure 4
See Figure 4
0
50 100 150 200 250 300 350 400 450 500
t − Time − ns
0
50 100 150 200 250 300 350 400 450 500
t − Time − ns
Figure 49
Figure 50
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
TYPICAL CHARACTERISTICS
RECEIVER OUTPUT
20 V STEP RESPONSE
16
12
8
V
=
15 V
CC
Gain = 5
R
R
= 150 Ω
= 2 kΩ
L
F
t /t = 5 ns
r f
See Figure 4
4
0
−4
−8
−12
−16
0
50 100 150 200 250 300 350 400 450 500
t − Time − ns
Figure 51
APPLICATION INFORMATION
The THS6002 contains four independent operational amplifiers. Two are designated as drivers because of their
high output current capability, and two are designated as receivers. The receiver amplifiers are current feedback
topology amplifiers made for high-speed operation and are capable of driving output loads of at least 80 mA.
The drivers are also current feedback topology amplifiers. However, the drivers have been specifically designed
to deliver the full power requirements of ADSL and therefore can deliver output currents of at least 400 mA at
full output voltage.
The THS6002 is fabricated using Texas Instruments 30-V complementary bipolar process, HVBiCOM. This
process provides excellent isolation and high slew rates that result in the device’s excellent crosstalk and
extremely low distortion.
independent power supplies
Each amplifier of the THS6002 has its own power supply pins. This was specifically done to solve a problem
that often occurs when multiple devices in the same package share common power pins. This problem is
crosstalk between the individual devices caused by currents flowing in common connections. Whenever the
current required by one device flows through a common connection shared with another device, this current,
in conjunction with the impedance in the shared line, produces an unwanted voltage on the power supply. Proper
power supply decoupling and good device power supply rejection helps to reduce this unwanted signal. What
is left is crosstalk.
However, with independent power supply pins for each device, the effects of crosstalk through common
impedance in the power supplies is more easily managed. This is because it is much easier to achieve low
common impedance on the PCB with copper etch than it is to achieve low impedance within the package with
either bond wires or metal traces on silicon.
24
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
APPLICATION INFORMATION
power supply restrictions
Although the THS6002 is specified for operation from power supplies of 5 V to 15 V (or singled-ended power
supply operation from 10 V to 30 V), and each amplifier has its own power supply pins, several precautions must
be taken to assure proper operation.
1. The power supplies for each amplifier must be the same value. For example, if the drivers use 15 volts,
then the receivers must also use 15 volts. Using 15 volts for one amplifier and 5 volts for another
amplifier is not allowed.
2. To save power by powering down some of the amplifiers in the package, the following rules must be
followed.
• The amplifier designated Receiver 1 must always receive power whenever any other amplifier(s) within
the package is used. This is because the internal startup circuitry uses the power from the Receiver 1
device.
• The −V
pins from all four devices must always be at the same potential.
CC
• Individual amplifiers are powered down by simply opening the +V
connection.
CC
As an example, if only the two drivers within the THS6002 are used, then the package power is reduced by
removing the +V connection to Receiver 2. This reduces the power consumption by an amount equal to the
CC
quiescent power of a single receiver amplifier. The +V
connections to Receiver 1 and both drivers are
CC
required. Also, all four amplifiers must be connected to −V , including Receiver 2.
CC
The THS6002 incorporates a standard Class A-B output stage. This means that some of the quiescent current
is directed to the load as the load current increases. So under heavy load conditions, accurate power dissipation
calculations are best achieved through actual measurements. For small loads, however, internal power
dissipation for each amplifier in the THS6002 can be approximated by the following formula:
V
O
≅ ǒ2 VCC CCǓ) ǒVCC
Ǔ
O
P
D
I
_ V
ǒ Ǔ
D
R
L
Where:
P
V
= power dissipation for one amplifier
= split supply voltage
CC
I
V
R
= supply current for that particular amplifier
= output voltage of amplifier
= load resistance
CC
O
L
To find the total THS6002 power dissipation, we simply sum up all four amplifier power dissipation results.
Generally, the worst case power dissipation occurs when the output voltage is one-half the V voltage. One
CC
last note, which is often overlooked: the feedback resistor (R ) is also a load to the output of the amplifier and
F
should be taken into account for low value feedback resistors.
25
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
APPLICATION INFORMATION
device protection features
The THS6002 has two built-in protection features that protect the device against improper operation. The first
protection mechanism is output current limiting. Should the output become shorted to ground the output current
is automatically limited to the value given in the data sheet. While this protects the output against excessive
current, the device internal power dissipation increases due to the high current and large voltage drop across
the output transistors. Continuous output shorts are not recommended and could damage the device.
Additionally, connection of the amplifier output to one of the supply rails ( V ) can cause failure of the device
CC
and is not recommended.
The second built-in protection feature is thermal shutdown. Should the internal junction temperature rise above
approximately 180_C, the device automatically shuts down. Such a condition could exist with improper heat
sinking or if the output is shorted to ground. When the abnormal condition is fixed, the internal thermal shutdown
circuit automatically turns the device back on.
thermal information
The THS6002 is packaged in a thermally-enhanced DWP package, which is a member of the PowerPAD family
of packages. This package is constructed using a downset leadframe upon which the die is mounted
[see Figure 52(a) and Figure 52(b)]. This arrangement results in the lead frame being exposed as a thermal pad
on the underside of the package [see Figure 52(c)]. Because this thermal pad has direct thermal contact with
the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal
pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device. This
is discussed in more detail in the PCB design considerations section of this document.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 52. Views of Thermally Enhanced DWP Package
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
APPLICATION INFORMATION
recommended feedback and gain resistor values
As with all current feedback amplifiers, the bandwidth of the THS6002 is an inversely proportional function of
the value of the feedback resistor. This can be seen from Figures 17 and 18. For the driver, the recommended
resistors for the optimum frequency response for a 25-Ω load system are 680-Ω for a gain = 1 and 620-Ω for
a gain = 2 or −1. For the receivers, the recommended resistors for the optimum frequency response are
560 Ω for a gain = 1 and 390 Ω for a gain = 2 or −1. These should be used as a starting point and once optimum
values are found, 1% tolerance resistors should be used to maintain frequency response characteristics.
Because there is a finite amount of output resistance of the operational amplifier, load resistance can play a
major part in frequency response. This is especially true with the drivers, which tend to drive low-impedance
loads. This can be seen in Figure 7, Figure 19, and Figure 20. As the load resistance increases, the output
resistance of the amplifier becomes less dominant at high frequencies. To compensate for this, the feedback
resistor should change. For 100-Ω loads, it is recommended that the feedback resistor be changed to 820 Ω
for a gain of 1 and 560 Ω for a gain of 2 or −1. Although, for most applications, a feedback resistor value of
1 kΩ is recommended, which is a good compromise between bandwidth and phase margin that yields a very
stable amplifier.
Consistent with current feedback amplifiers, increasing the gain is best accomplished by changing the gain
resistor, not the feedback resistor. This is because the bandwidth of the amplifier is dominated by the feedback
resistor value and internal dominant-pole capacitor. The ability to control the amplifier gain independently of the
bandwidth constitutes a major advantage of current feedback amplifiers over conventional voltage feedback
amplifiers. Therefore, once a frequency response is found suitable to a particular application, adjust the value
of the gain resistor to increase or decrease the overall amplifier gain.
Finally, it is important to realize the effects of the feedback resistance on distortion. Increasing the resistance
decreases the loop gain and increases the distortion. It is also important to know that decreasing load
impedance increases total harmonic distortion (THD). Typically, the third order harmonic distortion increases
more than the second order harmonic distortion.
offset voltage
The output offset voltage, (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times
OO
IO
IB
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
R
F
G
I
IB−
−
+
V
OS
R
S
I
+
−
R
R
F
+ ǒ" V
Ǔ
V
" I
R
ǒ
1 )
Ǔ
" I
R
V
IO
OS
IO
IB)
S
IB*
F
IB+
G
Figure 53. Output Offset Voltage Model
27
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
APPLICATION INFORMATION
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true for the receiver amplifiers which are
generally used for amplifying small signals coming over a transmission line. The noise model for current
feedback amplifiers (CFB) is the same as voltage feedback amplifiers (VFB). The only difference between the
two is that the CFB amplifiers generally specify different current noise parameters for each input while VFB
amplifiers usually only specify one noise current parameter. The noise model is shown in Figure 54. This model
includes all of the noise sources as follows:
• e = amplifier internal voltage noise (nV/√Hz)
n
• IN+ = noninverting current noise (pA/√Hz)
• IN− = inverting current noise (pA/√Hz)
• e = thermal voltage noise associated with each resistor (e = 4 kTR )
Rx
Rx
x
e
Rs
e
n
R
Noiseless
S
+
_
e
ni
e
no
IN+
IN−
e
Rf
R
F
e
Rg
R
G
Figure 54. Noise Model
The total equivalent input noise density (e ) is calculated by using the following equation:
ni
2
) ǒIN ) RSǓ2 ) IN– ǒR
Ǔ
G Ǔ
) 4 kTR ) 4 kTǒR GǓ
2
Ǹ
ǒ Ǔ
ǒ
e
+
e
ø R
ø R
n
s
ni
F
F
Where:
−23
k = Boltzmann’s constant = 1.380658 × 10
T = temperature in degrees Kelvin (273 +°C)
R || R = parallel resistance of R and R
F
G
F
G
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (e ) by the
ni
overall amplifier gain (A ).
V
R
F
+ e ǒ1 ) Ǔ(Noninverting Case)
e
+ e
A
no
ni
R
G
ni
V
28
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
APPLICATION INFORMATION
noise calculations and noise figure (continued)
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing R ), the input noise is reduced considerably because of the parallel
G
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (R ) and the internal amplifier noise voltage (e ). Because noise is summed in a root-mean-squares
S
n
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
2
e
ȱ ȳ
ni
NF + 10log
ȧeRsȧ
Ȳ ȴ
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
2
2
ȱ
ȳ
ȣ
ȡ
Ȣ
) ǒIN ) R
Ǔ
S
ǒe Ǔ
ȧ
ȧ
n
ȧ
ȧ
Ȥ
ȧ
ȧ
NF + 10log 1 )
ȧ
ȧ
ȧ
ȧ
4 kTR
S
ȧ
ȧ
Ȳ
ȴ
The Figure 55 shows the noise figure graph for the THS6002.
NOISE FIGURE
vs
SOURCE RESISTANCE
20
T
A
= 25°C
18
16
14
12
10
8
6
4
2
0
10
100
1k
10k
R
− Source Resistance − Ω
s
Figure 55. Noise Figure vs. Source Resistance
29
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
APPLICATION INFORMATION
PCB design considerations
Proper PCB design techniques in two areas are important to assure proper operation of the THS6002. These
areas are high-speed layout techniques and thermal-management techniques. Because the THS6002 is a
high-speed part, the following guidelines are recommended.
D
Ground plane − It is essential that a ground plane be used on the board to provide all components with a
low inductive ground connection. Although a ground connection directly to a terminal of the THS6002 is not
necessarily required, it is recommended that the thermal pad of the package be tied to ground. This serves
two functions. It provides a low inductive ground to the device substrate to minimize internal crosstalk and
it provides the path for heat removal.
D
Input stray capacitance − To minimize potential problems with amplifier oscillation, the capacitance at the
inverting input of the amplifiers must be kept to a minimum. To do this, PCB trace runs to the inverting input
must be as short as possible, the ground plane must be removed under any etch runs connected to the
inverting input, and external components should be placed as close as possible to the inverting input. This
is especially true in the noninverting configuration. An example of this can be seen in Figure 56, which shows
what happens when 1.8 pF is added to the inverting input terminal in the noninverting configuration. The
bandwidth increases dramatically at the expense of peaking. This is because some of the error current is
flowing through the stray capacitor instead of the inverting node of the amplifier. Although, in the inverting
mode, stray capacitance at the inverting input has little effect. This is because the inverting node is at a
virtual ground and the voltage does not fluctuate nearly as much as in the noninverting configuration.
DRIVER
NORMALIZED FREQUENCY RESPONSE
vs
FREQUENCY
3
V
=
15 V
CC
V = 200 mV
2
I
R
R
= 25 Ω
= 1 kΩ
L
F
1
0
Gain = 1
C = 0 pF
I
(Stray C Only)
−1
−2
C = 1.8 pF
I
1 kΩ
−3
−4
−5
C
in
in
V
out
−
V
+
R
25 Ω
=
L
50 Ω
−6
−7
100
1M
10M
f − Frequency − Hz
100M
500M
Figure 56. Driver Normalized Frequency Response vs. Frequency
30
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
APPLICATION INFORMATION
PCB design considerations (continued)
D
Proper power supply decoupling − Use a minimum of a 6.8-µF tantalum capacitor in parallel with a 0.1-µF
ceramic capacitor on each supply terminal. It may be possible to share the tantalum among several
amplifiers depending on the application, but a 0.1-µF ceramic capacitor should always be used on the
supply terminal of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible
to the supply terminal. As this distance increases, the inductance in the connecting etch makes the capacitor
less effective. The designer should strive for distances of less than 0.1 inches (2,54 mm) between the device
power terminal and the ceramic capacitors.
Because of its power dissipation, proper thermal management of the THS6002 is required. Although there are
many ways to properly heatsink this device, the following steps illustrate one recommended approach for a
multilayer PCB with an internal ground plane.
1. Prepare the PCB with a top side etch pattern as shown in Figure 57. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils (0,33 mm) in diameter. They
are kept small so that solder wicking through the holes is not a problem during reflow.
3. Place four more holes under the package, but outside the thermal pad area. These holes are 25 mils
(0,635 mm) in diameter. They may be larger because they are not in the area to be soldered so that wicking
is not a problem.
4. Connect all nine holes, the five within the thermal pad area and the four outside the pad area, to the internal
ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
However, in this application, low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS6002 package should make their connection to the internal ground plane with a
complete connection around the entire circumference of the plated through hole.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area with
its five holes. The four larger holes outside the thermal pad area, but still under the package, should be
covered with solder mask.
7. Apply solder paste to the exposed thermal pad area and all of the operational amplifier terminals.
8. With these preparatory steps in place, the THS6002 is simply placed in position and run through the solder
reflow operation as any standard surface mount component. This results in a part that is properly installed.
31
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APPLICATION INFORMATION
PCB design considerations (continued)
Additional 4 vias outside of thermal pad area
but under the package
Via diameter = 25 mils (0,635 mm))
Thermal pad area (150 mils x 170 mils)
(3,81 mm x 4,32 mm) with 5 vias
Via diameter = 13 mils(0,33 mm)
Figure 57. PowerPad PCB Etch and Via Pattern
The actual thermal performance achieved with the THS6002 in its PowerPAD package depends on the
application. In the previous example, if the size of the internal ground plane is approximately 3 inches × 3 inches
(76,2 mm x 76,2 mm), then the expected thermal coefficient, θ , is about 21.5_C/W. For a given θ , the
JA
JA
maximum power dissipation is shown in Figure 58 and is calculated by the following formula:
T
–T
MAX
A
P
+
ǒ Ǔ
D
q
JA
Where:
P
= Maximum power dissipation of THS6002 (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to case (0.37°C/W)
= Thermal coefficient from case to ambient
JC
CA
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package. This document can be
found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be
ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
32
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APPLICATION INFORMATION
PCB design considerations (continued)
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
9
8
7
6
T = 150°C
j
PCB Size = 3” x 3”
(76,2 mm x 76,2 mm)
No Air Flow
θ
JA
= 21.5°C/W
2 oz Trace and
Copper Pad
with Solder
5
4
3
2
θ
= 43.9°C/W
JA
2 oz Trace and Copper Pad
without Solder
1
0
−40 −20
0
20
40
60
80
100
T
A
− Free-Air Temperature − °C
Figure 58. Maximum Power Dissipation vs Free-Air Temperature
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
APPLICATION INFORMATION
ADSL
The THS6002 was primarily designed as a line driver and line receiver for ADSL (asymmetrical digital subscriber
line). The driver output stage has been sized to provide full ADSL power levels of 20 dBm onto the telephone
lines. Although actual driver output peak voltages and currents vary with each particular ADSL application, the
THS6002 is specified for a minimum full output current of 400 mA at its full output voltage of approximately 12
V. This performance meets the demanding needs of ADSL at the central office end of the telephone line. A typical
ADSL schematic is shown in Figure 59.
15 V
+
THS6002
Driver 1
0.1 µF
6.8 µF
12.5 Ω
+
_
V
I+
1:2
1 kΩ
To Telephone Line
100 Ω
1 kΩ
0.1 µF
6.8 µF
+
−15 V
15 V
1 kΩ
15 V
+
2 kΩ
1 kΩ
THS6002
Driver 2
0.1 µF
6.8 µF
0.1 µF
12.5 Ω
+
V
I−
−
+
_
V
O+
THS6002
Receiver 1
1 kΩ
0.1 µF
−15 V
1 kΩ
1 kΩ
6.8 µF
+
15 V
−15 V
2 kΩ
1 kΩ
0.1 µF
−
+
V
O−
THS6002
Receiver 2
0.01 µF
−15 V
Figure 59. THS6002 ADSL Application
34
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APPLICATION INFORMATION
ADSL (continued)
The ADSL transmit band consists of 255 separate carrier frequencies each with its own modulation and
amplitude level. With such an implementation, it is imperative that signals put onto the telephone line have as
low a distortion as possible. This is because any distortion either interferes directly with other ADSL carrier
frequencies or it creates intermodulation products that interfere with ADSL carrier frequencies.
The THS6002 has been specifically designed for ultra low distortion by careful circuit implementation and by
taking advantage of the superb characteristics of the complementary bipolar process. Driver single-ended
distortion measurements are shown in Figure 23. It is commonly known that in the differential driver
configuration, the second order harmonics tend to cancel out. Thus, the dominant total harmonic distortion
(THD) will be primarily due to the third order harmonics. For this test, the load was 25 Ω and the output signal
produced a 20 V
signal. Thus, the test was run at full signal and full load conditions. Because the feedback
O(PP)
resistor used for the test was 4 kΩ, the distortion numbers are actually in a worst-case scenario. Distortion
should be reduced as the feedback resistance drops. This is because the bandwidth of the amplifier increases
dramatically, which allows the amplifier to react faster to any nonlinearities in the closed-loop system.
Another significant point is the fact that distortion decreases as the impedance load increases. This is because
the output resistance of the amplifier becomes less significant as compared to the output load resistance.
35
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
APPLICATION INFORMATION
HDSL
Shown in Figure 60 is an example of the THS6002 being used for HDSL-2 applications. The receiver amplifiers
within the THS6002 have been configured as predrivers for the driver amplifiers. This dual composite amplifier
setup has the effect of raising the open loop gain for the combination of both amplifiers, thereby giving improved
distortion performance.
7.5 kΩ
1 kΩ
11 kΩ
12 V
12 V
6
7
−
4
5
9
30 Ω
Receiver 1
+
2
+
Output
27.4 V
THS6002
−
1:1.5
O(PP)
Driver 1
−12 V
−12 V
1 kΩ
135 Ω
511 Ω
1 kΩ
1 kΩ
12 V
Input
3 V
7.5 kΩ
(PP)
2
1
1 kΩ
11 kΩ
12 V
−
6
U2
+
THS4001
−12 V
12 V
15
14
−
17
12
30 Ω
Receiver 2
+
−
19
+
16
Driver 2
−12 V
−12 V
1 kΩ
511 Ω
Figure 60. HDSL-2 Line Driver
general configurations
A common error for the first-time CFB user is to create a unity gain buffer amplifier by shorting the output directly
to the inverting input. A CFB amplifier in this configuration is now commonly referred to as an oscillator. The
THS6002, like all CFB amplifiers, must have a feedback resistor for stable operation. Additionally, placing
capacitors directly from the output to the inverting input is not recommended. This is because, at high
frequencies, a capacitor has a very low impedance. This results in an unstable amplifier and should not be
considered when using a current-feedback amplifier. Because of this, integrators and simple low-pass filters,
which are easily implemented on a VFB amplifier, have to be designed slightly differently. If filtering is required,
simply place an RC-filter at the noninverting terminal of the operational-amplifier (see Figure 61).
36
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
APPLICATION INFORMATION
general configurations (continued)
R
R
F
G
V
R
O
F
1
ǒ
Ǔ
+
ǒ
1 )
Ǔ
V
R
1 ) sR1C1
I
G
−
V
O
1
+
f
+
V
I
–3dB
2pR1C1
R1
C1
Figure 61. Single-Pole Low-Pass Filter
If a multiple pole filter is required, the use of a Sallen-Key filter can work very well with CFB amplifiers. This is
because the filtering elements are not in the negative feedback loop and stability is not compromised. Because
of their high slew-rates and high bandwidths, CFB amplifiers can create very accurate signals and help minimize
distortion. An example is shown in Figure 62.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
F
1
R
=
G
R
F
2 −
)
R
(
Q
G
Figure 62. 2-Pole Low-Pass Sallen-Key Filter
There are two simple ways to create an integrator with a CFB amplifier. The first one shown in Figure 63 adds
a resistor in series with the capacitor. This is acceptable because at high frequencies, the resistor is dominant
and the feedback impedance never drops below the resistor value. The second one shown in Figure 64 uses
positive feedback to create the integration. Caution is advised because oscillations can occur because of the
positive feedback.
C1
R
F
R
G
1
S )
ȡ
ȣ
−
+
V
I
R C1ȧ
V
R
F
O
F
V
O
+
ǒ Ǔ
ȧ
V
R
S
I
G
THS6002
Ȣ
Ȥ
Figure 63. Inverting CFB Integrator
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SLOS202E− JANUARY 1998− REVISED MARCH 2007
APPLICATION INFORMATION
general configurations (continued)
R
R
F
G
For Stable Operation:
R
R
R2
F
≥
−
+
R1 || R
G
A
THS6002
V
O
R
R
F
1 +
V
O
≅ V
G
I
R1
R2
)
(
sR1C1
V
I
C1
R
A
Figure 64. Non-Inverting CFB Integrator
Another good use for the THS6002 driver amplifiers are as very good video distribution amplifiers. One
characteristic of distribution amplifiers is the fact that the differential phase (DP) and the differential gain (DG)
are compromised as the number of lines increases and the closed-loop gain increases. Be sure to use
termination resistors throughout the distribution system to minimize reflections and capacitive loading.
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
THS6002CDWP
ACTIVE
SO
Power
PAD
DWP
20
20
20
20
20
20
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
THS6002CDWPG4
THS6002IDWP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
Power
PAD
DWP
DWP
DWP
DWP
DWP
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SO
Power
PAD
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
THS6002IDWPG4
THS6002IDWPR
THS6002IDWPRG4
SO
Power
PAD
25 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SO
Power
PAD
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
SO
Power
PAD
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS6002IDWPR
SO
Power
PAD
DWP
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO PowerPAD DWP 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
THS6002IDWPR
2000
Pack Materials-Page 2
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