THVD1451DRBR [TI]
具有 ±18kV IEC ESD 保护功能的 3.3V 至 5V RS-485 收发器 | DRB | 8 | -40 to 125;
| 型号： | THVD1451DRBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 ±18kV IEC ESD 保护功能的 3.3V 至 5V RS-485 收发器 | DRB | 8 | -40 to 125 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总49页 (文件大小：1944K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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THVD1410
THVD1450, THVD1451, THVD1452
ZHCSI82E –MAY 2018–REVISED MAY 2019
具有 ±18kV IEC ESD 保护功能的 THVD14xx 3.3V 至 5V RS-485 收发器
1 特性
其中的每个型号均是通过 3V 至 5.5V 的单电源供电运
行。该系列中的器件具有扩展共模电压范围，因此这些
器件适用于长电缆上的 应用 长线缆。
1
•
•
•
满足或超过 TIA/EIA-485A 标准的要求
3V 至 5.5V 电源电压
差分输出超过 2.1V，实现 PROFIBUS 与 5V 电源
兼容
THVD14xx 系列器件可提供小型 VSON 和 VSSOP 封
装，适用于空间受限的 应用。这些器件在自然通风环
境下的额定温度范围为 –40°C 至 125°C。
•
总线 I/O ESD 保护
–
–
–
–
±30kV HBM
器件信息(1)
±18kV IEC 61000-4-2 接触放电
±25kV IEC 61000-4-2 气隙放电
±4kV IEC 61000-4-4 快速瞬变脉冲
器件型号
THVD1410
封装
VSSOP (8)
封装尺寸（标称值）
3.00mm × 3.00mm
4.90mm × 3.91mm
3.00mm × 3.00mm
3.00mm × 3.00mm
4.90mm × 3.91mm
3.00mm × 3.00mm
4.90mm × 3.91mm
3.00mm × 3.00mm
8.65mm × 3.91mm
SOIC (8)
•
扩展级运行共模
范围：±15V
VSON (8)
VSSOP (8)
SOIC (8)
THVD1450
•
•
•
低 EMI 500kbps 和 50Mbps 数据速率
用于噪声抑制的大接收器滞后
低功耗
VSON (8)
SOIC (8)
THVD1451
THVD1452
–
–
待机电源电流：< 1µA
VSSOP (10)
SOIC (14)
运行期间的电流：< 3mA
•
扩展环境温度
范围：–40°C 至 125°C
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
•
•
•
•
适用于热插拔功能的无干扰加电/断电
开路、短路和空闲总线失效防护
THVD1410 和 THVD1450 简化原理图
1/8 单位负载（多达 256 个总线节点）
1
R
小尺寸 VSON 和 VSSOP 封装（可节省布板空间）
或 SOIC 封装（可实现快插兼容性）
2
7
6
RE
B
A
3
4
DE
D
2 应用
•
•
•
•
•
•
•
•
电机驱动器
THVD1451 简化原理图
工厂自动化和控制
电网基础设施
楼宇自动化
HVAC 系统
视频监控
8
A
B
2
R
7
6
5
Z
Y
3
D
过程分析
无线基础设施
THVD1452 简化原理图
(9)12
A
B
2(1)
3(2)
3 说明
R
(8)11
RE
THVD14xx 是一系列抗噪 RS-485/RS-422 收发器，专
用于在恶劣的工业环境中运行。这些器件的总线引脚可
耐受高级别的 IEC 电气快速瞬变 (EFT) 和 IEC 静电放
电 (ESD) 事件，从而无需使用其他系统级保护组件。
4(3)
5(4)
DE
D
(7)10
Z
Y
( )9
6
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEY3
THVD1410
THVD1450, THVD1451, THVD1452
ZHCSI82E –MAY 2018–REVISED MAY 2019
www.ti.com.cn
目录
9.1 Overview ................................................................. 18
9.2 Functional Block Diagrams ..................................... 18
9.3 Feature Description................................................. 19
9.4 Device Functional Modes........................................ 19
10 Application and Implementation........................ 22
10.1 Application Information...................................... 22
10.2 Typical Application ............................................... 22
11 Power Supply Recommendations ..................... 28
12 Layout................................................................... 29
12.1 Layout Guidelines ................................................. 29
12.2 Layout Example .................................................... 29
13 器件和文档支持 ..................................................... 30
13.1 器件支持................................................................ 30
13.2 第三方产品免责声明.............................................. 30
13.3 相关链接................................................................ 30
13.4 接收文档更新通知 ................................................. 30
13.5 社区资源................................................................ 30
13.6 商标....................................................................... 30
13.7 静电放电警告......................................................... 30
13.8 Glossary................................................................ 30
14 机械、封装和可订购信息....................................... 30
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 4
Pin Configuration and Functions......................... 5
Specifications......................................................... 8
7.1 Absolute Maximum Ratings ...................................... 8
7.2 ESD Ratings.............................................................. 8
7.3 ESD Ratings [IEC] .................................................... 8
7.4 Recommended Operating Conditions....................... 9
7.5 Thermal Information.................................................. 9
7.6 Power Dissipation ..................................................... 9
7.7 Electrical Characteristics......................................... 10
7.8 Switching Characteristics........................................ 11
7.9 Typical Characteristics: All Devices........................ 12
7.10 Typical Characteristics: THD1450, THVD1451 and
THVD1452 ............................................................... 14
7.11 Typical Characteristics: THVD1410 ...................... 15
Parameter Measurement Information ................ 16
Detailed Description ............................................ 18
8
9
4 修订历史记录
Changes from Revision D (March 2019) to Revision E
Page
•
将 THVD1451 从产品预览 更改为生产 数据........................................................................................................................... 1
Changes from Revision C (February 2019) to Revision D
Page
•
将 THVD1410 从产品预览 更改为生产数据............................................................................................................................ 1
Changes from Revision B (December 2018) to Revision C
Page
•
将 THVD1452 从产品预览 更改为生产 数据........................................................................................................................... 1
Changes from Revision A (May 2018) to Revision B
Page
•
•
•
•
•
•
•
•
•
•
•
•
添加特性：“差分输出超过 2.1 V...” ......................................................................................................................................... 1
更改特性：将“±18kV IEC 61000-4-2 气隙放电”更改为：“±25kV IEC 61000-4-2 气隙放电”................................................... 1
添加 THVD1451 的 SOIC (8) 封装 ......................................................................................................................................... 1
Added Thermal Pad to the THVD1450 DRB package ........................................................................................................... 5
Added Thermal Pad to the THVD1451 DRB package ........................................................................................................... 6
Changed all pins HBM ESD rating from 4 kV to 8 kV ............................................................................................................ 8
Changed IEC ESD air-gap discharge rating from 18 kV to 25 kV.......................................................................................... 8
Changed THVD1410 power dissipation numbers .................................................................................................................. 9
Changed THVD1410 driver tr, tf TYP from 400 ns to 460 ns and MAX from 600 ns to 680 ns ........................................... 11
Changed THVD1410 receiver tr, tf TYP from 13 ns to 10 ns................................................................................................ 11
Changed THVD1410 receiver tPHL, tPLH TYP from 60 ns to 35 ns....................................................................................... 11
Added Typical Characteristics, THD1450D.......................................................................................................................... 14
2
版权 © 2018–2019, Texas Instruments Incorporated
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com.cn
ZHCSI82E –MAY 2018–REVISED MAY 2019
•
•
•
•
Added condition to 图 8 to 图 3 ............................................................................................................................................ 14
Added Typical Characteristics, THD1410............................................................................................................................. 15
Changed A to A/Y and B to B/Z in 图 20 to 图 24................................................................................................................ 16
Added 3rd paragraph to the Overview section..................................................................................................................... 18
Changes from Original (November 2017) to Revision A
Page
•
将文档状态从预告信息 更改为生产数据.................................................................................................................................. 1
Copyright © 2018–2019, Texas Instruments Incorporated
3
THVD1410
THVD1450, THVD1451, THVD1452
ZHCSI82E –MAY 2018–REVISED MAY 2019
www.ti.com.cn
5 Device Comparison Table
PART NUMBER
THVD1410
THVD1450
THVD1451
THVD1452
DUPLEX
ENABLES
DE, RE
DE, RE
None
SIGNALING RATE
NODES
Half
Half
Full
Full
up to 500 kbps
256
up to 50 Mbps
DE, RE
4
Copyright © 2018–2019, Texas Instruments Incorporated
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com.cn
ZHCSI82E –MAY 2018–REVISED MAY 2019
6 Pin Configuration and Functions
THVD1410, THVD1450 Devices
8-Pin D Package (SOIC)
Top View
THVD1410, THVD1450 Devices
8-Pin DGK Package (VSSOP)
Top View
R
RE
DE
D
1
2
3
4
8
7
6
5
VCC
B
R
RE
DE
D
1
2
3
4
8
7
6
5
VCC
B
A
A
GND
GND
Not to scale
Not to scale
THVD1450 Device
8-Pin DRB Package (VSON)
Top View
R
RE
DE
D
1
2
3
4
8
7
6
5
VCC
B
Thermal
Pad
A
GND
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
A
D
6
7
4
3
5
1
8
2
DGK
DRB
6
7
4
3
5
1
8
2
6
7
4
3
5
1
8
2
Bus input/output
Bus input/output
Digital input
Digital input
Ground
Bus I/O port, A (complementary to B)
Bus I/O port, B (complementary to A)
Driver data input
B
D
DE
GND
R
Driver enable, active high (2-MΩ internal pull-down)
Device ground
Digital output
Power
Receive data output
VCC
RE
3.3-V to 5-V supply
Digital input
Receiver enable, active low (2-MΩ internal pull-up)
Thermal
Pad
No electrical connection. Should be connected to GND for optimal
thermal performance.
—
—
I/O
Copyright © 2018–2019, Texas Instruments Incorporated
5
THVD1410
THVD1450, THVD1451, THVD1452
ZHCSI82E –MAY 2018–REVISED MAY 2019
www.ti.com.cn
THVD1451 Device
8-Pin D Package (SOIC)
Top View
THVD1451 Device
8-Pin DRB Package (VSON)
Top View
VCC
R
1
2
3
4
8
7
6
5
A
B
Z
Y
VCC
R
1
2
3
4
8
7
6
5
A
B
Z
Y
D
Thermal
Pad
GND
D
GND
Not to scale
Not to scale
Pin Functions
PIN
I/O
Description
NAME
D
DRB
A
8
7
3
4
8
7
3
4
Bus input Bus input, A (complementary to B)
Bus input Bus input, B (complementary to A)
Digital input Driver data input
B
D
GND
Ground
Device ground
Digital
output
R
2
2
Receive data output
VCC
Y
1
5
6
1
5
6
Power
3.3-V to 5-V supply
Bus output Digital bus output, Y (Complementary to Z)
Bus output Digital bus output, Z (Complementary to Y)
Z
Thermal
Pad
No electrical connection. Should be connected to GND for optimal thermal
performance.
—
I/O
6
Copyright © 2018–2019, Texas Instruments Incorporated
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com.cn
ZHCSI82E –MAY 2018–REVISED MAY 2019
THVD1452 Device
14-Pin D Package (SOIC)
Top View
THVD1452 Device
10-Pin DGS Package (VSSOP)
Top View
NC
R
1
2
3
4
5
6
7
14
VCC
VCC
A
R
RE
1
2
3
4
5
10
9
VCC
A
13
12
11
10
9
RE
DE
8
B
DE
B
D
7
Z
D
Z
GND
6
Y
GND
GND
Y
8
NC
Not to scale
Not to scale
NC – No internal connection
Pin Functions
PIN
I/O
DESCRIPTION
NAME
A
D
DGS
9
12
Bus input
Bus input
Digital input
Digital input
Ground
Bus input, A (complementary to B)
Bus input, B (complementary to A)
Driver data input
B
11
8
D
5
4
DE
GND
NC
R
4
3
Driver enable, active high (2-MΩ internal pull-down)
Device ground
6, 7(1)
5
1, 8
—
1
—
Internally not connected
2
Digital output
Power
Receive data output
VCC
Y
13, 14(1)
10
6
3.3-V to 5-V supply
9
10
3
Bus output
Bus output
Digital input
Digital bus output, Y (Complementary to Z)
Digital bus output, Z (Complementary to Y)
Receiver enable, active low (2-MΩ internal pull-up)
Z
7
RE
2
(1) These pins are internally connected
Copyright © 2018–2019, Texas Instruments Incorporated
7
THVD1410
THVD1450, THVD1451, THVD1452
ZHCSI82E –MAY 2018–REVISED MAY 2019
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage
Bus voltage
VCC
-0.5
7
V
Range at any bus pin (A, B, Y, or Z) as differential
or common-mode with respect to GND
-18
-0.3
-24
-65
18
5.7
24
V
V
Input voltage
Range at any logic pin (D, DE, or RE)
Receiver output
current
IO
mA
℃
Storage temperature range
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±30
UNIT
kV
Bus pins and
GND
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
All other pins
±8
kV
V(ESD)
Electrostatic discharge
Charged device model (CDM), per
JEDEC JESD22-C101(2)
All pins
±1.5
kV
Machine model (MM), per JEDEC
JESD22-A115-A
All pins
±200
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 ESD Ratings [IEC]
VALUE
UNIT
Contact discharge, per IEC 61000-
4-2
Bus pins and
GND
±18
±25
±4
kV
V(ESD)
Electrostatic discharge
Electrical fast transient
Air-gap discharge, per IEC 61000-4- Bus pins and
2
kV
kV
GND
Bus pins and
GND
V(EFT)
Per IEC 61000-4-4
8
Copyright © 2018–2019, Texas Instruments Incorporated
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com.cn
ZHCSI82E –MAY 2018–REVISED MAY 2019
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
5.5
UNIT
V
VCC
VI
Supply voltage
Input voltage at any bus terminal(1)
-15
15
V
High-level input voltage (driver, driver
enable, and receiver enable inputs)
VIH
VIL
2
0
VCC
0.8
V
V
Low-level input voltage (driver, driver
enable, and receiver enable inputs)
VID
IO
Differential input voltage
Output current, driver
-15
-60
-8
15
60
8
V
mA
mA
Ω
IOR
RL
Output current, receiver
Differential load resistance
Signaling rate: THVD1410
54
1/tUI
500
50
kbps
Signaling rate: THVD1450, THVD1451,
THVD1452
1/tUI
Mbps
TA
TJ
Operating ambient temperature
Junction temperature
-40
-40
125
150
℃
℃
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
7.5 Thermal Information
THVD1410
THVD1450
THVD1451
THVD1410
THVD1450
THVD1450
THVD1451
THVD1452
THVD1452
THERMAL METRIC(1)
UNIT
D (SOIC)
8 PINS
D (SOIC)
14 PINS
DGK (VSSOP) DGS (VSSOP)
DRB (VSON)
8 PINS
8 PINS
10 PINS
Junction-to-ambient thermal
resistance
RθJA
114.3
56.7
57.7
12.8
57
86.4
43.7
42.5
10.2
42.2
N/A
155.2
155.6
48.6
49.1
21.1
0.8
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(to Junction-to-case (top) thermal
47.2
76.1
3.9
49.3
77.1
4.5
resistance
p)
Junction-to-board thermal
resistance
RθJB
Junction-to-top characterization
parameter
ΨJT
Junction-to-board
ΨJB
74.8
N/A
75.7
N/A
21.1
2.7
characterization parameter
RθJC(b Junction-to-case (bottom)
N/A
thermal resistance
ot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.6 Power Dissipation
PARAMETE
Description
TEST CONDITIONS
MIN
TYP
MAX
UNIT
R
Driver and receiver enabled, VCC = 5.5 Unterminated: RL = 300 Ω, CL = 50 pF
360
370
410
360
320
330
mW
mW
mW
mW
mW
mW
V, TA = 1250C, 50% duty cycle square
RS-422 load: RL = 100 Ω, CL = 50 pF
wave at 500kbps signaling rate,
RS-485 load: RL = 54 Ω, CL = 50 pF
THVD1410
PD
Driver and receiver enabled, VCC = 5.5 Unterminated: RL = 300 Ω, CL = 50 pF
V, TA = 1250C, 50% duty cycle square
RS-422 load: RL = 100 Ω, CL = 50 pF
wave at 50Mbps signaling rate,
RS-485 load: RL = 54 Ω, CL = 50 pF
THVD145x devices
Copyright © 2018–2019, Texas Instruments Incorporated
9
THVD1410
THVD1450, THVD1451, THVD1452
ZHCSI82E –MAY 2018–REVISED MAY 2019
www.ti.com.cn
7.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC
5 V.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
RL = 60 Ω, -15 V ≤ Vtest ≤ 15 V (See 图 20)(1)
1.5
2.1
3.5
V
V
RL = 60 Ω, -15 V ≤ Vtest ≤ 15 V, 4.5 V ≤ VCC
5.5 V, (See 图 20)
≤
Driver differential output voltage
magnitude
|VOD
|
RL = 100 Ω (See 图 21)
RL = 54 Ω (See 图 21)
2
4
V
V
1.5
3.5
Change in differential output
voltage
Δ|VOD
|
-200
1
200
3
mV
V
VOC
Common-mode output voltage
RL = 54 Ω (See 图 21)
VCC/2
Change in steady-state common-
mode output voltage
ΔVOC(SS)
-200
-250
200
250
mV
mA
IOS
Short-circuit output current
DE = VCC, -7 V ≤ VO ≤ 12 V
Receiver
VI = 12V
DE = 0 V, VCC = 0 V or 5.5 V
VI = -7V
50
-65
125
125
µA
µA
µA
µA
-100
II
Bus input current
VI = 15V
DE = 0 V, VCC = 0 V or 5.5 V
VI = -15V
60
-200
-130
Positive-going input threshold
voltage
VTH+
See(2)
-100
-20
mV
Negative-going input threshold
voltage
Over common-mode range of ± 15 V
VTH-
VHYS
VOH
-200
-130 See(2)
30
mV
mV
V
Input hysteresis
VCC
–
VCC
–
Output high voltage
IOH = -8 mA
0.4
0.2
VOL
Output low voltage
IOL = 8 mA
0.2
0.4
1
V
IOZR
Output high-impedance current
VO = 0 V or VCC, RE = VCC
-1
µA
Logic
IIN
Input current (D, DE, RE)
3 V ≤ VCC ≤ 5.5 V, 0 V ≤ VIN ≤ VCC
-6.2
6.2
µA
Device
RE = 0 V ,
Driver and receiver enabled
DE = VCC
No load
,
2.4
2
3
2.5
mA
mA
µA
RE = VCC
,
Driver enabled, receiver disabled DE = VCC
No load
,
ICC
Supply current (quiescent)
RE = 0 V,
Driver disabled, receiver enabled DE = 0 V,
No load
700
960
RE = VCC
DE = 0 V, D
= open, No
load
,
Driver and receiver disabled
0.1
1
µA
TSD
Thermal shutdown temperature
170
℃
(1) |VOD| ≥ 1.4 V when TA > 85 ℃, Vtest < -7 V and VCC < 3.135 V.
(2) Under any specific conditions, VTH+ is assured to be at least VHYS higher than VTH–
.
10
Copyright © 2018–2019, Texas Instruments Incorporated
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com.cn
ZHCSI82E –MAY 2018–REVISED MAY 2019
7.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC
=
5 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver: THVD1410
tr, tf
Differential output rise/fall time
Propagation delay
250
460
250
680
500
10
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF, See 图 22
Pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Disable time
80
100
4
200
600
11
RE = 0 V, See 图 23 and 图 24
RE = VCC, See 图 23 and 图 24
tPZH, tPZL
Enable time
Receiver: THVD1410
tr, tf
Output rise/fall time
10
35
20
110
7
ns
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
tPHZ, tPLZ
tPZH(1), tPZL(1),
tPZH(2)
tPZL(2)
Driver: THVD1450, THVD1451, THVD1452
Propagation delay
Pulse skew, |tPHL – tPLH
Disable time
CL = 15 pF, See 图 25
|
30
60
60
DE = VCC, See 图 26
DE = 0 V, See 图 27
140
,
,
Enable time
6
14
µs
tr, tf
Differential output rise/fall time
Propagation delay
1
3
3
6
20
3.5
25
50
10
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF, See 图 22
10
Pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Disable time
15
20
RE = 0 V, See 图 23 and 图 24
RE = VCC, See 图 23 and 图 24
tPZH, tPZL
Enable time
2.5
Receiver: THVD1450, THVD1451, THVD1452
tr, tf
Output rise/fall time
Propagation delay
Pulse skew, |tPHL – tPLH
Disable time
2
6
40
ns
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
tPHZ, tPLZ
tPZH(1), tPZL(1),
tPZH(2)
tPZL(2)
CL = 15 pF, See 图 25
25
|
3.5
28
14
50
DE = VCC, See 图 26
DE = 0V, See 图 27
110
,
,
Enable time
4
14
µs
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7.9 Typical Characteristics: All Devices
6
5
4
3
2
1
0
6
5
4
3
2
1
0
VOL
VOH
0
10 20 30 40 50 60 70 80 90 100 110
0
10 20 30 40 50 60 70 80 90 100 110
IO Driver Output Current (mA)
IO Driver Output Current (mA)
D001
D002
VCC = 5 V
DE = VCC
D = 0 V
VCC = 5 V
DE = VCC
D = 0 V
图 1. Driver Output Voltage vs Driver Output Current
图 2. Driver Differential Output voltage vs Driver Output
Current
6
5
4
3
2
1
0
6
3.2
VOL
VOH
2.8
2.4
2
5
4
3
2
1.6
1.2
0.8
0.4
0
VTH (-7 V)
VTH (0 V)
VTH (12 V)
1
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
IO Driver Output Current (mA)
-170 -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 -50
VID Differential Input Voltage (mV)
D007
D101
VCC = 5 V
TA = 25°C
VCC = 3.3 V
DE = VCC
D = 0 V
图 3. Receiver Output vs Input
图 4. Driver Output Voltage vs Driver Output Current
3.4
3.2
3
3.5
3
VTH (12V)
VTH (0V)
VTH (-7V)
2.8
2.6
2.4
2.2
2
2.5
2
1.5
1
1.8
1.6
1.4
1.2
0.5
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
IO Driver Output Current (mA)
-180
-160
-140
-120
-100
-80
-60
-40
VID Differential Input Voltage (mV)
D102
D106
VCC = 3.3 V
DE = VCC
D = 0 V
VCC = 3.3 V
TA = 25°C
图 5. Driver Differential Output Voltage vs Driver Output
图 6. Receiver Output vs Input
Current
12
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Typical Characteristics: All Devices (接下页)
80
70
60
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VCC Supply Voltage (V)
D003
TA = 25°C
DE = VCC
D = VCC
RL = 54 Ω
图 7. Driver Output Current vs Supply Voltage
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7.10 Typical Characteristics: THD1450, THVD1451 and THVD1452
7
6
5
4
3
2
1
0
16
14
12
10
8
6
4
2
0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
D004
D005
VCC = 5 V
VCC = 5 V
图 8. Driver Rise or Fall Time vs Temperature
图 9. Driver Propagation Delay vs Temperature
4
3.8
3.6
3.4
3.2
3
120
100
80
60
40
20
2.8
-40
0
0
-20
0
20
40
60
80
100 120 140
5
10
15
20
25
30
35
40
45
50
Temperature (0C)
SIgnaling Rate (Mbps)
D103
D006
VCC = 3.3 V
RL = 54 Ω
VCC = 5 V
TA = 25°C
图 11. Driver Rise or Fall Time vs Temperature
图 10. Supply Current vs Signal Rate
17
16.5
16
85
82.5
80
77.5
75
15.5
15
72.5
70
14.5
14
67.5
65
13.5
13
62.5
60
12.5
-40
57.5
-20
0
20
40
60
80
100 120 140
0
5
10
15
20
25
30
35
40
45
50
Temperature (0C)
SIgnaling Rate (Mbps)
D104
D105
VCC = 3.3 V
RL = 54 Ω
VCC = 3.3 V
TA = 25°C
图 12. Driver Propagation Delay vs Temperature
图 13. Supply Current vs Signal Rate
14
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7.11 Typical Characteristics: THVD1410
600
580
560
540
520
500
480
460
440
420
400
276
273
270
267
264
261
258
255
252
249
246
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (0C)
Temperature (0C)
D107
D108
VCC = 5 V
VCC = 5 V
图 14. Driver Rise or Fall Time vs Temperature
图 15. Driver Propagation Delay vs Temperature
105
550
525
500
475
450
425
400
375
350
325
300
100
95
90
85
80
75
70
50
100 150 200 250 300 350 400 450 500
Signaling Rate (kbps)
-40
-20
0
20
40
60
80
100 120 140
Temperature (0C)
D109
D110
RL = 54 Ω
VCC = 5 V
TA = 25°C
VCC = 3.3 V
图 16. Supply Current vs Signal Rate
图 17. Driver Rise or Fall Time vs Temperature
345
340
335
330
325
320
315
310
305
300
295
290
58
56
54
52
50
48
46
44
-40
-20
0
20
40
60
80
100 120 140
50
100 150 200 250 300 350 400 450 500
Signaling Rate (kbps)
Temperature (0C)
D111
D112
VCC = 3.3 V
RL = 54 Ω
VCC = 3.3 V
TA = 25°C
图 18. Driver Propagation Delay vs Temperature
图 19. Supply Current vs Signal Rate
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8 Parameter Measurement Information
Vcc
375 Ω
DE
A/Y
D
Vtest
R
VOD
0V or Vcc
L
B/Z
375 Ω
图 20. Measurement of Driver Differential Output Voltage With Common-Mode Load
A/Y
V
A
RL/2
A/Y
B/Z
B/Z
D
V
B
V
0V or V
cc
OD
RL/2
VOC(PP)
ûVOC(SS)
CL
VOC
V
OC
图 21. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
Vcc
Vcc
50
%
V
I
DE
0 V
A/Y
B/Z
tPLH
tPHL
RL=
D
CL= 50 pF
~
2 V
~
V
54 Ω
OD
Input
90
%
%
50 Ω
V
I
50
10
Generator
V
OD
%
~
œ 2 V
~
tr
tf
图 22. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A/Y
V
cc
S 1
V
D
O
V
50 %
I
0 V
B/Z
DE
tPZH
RL
=
CL
50
=
110 Ω
V
pF
OH
Input
Generator
90
%
50 Ω
VI
50
%
V
O
~
~ 0V
tPHZ
图 23. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load
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Parameter Measurement Information (接下页)
Vcc
Vcc
0 V
RL= 110 Ω
A/Y
B/Z
50 %
VI
S1
VO
D
tPZL
tPLZ
Vcc
≈
VO
DE
CL=
50 pF
Input
50%
50Ω
VI
10%
Generator
VOL
图 24. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
3 V
50%
V
I
A
B
0 V
R
VO
t
tPHL
Input
PLH
50 Ω
V
1.5V
0 V
VOH
Generator
I
90%
50%
10%
CL=15 pF
RE
V
OD
V
tr
OL
t
f
图 25. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
V
cc
Vcc
DE
Vcc
V
50%
I
0V
V
A
B
tPZH(1)
1 kΩ
tPHZ
D
V
O
R
D at Vcc
S1 to GND
0V or Vcc
S1
OH
90%
V
50%
O
CL=15 pF
≈ 0V
RE
tPZL(1)
tPLZ
Input
Generator
D at 0V
S1 to Vcc
V
CC
50 Ω
V
I
V
50%
O
10%
V
OL
图 26. Measurement of Receiver Enable/Disable Times With Driver Enabled
Vcc
0V
Vcc
VI
50%
A
B
1 kΩ
tPZH(2)
V or 1.5V
VO
R
S1
VOH
A at 1.5V
B at 0V
S1 to GND
1.5 V or 0V
50%
VO
CL=15 pF
RE
≈ 0V
tPZL(2)
Input
Generator
A at 0V
B at 1.5V
S1 to VCC
VCC
50 Ω
VI
VO
50%
VOL
图 27. Measurement of Receiver Enable Times With Driver Disabled
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9 Detailed Description
9.1 Overview
THVD1410 and THVD1450 are low-power, half duplex RS-485 transceivers available in two speed grades
suitable for data transmission up to 500 kbps and 50 Mbps respectively.
THVD1451 is fully enabled with no external enabling pins. THVD1452 has active-high driver enable and active-
low receiver enable. A standby current of less than 1 µA can be achieved by disabling both driver and receiver.
THVD14xx family of devices have a higher typical differential output voltage (VOD) than traditional transceivers for
better noise immunity. A minimum differential output voltage of 2.1 V is specified with VCC voltage of 5 V ±10% to
meet the requirements of PROFIBUS applications.
9.2 Functional Block Diagrams
VCC
R
RE
A
B
DE
D
GND
图 28. THVD1410 and THVD1450
VCC
A
R
D
R
B
VCC
Z
Y
D
GND
图 29. THVD1451
VCC
A
R
R
B
RE
DE
D
Z
Y
D
GND
图 30. THVD1452
18
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9.3 Feature Description
Internal ESD protection circuits protect the transceiver against electrostatic discharges (ESD) according to IEC
61000-4-2 of up to ±18 kV and against electrical fast transients (EFT) according to IEC 61000-4-4 of up to ±4 kV.
With careful system design, one could achieve ±4 kV EFT Criterion A (no data loss when transient noise is
present).
The THVD14xx device family provides internal biasing of the receiver input thresholds in combination with large
input-threshold hysteresis. The receiver output remains logic high under a bus-idle or bus-short conditions
without the need for external failsafe biasing resistors. Device operation is specified over a wide ambient
temperature range from –40°C to 125°C.
9.4 Device Functional Modes
9.4.1 Device Functional Modes for THVD1410 and THVD1450
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse: B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
表 1. Driver Function Table for THVD1410 and THVD1450
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
A
H
L
B
L
H
H
Actively drive bus high
Actively drive bus low
L
X
H
L
H
Z
Z
L
Z
Z
H
Driver disabled
X
OPEN
H
Driver disabled by default
Actively drive bus high by default
OPEN
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
表 2. Receiver Function Table for THVD1410 and THVD1450
DIFFERENTIAL INPUT
VID = VA – VB
VTH+ < VID
ENABLE
OUTPUT
FUNCTION
RE
R
H
?
L
Receive valid bus high
Indeterminate bus state
Receive valid bus low
Receiver disabled
VTH- < VID < VTH+
VID < VTH-
L
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
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9.4.2 Device Functional Modes for THVD1451
For this device, the driver and receiver are fully enabled, thus the differential outputs Y and Z follow the logic
states at data input D at all times. A logic high at D causes Y to turn high and Z to turn low. In this case, the
differential output voltage defined as VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns
high, Y becomes low, and VOD is negative. The D pin has an internal pull-up resistor to VCC, thus, when left
open while the driver is enabled, output Y turns high and Z turns low.
表 3. Driver Function Table for THVD1451
INPUT
OUTPUTS
FUNCTIONS
D
H
Y
H
L
Z
L
Actively drive bus high
Actively drive bus low
L
H
L
OPEN
H
Actively drive bus High by default
When the differential input voltage defined as VID = VA – VB is higher than the positive input threshold, VTH+, the
receiver output, R, turns high. When VID is less than the negative input threshold, VTH–, the receiver output, R,
turns low. If VID is between VTH+ and VTH– the output is indeterminate. Internal biasing of the receiver inputs
causes the output to go failsafe-high when the transceiver is disconnected from the bus (open-circuit), the bus
lines are shorted to one another (short-circuit), or the bus is not actively driven (idle bus).
表 4. Receiver Function Table for THVD1451
DIFFERENTIAL INPUT
VID = VA – VB
OUTPUT
FUNCTION
R
H
?
VTH+ < VID
Receive valid bus high
Indeterminate bus state
Receive valid bus low
Fail-safe high output
Fail-safe high output
Fail-safe high output
VTH- < VID < VTH+
VID < VTH-
L
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
H
H
H
20
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9.4.3 Device Functional Modes for THVD1452
When the driver enable pin, DE, is logic high, the differential outputs Y and Z follow the logic states at data input
D. A logic high at D causes Y to turn high and Z to turn low. In this case the differential output voltage defined as
VOD = VY – VZ is positive. When D is low, the output states reverse: Z turns high, Y becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
Y turns high and Z turns low.
表 5. Driver Function Table for THVD1452
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
Y
H
L
Z
L
H
H
Actively drive bus high
Actively drive bus low
L
X
H
L
H
Z
Z
L
Z
Z
H
Driver disabled
X
OPEN
H
Driver disabled by default
Actively drive bus high by default
OPEN
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
表 6. Receiver Function Table for THVD1452
DIFFERENTIAL INPUT
VID = VA – VB
VTH+ < VID
ENABLE
OUTPUT
FUNCTION
RE
R
H
?
L
Receive valid bus high
Indeterminate bus state
Receive valid bus low
Receiver disabled
VTH- < VID < VTH+
VID < VTH-
L
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The THVD14xx family consists of half-duplex and full-duplex RS-485 transceivers commonly used for
asynchronous data transmissions. For half-duplex devices, the driver and receiver enable pins allow for the
configuration of different operating modes. Full-duplex implementation requires two signal pairs (four wires), and
allows each node to transmit data on one pair while simultaneously receiving data on the other pair.
10.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, generally allows for higher data rates
over longer cable length.
R
R
R
R
A
B
A
B
RE
RE
R
R
T
T
DE
D
DE
D
D
D
A
B
A
B
R
R
R
R
D
D
D
D
RE DE
RE DE
图 31. Typical RS-485 Network With Half-Duplex Transceivers
Y
Z
A
B
R
D
R
R
R
R
R
R
T
T
T
T
DE
RE
Master
R
Slave
D
RE
D
DE
D
B
A
Z
Y
A
B
Z
Y
R
Slave
D
R RE DE D
图 32. Typical RS-485 Network With Full-Duplex Transceivers
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Typical Application (接下页)
10.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
short the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
10000
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100 k
1M
10M
100 M
Data Rate (bps)
图 33. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (that is, 50 Mbps for the THVD1450, THVD1451 and THVD1452) in cases
where the interconnect is short enough (or has suitably low attenuation at signal frequencies) to not degrade the
data.
10.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections of varying phase as the length of the stub increases. As a general guideline, the electrical length, or
round-trip delay, of a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum
physical stub length as shown in 公式 1.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
10.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to drive 32 unit loads (UL), where 1 unit load
represents a load impedance of approximately 12 kΩ. Because the THVD14xx family consists of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
版权 © 2018–2019, Texas Instruments Incorporated
23
THVD1410
THVD1450, THVD1451, THVD1452
ZHCSI82E –MAY 2018–REVISED MAY 2019
www.ti.com.cn
Typical Application (接下页)
10.2.1.4 Receiver Failsafe
The differential receivers of the THVD14xx family are failsafe to invalid bus states caused by the following:
•
•
•
Open bus conditions, such as a disconnected connector
Shorted bus conditions, such as cable damage shorting the twisted-pair together
Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a high when the differential input VID is more positive than 200 mV, and must output a Low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VTH+, VTH–, and VHYS (the separation between VTH+ and VTH–). As shown in the table, differential signals more
negative than –200 mV will always cause a low receiver output, and differential signals more positive than 200
mV will always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VTH+ threshold, and the receiver output will
be High. Only when the differential input is more than VHYS below VTH+ will the receiver output transition to a Low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value, VHYS, as well as the value of VTH+
.
24
版权 © 2018–2019, Texas Instruments Incorporated
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com.cn
ZHCSI82E –MAY 2018–REVISED MAY 2019
Typical Application (接下页)
10.2.1.5 Transient Protection
The bus pins of the THVD14xx transceiver family include on-chip ESD protection against ±30-kV HBM and ±18-
kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more
severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge resistance,
R(D), of the IEC model produce significantly higher discharge currents than the HBM model. As stated in the IEC
61000-4-2 standard, contact discharge is the preferred transient protection test method.
R(C)
R(D)
40
35
30
25
20
15
10
5
50 M
(1 M)
330 Ω
10-kV IEC
(1.5 kΩ)
Device
Under
Test
High-Voltage
Pulse
Generator
150 pF
(100 pF)
C(S)
10-kV HBM
0
0
50
100
150
200
250
300
Time (ns)
图 34. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables. Designers may choose to
implement protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
图 35 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
The right hand diagram shows the pulse power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
22
20
18
16
14
12
10
8
0.5-kV Surge
4-kV EFT
6
4
2
0.5-kV Surge
10-kV ESD
0
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
Time (µs)
Time (µs)
图 35. Power Comparison of ESD, EFT, and Surge Transients
版权 © 2018–2019, Texas Instruments Incorporated
25
THVD1410
THVD1450, THVD1451, THVD1452
ZHCSI82E –MAY 2018–REVISED MAY 2019
www.ti.com.cn
Typical Application (接下页)
If the surge transients, high-energy content is characterized by long pulse duration and slow decaying pulse
power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver is
converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver. 图
36 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT pulse
train that is commonly applied during compliance testing.
1000
100
Surge
10
1
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
图 36. Comparison of Transient Energies
26
版权 © 2018–2019, Texas Instruments Incorporated
THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com.cn
ZHCSI82E –MAY 2018–REVISED MAY 2019
Typical Application (接下页)
10.2.2 Detailed Design Procedure
图 37 and 图 38 suggest a protection circuit against 1 kV surge (IEC 61000-4-5) transients. 表 7 shows the
associated bill of materials.
5V
100nF
100nF
10k
V
CC
R1
R
RxD
TVS
RE
DE
D
A
B
MCU/
UART
DIR
TxD
R2
10k
GND
图 37. Transient Protection Against Surge Transients for Half-Duplex Devices
5V
100nF
R1
10k
V
CC
TVS
A
B
R
RxD
DIR
RE
R2
R1
MCU/
UART
DE
D
DIR
TxD
TVS
Z
Y
10k
GND
R2
图 38. Transient Protection Against Surge Transients for Full-Duplex Devices
表 7. Bill of Materials
DEVICE
XCVR
R1
FUNCTION
ORDER NUMBER
MANUFACTURER
RS-485 transceiver
THVD14xx
TI
10-Ω, pulse-proof thick-film resistor
CRCW0603010RJNEAHP
CDSOT23-SM712
Vishay
Bourns
R2
TVS
Bidirectional 400-W transient suppressor
版权 © 2018–2019, Texas Instruments Incorporated
27
THVD1410
THVD1450, THVD1451, THVD1452
ZHCSI82E –MAY 2018–REVISED MAY 2019
www.ti.com.cn
10.2.3 Application Curves
50 Mbps
VCC = 5 V
图 39. THVD1450 Waveforms with 54-Ω Termination
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100
nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
28
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THVD1410
THVD1450, THVD1451, THVD1452
www.ti.com.cn
ZHCSI82E –MAY 2018–REVISED MAY 2019
12 Layout
12.1 Layout Guidelines
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against surge transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from penetrating your
board.
2. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF decoupling capacitors as close as possible to the VCC pins of transceiver, UART
and/or controller ICs on the board.
5. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize effective via inductance.
6. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in theses lines
during transient events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
12.2 Layout Example
5
Via to ground
C
Via to VCC
4
R
6
6
R
R
1
R
MCU
5
TVS
THVD14x0
5
图 40. Half-Duplex Layout Example
版权 © 2018–2019, Texas Instruments Incorporated
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THVD1410
THVD1450, THVD1451, THVD1452
ZHCSI82E –MAY 2018–REVISED MAY 2019
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13 器件和文档支持
13.1 器件支持
13.2 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 8. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
请单击此处
THVD1410
THVD1450
THVD1451
THVD1452
13.4 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。.
13.5 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.6 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.8 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
30
版权 © 2018–2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THVD1410D
THVD1410DGK
THVD1410DGKR
THVD1410DR
THVD1450D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
VSSOP
VSSOP
SOIC
D
DGK
DGK
D
8
8
75
80
RoHS & Green
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
VD1410
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAUAG
NIPDAUAG | SN
NIPDAU
1410
8
2500 RoHS & Green
2500 RoHS & Green
1410
8
VD1410
VD1450
1450
SOIC
D
8
75
80
RoHS & Green
RoHS & Green
NIPDAU
THVD1450DGK
THVD1450DGKR
THVD1450DR
THVD1450DRBR
THVD1450DRBT
THVD1451D
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
NIPDAUAG
NIPDAUAG | SN
NIPDAU
8
2500 RoHS & Green
2500 RoHS & Green
3000 RoHS & Green
1450
8
VD1450
1450
SON
DRB
DRB
D
8
SN
SON
8
250
75
RoHS & Green
RoHS & Green
SN
1450
SOIC
8
NIPDAU
VD1451
VD1451
1451
THVD1451DR
THVD1451DRBR
THVD1451DRBT
THVD1452D
SOIC
D
8
2500 RoHS & Green
3000 RoHS & Green
NIPDAU
SON
DRB
DRB
D
8
SN
SON
8
250
50
RoHS & Green
RoHS & Green
RoHS & Green
SN
1451
SOIC
14
10
10
14
NIPDAU
1452
THVD1452DGS
THVD1452DGSR
THVD1452DR
VSSOP
VSSOP
SOIC
DGS
DGS
D
80
NIPDAUAG
NIPDAUAG | SN
NIPDAU
1452
2500 RoHS & Green
2500 RoHS & Green
1452
1452
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
21-Mar-2023
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THVD1410DGKR
THVD1410DGKR
THVD1450DGKR
THVD1450DRBR
THVD1450DRBT
THVD1451DRBR
THVD1451DRBT
THVD1452DGSR
VSSOP
VSSOP
VSSOP
SON
DGK
DGK
DGK
DRB
DRB
DRB
DRB
DGS
8
8
2500
2500
2500
3000
250
330.0
330.0
330.0
330.0
180.0
330.0
180.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
5.3
5.3
5.3
3.3
3.3
3.3
3.3
5.3
3.4
3.4
3.4
3.3
3.3
3.3
3.3
3.4
1.4
1.4
1.4
1.0
1.0
1.0
1.0
1.4
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q2
Q2
Q2
Q2
Q1
8
8
SON
8
SON
8
3000
250
SON
8
VSSOP
10
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THVD1410DGKR
THVD1410DGKR
THVD1450DGKR
THVD1450DRBR
THVD1450DRBT
THVD1451DRBR
THVD1451DRBT
THVD1452DGSR
VSSOP
VSSOP
VSSOP
SON
DGK
DGK
DGK
DRB
DRB
DRB
DRB
DGS
8
8
2500
2500
2500
3000
250
366.0
364.0
364.0
346.0
200.0
346.0
200.0
366.0
364.0
364.0
364.0
346.0
183.0
346.0
183.0
364.0
50.0
27.0
27.0
35.0
25.0
35.0
25.0
50.0
8
8
SON
8
SON
8
3000
250
SON
8
VSSOP
10
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
THVD1410D
THVD1410DGK
THVD1450D
D
DGK
D
SOIC
VSSOP
SOIC
8
8
75
80
75
80
75
50
80
507
330
507
330
507
507
330
8
6.55
8
3940
500
4.32
2.88
4.32
2.88
4.32
4.32
2.88
8
3940
500
THVD1450DGK
THVD1451D
DGK
D
VSSOP
SOIC
8
6.55
8
8
3940
3940
500
THVD1452D
D
SOIC
14
10
8
THVD1452DGS
DGS
VSSOP
6.55
Pack Materials-Page 3
PACKAGE OUTLINE
DGS0010A
VSSOP - 1.1 mm max height
S
C
A
L
E
3
.
2
0
0
SMALL OUTLINE PACKAGE
C
SEATING PLANE
0.1 C
5.05
4.75
TYP
PIN 1 ID
AREA
A
8X 0.5
10
1
3.1
2.9
NOTE 3
2X
2
5
6
0.27
0.17
10X
3.1
2.9
1.1 MAX
0.1
C A
B
B
NOTE 4
0.23
0.13
TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.7
0.4
0 - 8
DETAIL A
TYPICAL
4221984/A 05/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.
www.ti.com
EXAMPLE BOARD LAYOUT
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
(R0.05)
TYP
SYMM
10X (0.3)
1
5
10
SYMM
6
8X (0.5)
(4.4)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221984/A 05/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DGS0010A
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
10X (1.45)
SYMM
(R0.05) TYP
10X (0.3)
8X (0.5)
1
5
10
SYMM
6
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221984/A 05/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRB0008F
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
S
C
A
L
E
3
0
.
A
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
1.6 0.05
(0.2) TYP
4
5
A
A
2X
1.95
2.4 0.05
8
1
6X 0.65
0.35
0.25
8X
PIN 1 ID
0.5
0.3
0.1
C A B
C
8X
(OPTIONAL)
0.05
4222121/C 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.55)
(2.8)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222121/C 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.6)
8X (0.3)
1
8
(0.635)
SYMM
(1.07)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222121/C 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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