THVD1500 [TI]
具有 ±8-kV IEC ESD 保护功能且速率高达 500kbps 的 5V RS-485 收发器;
| 型号： | THVD1500 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 ±8-kV IEC ESD 保护功能且速率高达 500kbps 的 5V RS-485 收发器 |
| 文件： | 总31页 (文件大小：829K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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THVD1500
ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
具有 ±8kV IEC ESD 保护功能的 THVD1500 500kbps RS-485 收发器
1 特性
2 应用
1
•
达到或超出 TIA/EIA-485A 标准和中国国家电网公
司 (SGCC) 第 11 部分串行通信协议 RS-485 标准
的要求
•
•
•
•
电量计
逆变器
HVAC 系统
视频监控系统
•
•
•
4.5V 至 5.5V 电源电压
半双工 RS-422/RS-485
总线 I/O 保护
3 说明
–
–
–
–
±16kV HBM ESD
THVD1500 是适用于工业应用的强大半双工 RS-485
收发器。这些总线引脚可耐受高级别的 IEC 接触放电
ESD 事件，从而无需使用其他系统级保护组件。
±8kV IEC 61000-4-2 接触放电
±10kV IEC 61000-4-2 空气间隙放电
±2kV IEC 61000-4-4 快速瞬变脉冲
该器件由 5V 单电源供电。总线引脚具备宽共模电压范
围和低输入泄漏，因此 THVD1500 适用于长电缆上的
多点 应用。
•
•
•
扩展的工业温度范围：-40°C 至 125°C
用于噪声抑制的大接收器滞后
低功耗
THVD1500 采用可实现简易兼容性的工业标准 8 引脚
SOIC 封装。该器件的温度范围是 -40°C 至 125°C。
–
–
低待机电源电流：小于 1µA
运行静态电流：小于 660µA
•
•
•
•
适用于热插拔功能的无干扰加电/断电
开路、短路和空闲总线失效防护
1/8 单位负载选项（多达 256 个总线节点）
低 EMI 500kbps
器件信息(1)
器件编号
THVD1500
封装
SOIC (8)
封装尺寸（标称值）
4.90mm × 3.91mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
空白
空白
空白
简化原理图
1
2
R
7
6
RE
B
A
3
4
DE
D
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEY4
THVD1500
ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
www.ti.com.cn
目录
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 15
9.1 Application Information........................................ 15
9.2 Typical Application ................................................. 15
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Power Dissipation ..................................................... 5
6.6 Electrical Characteristics........................................... 6
6.7 Switching Characteristics.......................................... 7
6.8 Typical Characteristics.............................................. 8
Parameter Measurement Information ................ 10
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagrams ..................................... 13
9
10 Power Supply Recommendations ..................... 19
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 器件和文档支持 ..................................................... 21
12.1 器件支持................................................................ 21
12.2 第三方产品免责声明.............................................. 21
12.3 接收文档更新通知 ................................................. 21
12.4 社区资源................................................................ 21
12.5 商标....................................................................... 21
12.6 静电放电警告......................................................... 21
12.7 术语表 ................................................................... 21
13 机械、封装和可订购信息....................................... 22
7
8
4 修订历史记录
Changes from Original (July 2018) to Revision A
Page
•
•
•
•
将标题中的“300kbps RS-485”更改成了“500kbps RS-485”..................................................................................................... 1
将特性 中的“低 EMI 300kbps”更改成了“低 EMI 500kbps” ...................................................................................................... 1
Changed Signaling rate From: 300 kbps To: 500 kbps in the Recommended Operating Condition ..................................... 5
Changed text From: "data transmission up to 300 kbps" To: "data transmission up to 500 kbps" in the Overview
section .................................................................................................................................................................................. 13
2
Copyright © 2017–2018, Texas Instruments Incorporated
THVD1500
www.ti.com.cn
ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
R
RE
DE
D
1
2
3
4
8
7
6
5
VCC
B
A
GND
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
R
NO.
1
Digital output
Digital input
Digital input
Digital input
Ground
Receive data output
RE
DE
D
2
Receiver enable, active low (internal 2-MΩ pull-up)
Driver enable, active high (internal 2-MΩ pull-down)
Driver data input
3
4
GND
A
5
Local device ground
6
Bus input/output
Bus input/output
Power
Bus I/O port, A (complementary to B)
Bus I/O port, B (complementary to A)
5-V supply
B
7
VCC
8
Copyright © 2017–2018, Texas Instruments Incorporated
3
THVD1500
ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–18
MAX
7
UNIT
V
Supply voltage
Bus voltage
VCC
Range at any bus pin (A or B)
Range at any logic pin (D, DE, or RE)
18
V
–0.3
5.7
Input voltage
V
Transient pulse voltage range at any bus pin
(A or B) through 100 Ω
–100
–24
100
Receiver output current
IO
24
mA
°C
°C
°C
Junction temperature
170
125
150
Absolute ambient temperature, TA
Storage temperature, Tstg
–55
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
UNIT
Pins Bus terminals and
GND
Contact Discharge, per IEC 61000-4-2
Air Gap Discharge, per IEC 61000-4-2
±8,000
Pins Bus terminals and
GND
±10,000
±16,000
±4,000
±1,500
Pins Bus terminals and
GND
V(ESD)
Electrostatic discharge
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
V
All pins except Bus
terminals and GND
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
Machine model (MM), per JEDEC JESD22-A115-A
±400
V(EFT)
Electrical fast transient
Per IEC 61000-4-4
Pins Bus terminals
±2,000
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4
Copyright © 2017–2018, Texas Instruments Incorporated
THVD1500
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ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
-7
NOM
MAX
5.5
UNIT
V
VCC
VI
Supply voltage
Input voltage at any bus terminal(1)
12
V
High-level input voltage (Driver, driver enable, and receiver enable
inputs)
VIH
VIL
2
0
VCC
0.8
V
V
Low-level input voltage (Driver, driver enable, and receiver enable
inputs)
VID
IO
Differential input voltage
Output current, Driver
Output current, Receiver
Differential load resistance
Signaling rate
-12
-60
-8
12
60
8
V
mA
mA
Ω
IOR
RL
54
1/tUI
TA
500
125
150
kbps
°C
Operating ambient temperature
Junction temperature
-40
-40
TJ
°C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
6.4 Thermal Information
THVD1500
THERMAL METRIC(1)
D (SOIC)
8 PINS
130.1
72.8
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
Thermal shut-down temperature
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C
RθJC(top)
RθJB
73.6
ψJT
25.0
ψJB
72.9
RθJC(bot)
TJ(TSD)
NA
170
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Power Dissipation
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
Unterminated RL = 300 Ω,
CL = 50 pF (driver)
300 kbps
300 kbps
300 kbps
50
mW
Driver and receiver enabled,
VCC = 5.5 V, TJ = 150 °C,
RS-422 load RL = 100 Ω,
50% duty cycle square wave at signaling CL = 50 pF (driver)
PD
110
170
mW
mW
rate
RS-485 load RL = 54 Ω,
CL = 50 pF (driver)
Copyright © 2017–2018, Texas Instruments Incorporated
5
THVD1500
ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
www.ti.com.cn
MAX UNIT
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Driver
RL = 60 Ω, -7 V ≤ Vtest ≤ 12 (See 图 8)
RL = 100 Ω (See 图 9)
1.5
2
2
2.5
2
V
V
V
Driver differential output
voltage magnitude
|VOD
|
RL = 54 Ω (See 图 9)
1.5
Change in differential
output voltage
Δ|VOD
|
RL = 54 Ω or 100 Ω (See 图 9)
RL = 54 Ω or 100 Ω (See 图 9)
RL = 54 Ω or 100 Ω (See 图 9)
RL = 54 Ω or 100 Ω (See 图 9)
–50
1
50
3
mV
V
Common-mode output
voltage
VOC
VCC/2
450
Steady-state common-
mode output voltage
ΔVOC(SS)
–50
50
mV
Peak-to-peak common-
mode output voltage
VOC(PP)
mV
mA
IOS
Short-circuit output current DE = VCC, -7 V ≤ VO ≤ 12 V, or A pin shorted to B pin
–100
100
100
Receiver
VI = 12 V
VI = -7 V
75
µA
µA
DE = 0 V,
Bus input current
II1
VCC = 0 V or 5.5 V
-97
96
-70
VA = -7 V, VB = 12 V and
Bus input impedance
RA, RB
VTH+
kΩ
VA = 12 V, VB = -7 V (See 图 14)
Positive-going input
threshold voltage
See(1)
–70
–50
mV
Negative-going input
threshold voltage
VTH-
VHYS
VOH
VOL
IOZ
–200
20
–150
50
See(1)
mV
mV
V
Input hysteresis
VCC
-
Output high voltage
Output low voltage
IOH = -8 mA
4
0.3
IOL = 8 mA
0.2
0.4
1
V
Output high-impedance
current
VO = 0 V or VCC, RE = VCC
-1
µA
mA
IOSR
Output short-circuit current RE = 0, DE = 0, See 图 13
95
Logic
Input current
IIN
4.5 V ≤ VCC ≤ 5.5 V
(D, DE, RE)
–5
0
5
µA
Supply
RE = 0 V, DE = VCC, No
load
Driver and receiver enabled
440
295
275
0.1
660
420
400
1
µA
µA
µA
µA
RE = VCC, DE = VCC
,
Driver enabled, receiver disabled
Supply current (quiescent)
No load
ICC
RE = 0 V, DE = 0 V, No
load
Driver disabled, receiver enabled
RE = VCC, DE = 0 V, D
= open, No load
Driver and receiver disabled
(1) Under any specific conditions, VIT+ is assured to be at least VHYS higher than VIT–.
6
Copyright © 2017–2018, Texas Instruments Incorporated
THVD1500
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ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
6.7 Switching Characteristics
over recommended operating conditions
PARAMETER
Driver
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Differential output rise/fall
time
tr, tf
180
250
450
ns
RL = 54 Ω, CL = 50 pF
See 图 10
tPHL, tPLH Propagation delay
tSK(P) Pulse skew, |tPHL – tPLH
250
25
350
40
ns
ns
ns
ns
µs
|
tPHZ, tPLZ Disable time
tPZH, tPZL Enable time
Receiver
70
160
400
3
RE = 0 V
RE = VCC
See 图 11 and 图 12
220
1.5
Differential output rise/fall
time
tr, tf
15
25
ns
CL = 15 pF
See 图 15
tPHL, tPLH Propagation delay
tSK(P) Pulse skew, |tPHL – tPLH
tPHZ, tPLZ Disable time
70
3
100
7
ns
ns
ns
ns
|
15
30
tPZH(1)
,
,
,
DE = VCC
DE = 0 V
See 图 16
See 图 17
100
175
tPZL(1)
tPZH(2)
tPZL(2)
Enable time
1
4
μs
版权 © 2017–2018, Texas Instruments Incorporated
7
THVD1500
ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
6.8 Typical Characteristics
www.ti.com.cn
5
4.5
4
5
4.5
4
VOL
VOH
VOD
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
20
40
60
80
0
20
40
60
80
IO Driver Output Current (mA)
IO Driver Output Current (mA)
D001
D002
VCC = 5 V
DE = VCC
VCC = 5 V
DE = VCC
D = 0 V
图 1. Driver Output voltage vs Driver Output Current
图 2. Driver Differential Output voltage vs Driver Output
Current
250
50
45
40
35
30
25
20
15
10
5
245
240
235
230
225
220
215
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
80
100
120
VCC Supply Voltage (V)
Temperature (èC)
D003
D004
RL = 54 Ω
DE = VCC
D = VCC
TA = 25°C
图 3. Driver Output Current vs Supply Voltage
图 4. Driver Rise or Fall Time vs Temperature
160
158
156
154
152
150
48
47.5
47
46.5
46
45.5
45
-40
-20
0
20
40
60
80
100
120
50
100
150
200
250
300
Temperature (èC)
Signal Rate (Kbps)
D005
D006
RL = 54 Ω
图 5. Driver Propagation Delay vs Temperature
图 6. Supply Current vs Signal Rate
8
版权 © 2017–2018, Texas Instruments Incorporated
THVD1500
www.ti.com.cn
ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
Typical Characteristics (接下页)
6
5
4
3
2
1
0
VCM=12V
VCM=0V
VCM=-7V
-170
-150
-130
-110
-90
-70
-50
Differential Input Voltage VID (mV)
D007
图 7. Receiver Output vs Input
版权 © 2017–2018, Texas Instruments Incorporated
9
THVD1500
ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
www.ti.com.cn
7 Parameter Measurement Information
375 Ω
Vcc
DE
D
A
B
V
test
VOD
R
0V or V
cc
L
375 Ω
图 8. Measurement of Driver Differential Output Voltage With Common-Mode Load
A
V
A
A
B
R /2
L
B
D
V
B
0V or V
cc
V
OD
V
OC(PP)
R /2
L
ûV
OC(SS)
V
OC
C
L
V
OC
图 9. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
V
cc
Vcc
DE
50%
V
I
0 V
A
B
t
t
R =
L
54 Ω
PHL
PLH
D
~
V
2 V
~
C = 50 pF
L
OD
90%
50%
10%
Input
50 Ω
V
I
Generator
V
OD
~ œ 2 V
~
t
r
t
f
图 10. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A
V
cc
S1
V
O
D
50%
V
I
0 V
V
B
R
110 Ω
=
DE
50 Ω
L
t
PZH
=
C
L
Input
OH
50 pF
90%
Generator
V
I
50%
V
O
~
~ 0V
t
PHZ
图 11. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load
Vcc
Vcc
50%
RL= 110 Ω
VI
tPZL
VO
A
B
0 V
S1
VO
tPLZ
D
Vcc
≈
DE
CL=
50 pF
Input
Generator
50%
10%
VOL
VI
50 Ω
图 12. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
10
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ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
Parameter Measurement Information (接下页)
VCC
RE
DE
DI
VCC
A
B
A
RO
GND
RS-485
GND
GND
图 13. Measurement of Receiver Output Short Circuit Current
VCC
RE
DE
DI
VCC
A
V
12 - (-7)
| IV |+| IV
R A , RB
=
B
V
|
b
a
V
RO
GND
RS-485
GND
GND
图 14. Measurement of Bus Impedance
3 V
0 V
VOH
50%
V
I
A
B
R
VO
t
tPHL
Input
Generator
PLH
50 Ω
V
1.5V
0 V
I
90%
50%
10%
CL=15 pF
RE
V
OD
V
tr
OL
t
f
图 15. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
V
cc
Vcc
DE
Vcc
V
50%
I
0V
V
A
B
tPZH(1)
1 kΩ
tPHZ
D
V
O
R
D at Vcc
S1 to GND
0V or Vcc
S1
OH
90%
V
50%
O
CL=15 pF
≈ 0V
RE
tPZL(1)
tPLZ
Input
Generator
D at 0V
S1 to Vcc
V
CC
50 Ω
V
I
V
50%
O
10%
V
OL
图 16. Measurement of Receiver Enable/Disable Times With Driver Enabled
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Parameter Measurement Information (接下页)
Vcc
0V
Vcc
VI
50%
A
B
1 kΩ
tPZH(2)
V or 1.5V
VO
R
S1
VOH
A at 1.5V
B at 0V
S1 to GND
1.5 V or 0V
50%
VO
CL=15 pF
RE
≈ 0V
tPZL(2)
Input
Generator
A at 0V
B at 1.5V
S1 to VCC
VCC
50 Ω
VI
VO
50%
VOL
图 17. Measurement of Receiver Enable Times With Driver Disabled
12
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ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
8 Detailed Description
8.1 Overview
The THVD1500 is a low-power, half-duplex RS-485 transceiver suitable for data transmission up to 500 kbps.
8.2 Functional Block Diagrams
VCC
R
RE
A
B
DE
D
GND
8.3 Feature Description
Internal ESD protection circuits protect the transceiver against Electrostatic Discharges (ESD) according to IEC
61000-4-2 of up to ±8 kV (Contact Discharge), ±10 kV (Air Gap Discharge) and against electrical fast transients
(EFT) according to IEC 61000-4-4 of up to ±2 kV.
The THVD1500 provides internal biasing of the receiver input thresholds in combination with large input-
threshold hysteresis. With a positive input threshold of VIT+ = –50 mV and an input hysteresis of VHYS = 50 mV,
the receiver output remains logic high under a bus-idle or bus-short conditions without the need for external
failsafe biasing resistors. Device operation is specified over a wide temperature range from –40°C to 125°C.
8.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined
as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
表 1. Driver Function Table
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
A
H
L
B
L
H
H
Actively drive bus high
Actively drive bus low
L
X
H
L
H
Z
Z
L
Z
Z
H
Driver disabled
X
OPEN
H
Driver disabled by default
Actively drive bus high by default
OPEN
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R, turns
high. When VID is negative and lower than the negative input threshold, VIT-, the receiver output, R, turns low. If
VID is between VIT+ and VIT- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
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13
THVD1500
ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
www.ti.com.cn
表 2. Receiver Function Table
DIFFERENTIAL INPUT
VID = VA – VB
VIT+ < VID
ENABLE
OUTPUT
FUNCTION
RE
R
H
?
L
Receive valid bus high
Indeterminate bus state
Receive valid bus low
Receiver disabled
VIT- < VID < VIT+
VID < VIT-
L
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
14
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THVD1500
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ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The THVD1500 is a half-duplex RS-485 transceiver commonly used for asynchronous data transmissions. The
driver and receiver enable pins allow for the configuration of different operating modes.
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R
R
R
R
A
B
A
B
RE
RE
R
R
T
T
DE
D
DE
D
D
D
A
B
A
B
R
R
R
R
D
D
D
D
RE DE
RE DE
图 18. Typical RS-485 Network With Half-Duplex Transceivers
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
shorter the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 300 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
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15
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ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
www.ti.com.cn
Typical Application (接下页)
9.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in 公式 1.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
9.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the THVD1500 consists of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
9.2.1.4 Receiver Failsafe
The differential receivers of the THVD1500 are failsafe to invalid bus states caused by the following:
•
•
•
Open bus conditions, such as a disconnected connector
Shorted bus conditions, such as cable damage shorting the twisted-pair together
Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the
receiver is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. In order to comply with the RS-422 and RS-485 standards, the receiver
output must output a high when the differential input VID is more positive than 200 mV, and must output a low
when VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are
VIT+, VIT–, and VHYS (the separation between VIT+ and VIT–). As shown in the Electrical Characteristics table,
differential signals more negative than –200 mV will always cause a low receiver output, and differential signals
more positive than 200 mV will always cause a high receiver output.
When the differential input signal is close to zero, it is still above the VIT+ threshold, and the receiver output will
be high. Only when the differential input is more than VHYS below VIT+ will the receiver output transition to a low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value, VHYS, as well as the value of VIT+
.
16
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THVD1500
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ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
Typical Application (接下页)
9.2.1.5 Transient Protection
The bus pins of the THVD1500 transceiver family include on-chip ESD protection against ±16-kV HBM and ±8-
kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more
severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge resistance,
R(D), of the IEC model produce significantly higher discharge currents than the HBM model.
R(C)
R(D)
40
35
30
25
20
15
10
5
50 M
(1 M)
330 Ω
10-kV IEC
(1.5 kΩ)
Device
Under
Test
High-Voltage
Pulse
Generator
150 pF
(100 pF)
C(S)
10-kV HBM
0
0
50
100
150
200
250
300
Time (ns)
图 19. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables. Designers may choose to
implement protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
图 20 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automations.
The right hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
22
20
18
16
14
12
10
8
0.5-kV Surge
4-kV EFT
6
4
2
0.5-kV Surge
10-kV ESD
0
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
Time (µs)
Time (µs)
图 20. Power Comparison of ESD, EFT, and Surge Transients
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www.ti.com.cn
Typical Application (接下页)
In the event of surge transients, high-energy content is characterized by long pulse duration and slow decaying
pulse power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver
is converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver.
图 21 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT pulse
train that is commonly applied during compliance testing.
1000
100
Surge
10
1
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
图 21. Comparison of Transient Energies
18
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ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
Typical Application (接下页)
9.2.2 Detailed Design Procedure
In order to protect bus nodes against high-energy transients, the implementation of external transient protection
devices is necessary. 图 22 suggest a protection circuit against 1 kV surge (IEC 61000-4-5) transients. 表 3
shows the associated Bill of Materials.
5V
100nF
100nF
10k
V
CC
R1
R
RxD
TVS
RE
DE
D
A
B
MCU/
UART
DIR
TxD
R2
10k
GND
图 22. Transient Protection Against ESD, EFT, and Surge Transients for Half-Duplex Devices
表 3. Bill of Materials
DEVICE
XCVR
R1
FUNCTION
ORDER NUMBER
MANUFACTURER
RS-485 transceiver
THVD1500
TI
10-Ω, pulse-proof thick-film resistor
CRCW0603010RJNEAHP
CDSOT23-SM712
Vishay
Bourns
R2
TVS
Bidirectional 400-W transient suppressor
9.2.3 Application Curves
Time œ 2 ms/div
Data Rate = 300 Kbps
图 23. TBD
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100
nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
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www.ti.com.cn
11 Layout
11.1 Layout Guidelines
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against surge transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across
the board.
2. Use VCC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART and/or
controller ICs on the board.
5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via inductance.
6. Use 1-kΩ to 10-kΩ pullup and pulldown resistors for enable lines to limit noise currents in theses lines during
transient events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
11.2 Layout Example
5
Via to ground
C
Via to VCC
4
R
6
6
R
R
1
R
MCU
5
TVS
THVD1500
5
图 24. Layout Example
20
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THVD1500
www.ti.com.cn
ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
12 器件和文档支持
12.1 器件支持
12.2 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。.
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
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13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
22
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THVD1500
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ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
PACKAGE OUTLINE
D0008B
SOIC - 1.75 mm max height
SCALE 2.800
SOIC
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A
B
.005-.010 TYP
[0.13-0.25]
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
.041
[1.04]
4221445/B 04/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15], per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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版权 © 2017–2018, Texas Instruments Incorporated
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THVD1500
ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
www.ti.com.cn
EXAMPLE BOARD LAYOUT
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.055)
[1.4]
8X (.061 )
[1.55]
SEE
DETAILS
SEE
DETAILS
SYMM
SYMM
1
1
8
8
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
5
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.213)
[5.4]
(.217)
[5.5]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221445/B 04/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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THVD1500
www.ti.com.cn
ZHCSGF8A –JULY 2017–REVISED NOVEMBER 2018
EXAMPLE STENCIL DESIGN
D0008B
SOIC - 1.75 mm max height
SOIC
8X (.061 )
[1.55]
8X (.055)
[1.4]
SYMM
SYMM
1
1
8
8
5
8X (.024)
[0.6]
8X (.024)
[0.6]
SYMM
SYMM
5
4
4
6X (.050 )
[1.27]
6X (.050 )
[1.27]
(.217)
[5.5]
(.213)
[5.4]
HV / ISOLATION OPTION
.162 [4.1] CLEARANCE / CREEPAGE
IPC-7351 NOMINAL
.150 [3.85] CLEARANCE / CREEPAGE
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:6X
4221445/B 04/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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版权 © 2017–2018, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THVD1500D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
VD1500
VD1500
THVD1500DR
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THVD1500DR
THVD1500DR
SOIC
SOIC
D
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
6.4
5.2
5.2
2.1
2.1
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THVD1500DR
THVD1500DR
SOIC
SOIC
D
D
8
8
2500
2500
356.0
340.5
356.0
336.1
35.0
25.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
SOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
THVD1500D
D
8
75
507
7.85
3750
2.24
Pack Materials-Page 3
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