THVD1454 [TI]
具有集成式 120Ω 可切换终端的 3V 至 5.5V 半双工 RS-485 收发器;
| 型号： | THVD1454 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成式 120Ω 可切换终端的 3V 至 5.5V 半双工 RS-485 收发器 |
| 文件： | 总29页 (文件大小：1985K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THVD1454
ZHCSQ45 –JANUARY 2023
THVD1454 具有集成
120Ω 可切换终端和压摆率控制功能的3V 至5.5V 半双工RS-485 收发器
1 特性
3 说明
• 符合或超出TIA/EIA-485A 标准要求
• 3V 至5.5V 电源电压
• 差分输出超过2.1V，在5V 电源下与PROFIBUS
兼容
• 半双工RS-422/RS-485
• 总线引脚之间的引脚控制片上120Ω端接电阻
• 最大数据速率可配置
THVD1454 是一款适用于工业应用的灵活半双工
RS-485 收发器。该器件具有片上120Ω端接电阻器和
驱动器输出压摆率控制等功能。这两个特性均由引脚控
制。这使得该器件可以在任何网络中的任何节点位置
（末端节点或中间节点）使用，无论是慢速还是快速。
终端设备设计人员现在可以设计通用印刷电路板
(PCB)，并使用软件配置PCB 来满足各种应用需求。
这可以为客户节省设计和鉴定时间。
– SLR = 高：500kbps
– SLR = 低电平或悬空：20Mbps
• 总线I/O 保护
这些总线引脚可耐受高级别的 IEC 接触放电 ESD 事
件，因此无需使用其他系统级保护元件。这些器件由
3V 至 5.5V 单电源供电。总线引脚具备宽共模电压范
围和低输入泄漏，从而使这些器件适用于长线缆上的多
点应用。
– ±16kV HBM ESD
– ±8kV IEC 61000-4-2 接触放电
– ±15kV IEC 61000-4-2 空气间隙放电
– ±4kV IEC 61000-4-4 快速瞬变脉冲
– ±16V 总线故障保护（总线引脚上的绝对最大电
压）
THVD1454 采用节省空间的高效散热型10 引脚VSON
封装(3mm x 3mm)。该器件的额定温度范围为 –40°C
至125°C。
• 工业级工作温度范围：
-40°C 至125°C
• 低功耗
封装信息
封装(1)
封装尺寸（标称值）
器件型号
THVD1454
VSON (10)
3.00mm x 3.00mm
– 关断电源电流< 5µA
– 运行期间静态电流< 3mA
• 适用于热插拔功能的无干扰上电/断电
• 开路、短路和空闲总线失效防护
• 1/8 单位负载（多达256 个总线节点）
• 节省空间的小型高效散热型10 引脚VSON 封装
(3mm x 3mm)
(1) 如需完整的器件型号，请参阅数据表末尾的可订购产品附录。
SLR
VCC
A
B
R
RE
DE
2 应用
I/O
and
control
• 工厂自动化与控制
• 楼宇自动化
• 电机驱动
120
D
• 电力输送
• 工业运输
• HVAC 系统
• 智能电表
TERM
简化版应用
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFQ5
THVD1454
ZHCSQ45 –JANUARY 2023
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagrams....................................... 12
8.3 Feature Description...................................................12
8.4 Device Functional Modes..........................................12
9 Application Information Disclaimer.............................15
9.1 Application Information............................................. 15
9.2 Typical Application.................................................... 15
9.3 Power Supply Recommendations.............................20
9.4 Layout....................................................................... 20
10 Device and Documentation Support..........................21
10.1 Device Support....................................................... 21
10.2 接收文档更新通知................................................... 21
10.3 支持资源..................................................................21
10.4 Trademarks.............................................................21
10.5 静电放电警告.......................................................... 21
10.6 术语表..................................................................... 21
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings .............................................................. 4
6.3 ESD Ratings [IEC]...................................................... 4
6.4 Recommended Operating Conditions.........................5
6.5 Thermal Information....................................................5
6.6 Power Dissipation....................................................... 5
6.7 Electrical Characteristics.............................................6
6.8 Switching Characteristics_500 kbps........................... 8
6.9 Switching Characteristics_20 Mbps............................9
6.10 Switching Characteristics_Termination resistor........ 9
7 Parameter Measurement Information..........................10
8 Detailed Description......................................................12
8.1 Overview...................................................................12
Information.................................................................... 21
11.1 Tape and Reel Information......................................22
11.2 Mechanical Data..................................................... 24
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
January 2023
*
Initial Release
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5 Pin Configuration and Functions
R
RE
1
2
3
4
5
10
9
V
B
A
ꢀ
CC
Thermal
Pad
DE
8
D
7
SLR
GND
TERM
6
Not to scale
图5-1. VSON (DRC) Package, 10-Pins
(Top View)
表5-1. Pin Functions
PIN
TYPE
DESCRIPTION
NAME
R
NO.
1
Digital output
Digital input
Digital input
Logic output RS-485 data
RE
2
Receiver enable/disable. Internal pull-up. Receiver disabled by default
Driver enable/disable. Internal pull-down. Driver disabled by default
DE
3
Logic input RS485 data. Internal pull-up. Drives the bus high by default if driver is
enabled
D
4
Digital input
120 Ωon-chip termination control for A/B pins. Internal pull-down. Termination across
A/B is disabled by default
TERM
GND
SLR
5
6
7
Digital input
GND
Ground
Slew rate control. Internal pull-down, default 20 Mbps operation. Logic high SLR
enables slow speed (500 kbps)
Digital input
A
8
9
Bus input/output
Bus input/output
Power
RS-485 bus pin. This pin is non-inverting driver output or non-inverting receiver input
RS-485 bus pin. This pin is inverting driver output or inverting receiver input
3 V to 5.5 V supply
B
VCC
10
Thermal
Pad
--
Connect to GND for optimal thermal and electrical performance
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
–0.5
–16
-6
MAX
7
UNIT
V
Supply voltage
VCC
Bus voltage
Voltage at any bus pin (A or B) with respect to GND
16
V
Differential bus voltage
Input voltage
(A-B) or (B-A) with termination enabled
6
V
Range at any logic pin (D, DE, SLR, TERM, or RE)
5.7
24
V
–0.3
–24
–65
Receiver output current
Storage temperature
IO
mA
°C
Tstg
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.
6.2 ESD Ratings
VALUE
UNIT
Bus terminals (A, B) and GND
±16,000
V
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
All pins except bus terminals
and GND
V(ESD)
Electrostatic discharge
±4,000
±1,500
V
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings [IEC]
VALUE
UNIT
V
Contact discharge, per IEC 61000-4-2
Air-gap discharge, per IEC 61000-4-2
Per IEC 61000-4-4
Bus terminals and GND
Bus terminals and GND
Bus terminals
±8,000
±15,000
±4,000
Electrostatic discharge, on chip
termination ON or OFF
V(ESD)
V(EFT)
Electrical fast transient
V
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
5.5
12
UNIT
V
VCC
VI
Supply voltage
Input voltage at any bus terminal (separately or common mode)(1)
High-level input voltage (D, DE, RE, TERM, SLR inputs)
Low-level input voltage (D, DE, RE, TERM, SLR inputs)
Output current, driver
V
–7
2
VIH
VIL
IO
5.5
0.8
60
V
0
V
mA
mA
–60
–8
54
IOR
RL
Output current, receiver
8
Differential load resistance
60
Ω
kbps
Mbps
°C
SLR = VIO
Signaling rate
500
20
1/tUI
SLR = GND or floating
(2)
TA
TJ
Operating ambient temperature
Junction temperature
-40
-40
125
150
(2)
°C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) Operation is specified for internal (junction) temperatures upto 150°C. Self-heating due to internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit which
disables the driver outputs when the junction temperature reaches typical 170°C.
6.5 Thermal Information
THVD1454
THERMAL METRIC(1)
DRC (VSON)
10 PINS
48.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
54
21.9
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.1
ψJT
21.9
ψJB
RθJC(bot)
6.7
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
6.6 Power Dissipation
PARAMETER
TEST CONDITIONS
Typical
185
Max
UNIT
SLR = H
500 kbps
20Mbps
500 kbps
20Mbps
210
340
360
430
Unterminated, TERM = L
mW
Driver and receiver enabled,
VCC = 5.5 V, TA = 125 °C,
D = square wave 50% duty
SLR = L
SLR = H
SLR = L
310
316
396
PD
TERM = H, With 120 Ωload between
mW
A/B inputs
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6.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC
= 5 V , unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Driver
1.5
2.1
2
3.3
3.3
4
V
V
V
V
V
RL = 60 Ω, –7 V ≤Vtest ≤12 V (See 图7-1 )
RL = 60 Ω, –7 V ≤Vtest ≤12 V, 4.5 V ≤VCC ≤5.5 V (See 图7-1 )
RL = 100 Ω(See 图7-2 )
Driver differential output
voltage magnitude
|VOD
|
2.1
1.5
3.3
3.3
RL = 54 Ω, 4.5 V ≤VCC ≤5.5 V (See 图7-2 )
RL = 54 Ω(See 图7-2 )
Change in magnitude of
differential output voltage
50
3
mV
V
Δ|VOD
|
RL = 54 Ωor 100 Ω(See 图7-2 )
RL = 54 Ωor 100 Ω(See 图7-2 )
–50
Common-mode output
voltage
VOC
VCC/2
Change in steady-state
common-mode output
voltage
50
mV
mA
ΔVOC(SS)
RL = 54 Ωor 100 Ω(See 图7-2 )
–50
IOS
Short-circuit output current
250
DE = VIO, -7 V ≤(VA or VB) ≤12 V, or A shorted to B
–250
Receiver
VI = 12 V
85
100
μA
μA
Bus input current
(termination disabled)
II
DE = 0 V, VCC = 0 V or 5.5 V
VI = –7 V
–100
–70
Receiver bus input leakage
current with termination
enabled
IRXT
DE = 0 V, VCC = 5.5 V, TERM = VCC
VI = - 7 to 12 V
-300
300
- 45
μA
Positive-going input
threshold voltage(1)
VTH+
- 85
mV
Negative-going input
threshold voltage(1)
Over common-mode range of - 7 V to 12 V
Measured between A and B, f = 1 MHz
VTH-
VHYS
CA,B
mV
mV
pF
–200
–150
50
Input hysteresis
30
Input differential
capacitance
20
VCC
–
VCC –
VOH
VOL
IOZ
Output high voltage
Output low voltage
V
V
IOH = –8 mA
0.4
0.2
IOL = 8 mA
0.2
0.4
2
Output high-impedance
current, R pin
VO = 0 V or VCC, RE = VCC
µA
–2
Logic
IIN
Input current (D, RE, DE ,
SLR, TERM)
-5
5
µA
3 V ≤VCC ≤5.5 V, 0 V ≤VIN ≤VCC
Thermal Protection
Thermal shutdown
threshold
TSHDN
Temperature rising
150
170
15
°C
°C
Thermal shutdown
hysteresis
THYS
Supply
UVVCC
Rising under-voltage
threshold on VCC
2.5
2.1
2.7
V
V
(rising)
UVVCC
Falling under-voltage
threshold on VCC
2
(falling)
UVVCC(hys Hysteresis on under-voltage
400
mV
of VCC
)
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6.7 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC
= 5 V , unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
RE = 0 V, DE = VCC
No load
,
Driver and receiver enabled
1.5
3
2.5
1.2
4
mA
mA
mA
µA
RE = VCC, DE = VCC
No load
,
Driver enabled, receiver disabled
Driver disabled, receiver enabled
Driver and receiver disabled
Driver and receiver enabled
1.3
0.8
0.2
1.4
1
Supply current (quiescent),
VCC = 4.5 V to 5.5 V, TERM
= Floating or low, SLR = X
ICC
RE = 0 V, DE = 0 V,
No load
RE = VCC, DE = 0 V,
D = open, No load
RE = 0 V, DE = VCC
,
2
mA
mA
mA
µA
No load
RE = VCC, DE = VCC
No load
,
Driver enabled, receiver disabled
Driver disabled, receiver enabled
Driver and receiver disabled
1.5
1
Supply current (quiescent),
VCC = 3 V to 3.6 V, TERM =
Floating or low, SLR = X
ICC
RE = 0 V, DE = 0 V,
No load
0.7
0.2
39
1
RE = VCC, DE = 0 V,
D = open, No load
4
Supply current in driver
termination mode
Driver enabled, receiver disabled with termination
ON
RE = VCC, DE= VIO
,
ICCDT
ICCRT
48
1.3
mA
mA
TERM = VCC
Supply current in receiver
termination mode
Receiver enabled and driver disabled, with
termination ON
RE = GND, DE = 0 V,
TERM = VCC
Supply current in device
disabled, termination
enabled mode
RE = VCC, DE = 0 V,
TERM = VCC
ICCT
Driver and Receiver disabled, termination ON
200
120
310
138
µA
On-Chip termination resistor
120 Ω termination across
receiver output A/B
terminals
DE = GND, TERM = VCC, VAB = 2 V, VB = -7 V, 0 V, 10 V
RTERM
102
Ω
See 图7-9
(1) VTH+ is specified to be at least VHYS higher than VTH–
.
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6.8 Switching Characteristics_500 kbps
500-kbps (with SLR = VCC) over recommended operating conditions. All typical values are at 25°C and supply voltage of VCC
= 5 V, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
VCC = 3 to 3.6 V, Typical
at 3.3V
200
220
250
270
260
260
2
600
600
500
450
15
ns
ns
ns
ns
ns
ns
tr, tf
Differential output rise/fall time
VCC = 4.5 to 5.5 V,
Typical at 5 V
VCC = 3 to 3.6 V, Typical
at 3.3V
RL = 54 Ω, CL = 50 pF
See 图7-3
tPHL, tPLH
Propagation delay
VCC = 4.5 to 5.5 V,
Typical at 5 V
VCC = 3 to 3.6 V, Typical
at 3.3V
tSK(P)
Pulse skew, |tPHL –tPLH
|
VCC = 4.5 to 5.5 V,
Typical at 5 V
2
15
tPHZ, tPLZ
tPZH, tPZL
Disable time
Enable time
RE = X
80
200
6
200
650
11
ns
ns
µs
RE = 0 V
RE = VCC
See 图7-4 and 图7-5
Receiver
tr, tf
Output rise/fall time
Propagation delay
Pulse skew, |tPHL –tPLH
Disable time
5
620
10
20
1200
40
ns
ns
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
tPHZ, tPLZ
tPZH(1)
CL = 15 pF
See 图7-6
|
DE = X
20
60
Enable time
DE = VCC
DE = VCC
80
155
1250
See 图7-7
See 图7-8
tPZL(1)
Enable time
650
tPZH(2)
,
Enable time
DE = 0 V
7
12
μs
tPZL(2)
(1)
A, B are RX input, Y/Z are driver output terminals in Full duplex mode
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6.9 Switching Characteristics_20 Mbps
20-Mbps (SLR = GND) over recommended operating conditions. All typical values are at 25°C and supply voltage of VCC = 5
V. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
VCC = 3 to 3.6 V, Typical
at 3.3 V
5
4.5
14
9
9
8
15
15
ns
ns
ns
ns
ns
ns
tr, tf
Differential output rise/fall time
VCC = 4.5 to 5.5 V,
Typical at 5 V
VCC = 3 to 3.6 V, Typical
at 3.3 V
22
20
1
50
RL = 54 Ω, CL = 50 pF
See 图7-3
tPHL, tPLH
Propagation delay
VCC = 4.5 to 5.5 V,
Typical at 5 V
40
VCC = 3 to 3.6 V, Typical
at 3.3 V
3.5
3.5
tSK(P)
Pulse skew, |tPHL –tPLH
|
VCC = 4.5 to 5.5 V,
Typical at 5 V
1
tPHZ, tPLZ
tPZH, tPZL
Disable time
Enable time
RE = X
25
30
6
50
70
11
ns
ns
RE = 0 V
RE = VCC
See 图7-4 and 图7-5
μs
Receiver
tr, tf
Output rise/fall time
Propagation delay
Pulse skew, |tPHL –tPLH
Disable time
5
10
55
4
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
30
CL = 15 pF
See 图7-6
|
tPHZ, tPLZ
DE = X
20
80
58
See 图7-7
See 图7-8
tPZH(1)
,
Enable time
Enable time
DE = VCC
155
11
ns
tPZL(1)
tPZH(2)
tPZL(2)
,
DE = 0 V
6
μs
(1) A, B are RX input, Y/Z are driver output terminals in Full duplex mode.
6.10 Switching Characteristics_Termination resistor
Parameters over recommended operating conditions. All typical values are at 25°C and supply voltage of VCC = 5 V , unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Termination resistor turn-on
time
tTEN
tTZ
1.5
4
µs
µs
RE = VCC, VAB = 2 V, VB = 0 V; See 图7-9
Termination resistor turn-off
time
4.6
7.2
RE = VCC, VAB = 2 V, VB = 0 V; See 图7-9
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7 Parameter Measurement Information
Vcc
375 Ω
DE
D
A
B
V
test
VOD
R
0V or V
cc
L
375 Ω
图7-1. Measurement of Driver Differential Output Voltage With Common-Mode Load
A
V
A
A
B
R /2
L
B
V
D
V
B
0V or V
cc
V
OD
V
OC(PP)
R /2
L
ûV
OC(SS)
V
OC
C
L
OC
图7-2. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
V
cc
0 V
Vcc
DE
50%
V
I
A
B
t
t
R =
L
54 Ω
PHL
PLH
D
~
V
2 V
~
C = 50 pF
L
OD
90%
Input
50 Ω
V
50%
10%
I
Generator
V
OD
~ œ 2 V
~
t
r
t
f
图7-3. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A
V
cc
S1
V
O
D
50%
V
I
0 V
B
R
=
DE
50 Ω
L
t
PZH
=
C
L
50 pF
110 Ω
V
Input
Generator
OH
90%
V
I
50%
V
O
~
~ 0V
t
PHZ
图7-4. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load
Vcc
Vcc
50%
RL= 110 Ω
VI
tPZL
VO
A
B
0 V
S1
VO
tPLZ
D
Vcc
≈
DE
CL=
50 pF
Input
50%
10%
VOL
VI
Generator
50 Ω
图7-5. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
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3 V
50%
V
I
A
B
0 V
R
VO
t
tPHL
Input
Generator
PLH
50 Ω
V
1.5V
0 V
VOH
I
90%
CL=15 pF
50%
10%
RE
V
OD
V
tr
OL
t
f
图7-6. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
V
cc
Vcc
DE
Vcc
V
50%
I
0V
V
A
B
tPZH(1)
1 kΩ
tPHZ
D
V
O
R
D at Vcc
S1 to GND
0V or Vcc
S1
OH
90%
V
50%
O
CL=15 pF
≈ 0V
RE
tPZL(1)
tPLZ
Input
Generator
D at 0V
S1 to Vcc
V
CC
50 Ω
V
I
V
50%
O
10%
V
OL
图7-7. Measurement of Receiver Enable/Disable Times With Driver Enabled
Vcc
0V
Vcc
VI
50%
A
B
1 kΩ
tPZH(2)
V or 1.5V
VO
R
S1
VOH
A at 1.5V
B at 0V
S1 to GND
1.5 V or 0V
50%
VO
CL=15 pF
RE
≈ 0V
tPZL(2)
Input
Generator
A at 0V
B at 1.5V
S1 to VCC
VCC
50 Ω
VI
VO
50%
VOL
图7-8. Measurement of Receiver Enable Times With Driver Disabled
VIO
RTERM_RX = VAB / IA
50%
TERM
IA
A
0 V
R
VAB
VB
tRTEN
tRTZ
90%
50%
10%
B
TERM
IA
图7-9. Measurement of enable and disable times of bus terminal termination resistor
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8 Detailed Description
8.1 Overview
The THVD1454 is a flexible half duplex RS-485 transceiver. The device has slew rate control pin SLR which can
be used to set the device in maximum 20 Mbps mode or slew rate limited 500 kbps mode. THVD1454 also has
on-chip 120 Ωtermination resistor across bus terminals A/B which is controlled using TERM pin.
8.2 Functional Block Diagrams
VCC
GND
A
Transmit Data = D
DE
TX
TERM
B
Control
Logic
RE
SLR
RX
Receive Data = R
8.3 Feature Description
The THVD1454 operates from 3 V to 5.5 V bus supply. Internal ESD protection circuits on bus pins protect the
transceiver against Electrostatic Discharges (ESD) according to IEC 61000-4-2 of up to ±8 kV (Contact
Discharge), ±15 kV (Air Gap Discharge) and against electrical fast transients (EFT) according to IEC 61000-4-4
of up to ±4 kV.
8.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this condition, the differential output voltage
defined as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low,
and VOD is negative.
When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground; thus, when left open, the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
表8-1. Driver Function Table
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
A
H
L
B
L
H
H
Actively drive bus high
Actively drive bus low
L
X
H
L
H
Z
Z
L
Z
Z
H
Driver disabled
X
OPEN
H
Driver disabled by default
Actively drive bus high by default
OPEN
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VTH+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VTH-, the receiver output, R, turns
low. If VID is between VTH+ and VTH- the output is indeterminate.
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When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go fail safe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
表8-2. Receiver Function Table
DIFFERENTIAL INPUT
VID = VA –VB
VTH+ < VID
ENABLE
OUTPUT
FUNCTION
RE
R
H
?
L
Receive valid bus high
Indeterminate bus state
Receive valid bus low
Receiver disabled
VTH- < VID < VTH+
VID < VTH-
L
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
8.4.1 On-Chip Switchable Termination
THVD1454 has integrated termination resistor of nominal 120 Ω across A/B bus terminals. Termination resistor
is enabled or disabled using the TERM pin described in 表8-3.
表8-3. On-chip termination function table
Signal state
Function
Comments
TERM = VCC
120 Ωenabled between A and B
120 Ωdisabled between A and B
TERM = GND or floating
Termination is disabled by default
On-chip 120 Ω termination resistor variation with temperature and across common mode voltage is shown in 图
8-1 and 图8-2.
117
116.5
116
130
128
126
124
122
120
118
116
114
112
110
108
106
104
102
100
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
115.5
115
114.5
114
113.5
113
112.5
112
111.5
111
110.5
-60 -40 -20
0
20
40
60
80 100 120 140
-9
-6
-3
0
3
6
9
12
Temperature (°C)
Bus Common Mode Voltage (V)
图8-1. Termination Resistor vs Temperature
图8-2. Termination Resistor vs Bus Common Mode
voltage
THVD1454 on-chip termination resistor has been designed so the termination block offers a resistive load to the
bus, and does not alter the magnitude or phase of the bus signals from DC to 20Mbps signaling. See 图 8-3 and
图 8-4 with the bus voltage swept from -6 V to +6 V. Current into the bus changes linearly in both conditions of
termination ON or OFF.
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40
20
60
40
VCC = 3.3 V
VCC = 5 V
20
0
0
-20
-40
-60
-20
-40
-60
-6
-4
-2
0
2
4
6
-6
-4
-2
0
2
4
6
Voltage Across Bus Terminals VAB (V)
Voltage Across Bus Terminals VAB (V)
图8-3. Voltage vs Current Across AB Bus Pins
图8-4. Voltage vs Current Across AB Bus Pins
with Termination OFF
with Termination ON
8.4.2 Operational Data rate
THVD1454 can be used in slow speed or fast speed RS-485 networks by configuring Slew rate control (SLR)
pin. 表8-4 describes slew rate control function.
表8-4. Slew rate control function table
Signal state
Driver
Receiver
Comment
Active high slew rate limiting applied on driver
output and glitch filter in receiver path
enabled
Maximum speed of operation Maximum speed of operation
= 500kbps = 500kbps
SLR = VCC
Maximum speed of operation Maximum speed of operation Slew rate limiting on driver output disabled
= 20Mbps = 20Mbps and glitch filter in receiver path disabled
SLR = GND or floating
Receiver path in the slow speed mode (500kbps) provides additional noise filtering. To attenuate noise
frequency noise pulses from the bus which can be wrongly interpreted as valid data, SLR = VCC enables a low
pass filter to filter out pulses with frequency higher than typical 800 kHz.
8.4.3 Protection Features
THVD1454 has in-built protection features such as supply undervoltage, bus short circuit and thermal shutdown.
Supply undervoltage protection is present on VCC supply. This maintains the bus output and receiver logic output
in known driven state when the supply is above the rising undervoltage threshold. 表 8-5 describes the device
behavior in various scenarios of supply levels.
表8-5. Supply Function Table
VCC
Driver Output
Receiver Output
Termination across bus pins
AB
> UVVCC(rising)
< UVVCC(falling)
Determined by DE and D inputs
High impedance
Determined by RE and A-B
Undetermined
Determined by TERM pin
OFF
Bus terminals are protected against high voltage short circuit events up to ± 16 V. Additionally, bus short circuit
current is limited to 250 mA. In events like bus contention when multiple drivers are driving the bus
simultaneously, the current through the bus terminals is internally limited. If the power dissipation makes the
junction temperature cross 150°C, thermal shutdown is activated which disables the driver and receiver and
reduces the on-chip power dissipation. The device is enabled once the junction temperature falls by the thermal
shutdown hysteresis as specified in electrical parameter section of the data sheet.
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9 Application Information Disclaimer
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The THVD1454 is a flexible RS-485 transceiver used for asynchronous data transmissions. The driver and
receiver enable pins, slew rate control, and termination control pins allow the device to be applicable for various
point-to-point, multipoint or multidrop network configurations.
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length. 图 9-1 shows two end nodes terminated, while remaining nodes unterminated. THVD1454 can be
designed in all node designs. TERM pin allows configuring the nodes for end nodes and middle nodes in the
network.
A
A
A
B
R
RE
DE
R
R
R
RE
DE
A
B
A
B
120
THVD1454
THVD1454
120
120
120
B
B
D
D
D
D
TERM
R
R
THVD1454
R
R
THVD1454
D
D
D
D
TERM
TERM
V
V
CC
CC
RE
RE
DE
DE
图9-1. Typical Half Duplex RS-485 Network With all Nodes Using THVD1454
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
shorter the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 300 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5% or
10%.
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9.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in 方程式1.
L(STUB) ≤0.1 × tr × v × c
(1)
where:
• tr is the 10/90 rise time of the driver
• c is the speed of light (3 × 108 m/s)
• v is the signal velocity of the cable or trace as a factor of c
THVD1454 can be used in both slow speed and high speed networks with SLR pin configurability. Slew rate
limiting makes the driver output rise or fall time slower so that stub lengths can be increased.
9.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the THVD1454 consists of 1/8 UL
transceivers, connecting up to 256 transceivers to the bus is possible.
9.2.1.4 Receiver Failsafe
The differential receiver of the THVD1454 is failsafe to invalid bus states caused by the following:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver outputs a failsafe logic high state so that the output of the receiver
is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output
must output a high when the differential input VID is more positive than 200 mV, and must output a low when VID
is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VTH+
,
VTH–, and VHYS (the separation between VTH+ and VTH–). As shown in the 表 8-2, differential signals more
negative than –200 mV always causes a low receiver output, and differential signals more positive than 200 mV
always causes a high receiver output.
When the differential input signal is close to zero, it is still above the VTH+ threshold, and the receiver output is
high. Only when the differential input is more than VHYS below VTH+ does the receiver output transition to a low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value, VHYS, as well as the value of VTH+
.
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9.2.1.5 Transient Protection
The bus pins of the THVD1454 transceiver family include on-chip ESD protection against ±16-kV HBM and ±8-
kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more
severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge resistance,
R(D), of the IEC model produce significantly higher discharge currents than the HBM model.
R(C)
R(D)
40
35
30
25
20
15
10
5
50 M
(1 M)
330 Ω
10-kV IEC
(1.5 kΩ)
Device
Under
Test
High-Voltage
Pulse
Generator
150 pF
(100 pF)
C(S)
10-kV HBM
0
0
50
100
150
200
250
300
Time (ns)
图9-2. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment.
Common discharge events occur because of human contact with connectors and cables. Designers may choose
to implement protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
图 9-3 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left side of the diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which exceed the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients
are representative of events that may occur in factory environments in industrial and process automation.
The right side of the diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients may occur in power generation and power-grid systems.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
22
20
18
16
14
12
10
8
0.5-kV Surge
4-kV EFT
6
4
2
0.5-kV Surge
10-kV ESD
0
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
Time (µs)
Time (µs)
图9-3. Power Comparison of ESD, EFT, and Surge Transients
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For surge transients, high-energy content is characterized by long pulse duration and slow decaying pulse
power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver is
converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver. 图
9-4 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT pulse
train that is commonly applied during compliance testing.
1000
100
Surge
10
1
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
图9-4. Comparison of Transient Energies
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9.2.2 Detailed Design Procedure
To protect bus nodes against high-energy transients, the implementation of external transient protection devices
is necessary. 图 9-5 suggests a protection circuit against 1 kV surge (IEC 61000-4-5) transients. 表 9-1 shows
the associated bill of materials.
3 V to 5.5 V
1 µF
V
10 k
CC
R1
R
RxD
TVS
RE
DE
D
A
B
MCU/
UART
DIR
TxD
R2
10 k
TERM
GND SLR
图9-5. Transient Protection Against Surge Transients for THVD1454
表9-1. Bill of Materials
DEVICE
XCVR
R1
FUNCTION
ORDER NUMBER
MANUFACTURER(1)
RS-485 transceiver
THVD1454
TI
CRCW0603010RJNEAHP
CDSOT23-SM712
Vishay
Bourns
10-Ω, pulse-proof thick-film resistor
R2
TVS
Bidirectional 400-W transient suppressor
(1) See the Device Support.
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9.3 Power Supply Recommendations
For reliable operation at all data rates and supply voltages, VCC supply should be decoupled with a 1 μF
ceramic capacitor located as close to the supply pin as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
9.4 Layout
9.4.1 Layout Guidelines
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against surge transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across
the board.
2. Use VCC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply atleast 1 μF decoupling capacitors as close as possible to the VCC pin of the transceiver, UART
and/or controller ICs on the board.
5. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize effective via inductance.
6. Use 1-kΩto 10-kΩpull-up and pull-down resistors for logic lines to limit noise currents in these lines during
transient events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
9.4.2 Layout Example
Via to ground
Via to VCC
C
R
VCC
1
2
3
4
5
10
9
R
TVS
TVS
RE
B
A
R
MCU
8
DE
VIO
7
SLR
D
GND
GND
6
TERM
图9-6. Layout Example for THVD1454 in VSON-10 Package
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10 Device and Documentation Support
10.1 Device Support
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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11.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
PTHVD1454DRCR
PTHVD1454DRCT
VSON
VSON
DRC
DRC
10
10
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
VSON
Package Drawing Pins
SPQ
3000
250
Length (mm) Width (mm)
Height (mm)
35.0
PTHVD1454DRCR
PTHVD1454DRCT
DRC
DRC
10
10
356.0
210.0
356.0
185.0
VSON
35.0
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11.2 Mechanical Data
PACKAGE OUTLINE
DRC0010V
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.75
1.55
2X (0.5)
4X (0.25)
(0.2) TYP
EXPOSED
THERMAL PAD
5
6
2X
2
11
SYMM
2.4
2.2
10
1
8X 0.5
0.3
0.2
10X
SYMM
10X
PIN 1 ID
(OPTIONAL)
0.1
C A B
C
0.05
0.5
0.3
4226575/A 02/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRC0010V
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
SYMM
11
(3.4)
(2.3)
(0.9)
8X (0.5)
6
5
(R0.05) TYP
(0.2) TYP
VIA
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226575/A 02/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRC0010V
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.51)
(0.5)
SYMM
EXPOSED METAL
TYP
10X (0.6)
1
10
(1.53)
2X
10X (0.24)
(1.02)
11
SYMM
(0.61)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4226575/A 02/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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16-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTHVD1454DRCR
ACTIVE
VSON
DRC
10
5000
TBD
Call TI
Call TI
-40 to 125
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
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