TLA2024 [TI]
具有基准电压、PGA 和 I2C 的 12 位、4 通道 Δ-Σ ADC;
| 型号： | TLA2024 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有基准电压、PGA 和 I2C 的 12 位、4 通道 Δ-Σ ADC |
| 文件： | 总34页 (文件大小：1504K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLA2021, TLA2022, TLA2024
ZHCSH32 –NOVEMBER 2017
TLA202x 成本经优化的超小型、12 位、系统监控 ADC
1 特性
3 说明
1
•
•
•
业界成本最低的 12 位 Δ-Σ ADC
TLA2021, TLA2022, and TLA2024 器件 (TLA202x) 均
为易于使用的低功耗、12 位 Δ-Σ 模数转换器 (ADC)，
适用于任何类型的系统监控 应用 （比如电源或电池电
压监控、电流检测或温度测量）。TLA2021 和
TLA2022 采用超小型无引线 10 引脚 X2QFN 封装，
为单通道 ADC，而 TLA2024 采用 灵活的输入多路复
用器 (MUX)，具有两个差动输入测量选项或四个单端
输入测量选项。
超小型 X2QFN 封装：2mm × 1.5mm
高集成度：
–
4 个单端或 2 个差分输入成就了TLA2024业界
最高通道密度 ADC（每个通道 0.75mm²）
–
–
–
PGA（仅限 TLA2022 and TLA2024）
电压基准
振荡器
•
•
•
•
低电流消耗：150µA
TLA202x 集成了电压基准和振荡器。此外，TLA2022
and TLA2024 包括一个可编程增益放大器 (PGA)，其
可选输入范围为 ±256mV 至 ±6.144V，可同时支持大
小信号测量。
宽电源电压范围：2V 至 5.5V
可编程数据速率：128SPS 至 3.3kSPS
I2C™兼容接口：
–
–
支持标准模式和快速模式
三个引脚可选 I2C 地址
TLA202x 通过兼容 I2C 的接口进行通信，且既可在连
续转换模式下工作，也可在单冲转换模式下工作。在单
冲转换模式下，这些器件会在一次转换后自动断电，从
而显著降低空闲期间的功耗。
•
工作温度范围：-40°C 至 +85°C
2 应用
•
个人电子产品：
所有这些 特性，加上较宽的工作电源电压范围，使得
TLA202x 十分适合功率受限和空间受限的系统监控 应
用中，中对于高效率、高电源密度和稳健性的需求。
–
–
–
电视、平板电脑、手机
可穿戴设备
无人机、玩具
器件信息(1)
•
•
家用电器和厨房电器
楼宇自动化：
器件型号
TLA2021
封装
封装尺寸（标称值）
–
HVAC、烟雾探测器
TLA2022
TLA2024
X2QFN (10)
1.50mm x 2.00mm
•
•
•
电池电压和电流监控
温度感应
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
电池供电、便携式仪表
系统监控应用示例
3.3 V
3.3 V
Power Supply
Monitoring
3.3 V
VDD
Current
RSHUNT
Sense
Amplifier
Voltage
Reference
AIN0
AIN1
AIN2
AIN3
SCL
I2C Bus
12-Bit
û¯
ADC
I2C
SDA
Mux
PGA
Analog Output
Temperature
Sensor IC
Interface
ADDR
3.3 V
Oscillator
TLA2024
RBIAS
GND
Thermistor
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBAS846
TLA2021, TLA2022, TLA2024
ZHCSH32 –NOVEMBER 2017
www.ti.com.cn
目录
8.6 Register Maps......................................................... 17
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application .................................................. 23
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics........................................... 5
7.6 I2C Timing Requirements.......................................... 6
7.7 Typical Characteristics.............................................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagrams ....................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 12
8.5 Programming........................................................... 13
9
10 Power Supply Recommendations ..................... 24
10.1 Power-Supply Sequencing.................................... 24
10.2 Power-Supply Decoupling..................................... 24
11 Layout................................................................... 25
11.1 Layout Guidelines ................................................. 25
11.2 Layout Example .................................................... 26
12 器件和文档支持 ..................................................... 27
12.1 器件支持................................................................ 27
12.2 相关链接................................................................ 27
12.3 接收文档更新通知 ................................................. 27
12.4 社区资源................................................................ 27
12.5 商标....................................................................... 27
12.6 静电放电警告......................................................... 27
12.7 Glossary................................................................ 27
13 机械、封装和可订购信息....................................... 27
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
NOTES
November 2017
*
第一版.
2
Copyright © 2017, Texas Instruments Incorporated
TLA2021, TLA2022, TLA2024
www.ti.com.cn
ZHCSH32 –NOVEMBER 2017
5 Device Comparison Table
MAXIMUM SAMPLE
RATE
INPUT CHANNELS,
DIFFERENTIAL
(Single-Ended)
RESOLUTION
DEVICE
(Bits)
PGA
INTERFACE
(SPS)
TLA2021
TLA2022
TLA2024
12
12
12
3300
3300
3300
1 (1)
1 (1)
2 (4)
No
Yes
Yes
I2C
I2C
I2C
6 Pin Configuration and Functions
TLA2021 and TLA2022 RUG Package
10-Pin X2QFN
TLA2024 RUG Package
10-Pin X2QFN
Top View
Top View
ADDR
NC
1
2
3
4
9
8
7
6
SDA
VDD
NC
ADDR
NC
1
2
3
4
9
8
7
6
SDA
VDD
AIN3
AIN2
GND
AIN0
GND
AIN0
NC
Not to scale
Not to scale
Pin Functions
PIN
TYPE
DESCRIPTION
TLA2021,
TLA2022
NAME
ADDR
AIN0
AIN1
AIN2
AIN3
GND
NC
TLA2024
I2C slave address select pin. See the I2C Address Selection section for details.
Analog input 0(1)
Analog input 1(1)
Analog input 2(1)
1
1
4
Digital input
Analog input
Analog input
Analog input
Analog input
Supply
4
5
5
—
—
3
6
7
Analog input 3(1)
3
Ground
2, 6, 7
10
9
2
—
No connect; always leave floating
SCL
10
9
Digital input
Digital I/O
Supply
Serial clock input. Connect to VDD using a pullup resistor.
Serial data input and output. Connect to VDD using a pullup resistor.
Power supply. Connect a 0.1-µF, power-supply decoupling capacitor to GND.
SDA
VDD
8
8
(1) Float unused analog inputs, or tie unused analog inputs to GND.
版权 © 2017, Texas Instruments Incorporated
3
TLA2021, TLA2022, TLA2024
ZHCSH32 –NOVEMBER 2017
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings(1)
MIN
–0.3
MAX
UNIT
Power-supply voltage
Analog input voltage
Digital input voltage
Input current
VDD to GND
7
VDD + 0.3
7
AIN0, AIN1, AIN2, AIN3
SDA, SCL, ADDR
GND – 0.3
GND – 0.3
–10
V
Continuous, any pin except power-supply pins
Junction, TJ
10
mA
°C
–40
125
Temperature
Storage, Tstg
–60
125
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
VDD to GND
ANALOG INPUTS(1)
2
5.5
V
Full-scale input voltage range(2)
(VIN = VAINP – VAINN
FSR
±0.256
GND
±6.144
VDD
V
V
)
V(AINx)
Absolute input voltage
DIGITAL INPUTS
Digital input voltage
TEMPERATURE
TA Operating ambient temperature
GND
–40
5.5
85
V
°C
(1) AINP and AINN denote the selected positive and negative inputs. On the TLA2024, AINx denotes one of the four available analog inputs.
(2) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be
applied to this device. See the Full-Scale Range (FSR) and LSB Size section more information.
7.4 Thermal Information
TLA202x
THERMAL METRIC(1)
RUG (X2QFN)
10 PINS
245.2
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
69.3
172.0
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.2
ψJB
170.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
TLA2021, TLA2022, TLA2024
www.ti.com.cn
ZHCSH32 –NOVEMBER 2017
7.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +85°C; typical specifications are at TA = 25°C; all
specifications are at VDD = 3.3 V, data rate = 128 SPS, and FSR = ±2.048 V (unless otherwise noted)
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FSR = ±6.144 V(1)
FSR = ±4.096 V(1), FSR = ±2.048 V
FSR = ±1.024 V
10
6
Common-mode input impedance
Differential input impedance
MΩ
3
FSR = ±0.512 V, FSR = ±0.256 V
FSR = ±6.144 V(1)
FSR = ±4.096 V(1)
100
22
15
MΩ
kΩ
FSR = ±2.048 V
4.9
2.4
710
FSR = ±1.024 V
FSR = ±0.512 V, ±0.256 V
SYSTEM PERFORMANCE
Resolution (no missing codes)
Data rate
12
Bits
DR
INL
128, 250, 490, 920, 1600, 2400, 3300
SPS
Data rate variation
Integral nonlinearity(2)
Offset error
All data rates
–10%
10%
1
±1
LSB
LSB
Offset drift
Gain error(3)
Gain drift(3)
0.01
0.05%
10
LSB/°C
ppm/°C
dB
PSRR
CMRR
Power-supply rejection ratio
Common-mode rejection ratio
85
90
dB
DIGITAL INPUT/OUTPUT
VIL
Logic input level, low
GND
0.7 VDD
GND
0.3 VDD
5.5
V
V
VIH
VOL
Logic input level, high
Logic output level, low
Input leakage current
IOL = 3 mA
0.15
0.4
V
GND < VDigital Input < VDD
–10
10
µA
POWER SUPPLY
Power-down
Operating
0.5
150
0.9
0.5
0.3
IVDD Supply current
µA
VDD = 5 V
VDD = 3.3 V
VDD = 2 V
PD
Power dissipation
mW
(1) This parameter expresses the full-scale range of the ADC scaling. No more than VDD + 0.3 V or 5.5 V (whichever is smaller) must be
applied to this device. See the Full-Scale Range (FSR) and LSB Size section for more information.
(2) Best-fit INL; covers 99% of full-scale.
(3) Includes all errors from onboard PGA and voltage reference.
Copyright © 2017, Texas Instruments Incorporated
5
TLA2021, TLA2022, TLA2024
ZHCSH32 –NOVEMBER 2017
www.ti.com.cn
7.6 I2C Timing Requirements
over operating ambient temperature range and VDD = 2 V to 5.5 V (unless otherwise noted)
MIN
MAX
UNIT
STANDARD-MODE
fSCL
SCL clock frequency
10
4.7
4.0
100
kHz
µs
tLOW
tHIGH
Pulse duration, SCL low
Pulse duration, SCL high
µs
Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.
tHD;STA
4
µs
tSU;STA
tHD;DAT
tSU;DAT
tr
Setup time, repeated START condition
Hold time, data
4.7
0
µs
µs
ns
ns
ns
µs
µs
µs
µs
Setup time, data
250
Rise time, SCL, SDA
1000
250
tf
Fall time, SCL, SDA
tSU;STO
tBUF
Setup time, STOP condition
Bus free time, between STOP and START condition
Valid time, data
4.0
4.7
tVD;DAT
tVD;ACK
FAST-MODE
fSCL
3.45
3.45
Valid time, acknowledge
SCL clock frequency
10
1.3
0.6
400
kHz
µs
tLOW
Pulse duration, SCL low
Pulse duration, SCL high
tHIGH
µs
Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.
tHD;STA
0.6
µs
tSU;STA
tHD;DAT
tSU;DAT
tr
Setup time, repeated START condition
Hold time, data
0.6
0
µs
µs
ns
ns
ns
µs
µs
µs
µs
Setup time, data
100
20
Rise time, SCL, SDA
300
300
tf
Fall time, SCL, SDA
tSU;STO
tBUF
tVD;DAT
tVD;ACK
Setup time, STOP condition
Bus free time, between STOP and START condition
Valid time, data
0.6
1.3
0.9
0.9
Valid time, acknowledge
tSU;DAT
tf
tr
70%
30%
. . .
cont.
SDA
SCL
tHD;DAT
tVD;DAT
tf
tHIGH
tr
70%
30%
70%
30%
. . .
cont.
tLOW
9th clock
tHD;STA
S
1 / fSCL
1st clock cycle
tBUF
SDA
tVD;ACK
tSU;STA
tHD;STA
tSU;STO
70%
30%
SCL
Sr
P
S
9th clock
图 1. I2C Timing Requirements
6
版权 © 2017, Texas Instruments Incorporated
TLA2021, TLA2022, TLA2024
www.ti.com.cn
ZHCSH32 –NOVEMBER 2017
7.7 Typical Characteristics
at FSR = ±2.048 V and DR = 128 SPS (unless otherwise noted)
3
2.5
2
250
200
150
100
VDD = 5 V
VDD = 3 V
VDD = 2 V
1.5
1
50
VDD = 5 V
VDD = 3 V
0.5
VDD = 2 V
0
0
-40
-20
0
20
40
60
80 100
-40
-20
0
20
40
60
80
100
Temperature (èC)
Temperature (èC)
图 2. Operating Current vs Temperature
图 3. Power-Down Current vs Temperature
6
VDD = 5 V
VDD = 3 V
VDD = 2 V
4
2
0
-2
-4
-6
-40
-20
0
20
40
60
80
100
Temperature (èC)
图 4. Data Rate vs Temperature
版权 © 2017, Texas Instruments Incorporated
7
TLA2021, TLA2022, TLA2024
ZHCSH32 –NOVEMBER 2017
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TLA202x are a family of very small, low-power, 12-bit, delta-sigma (ΔΣ) analog-to-digital converters (ADCs).
The TLA202x consist of a ΔΣ ADC core with an internal voltage reference, a clock oscillator, and an I2C
interface. The TLA2022 and TLA2024 also integrate a programmable gain amplifier (PGA). 图 5, 图 6, and 图 7
show the functional block diagrams of the TLA2024, TLA2022, and TLA2021, respectively.
The TLA202x ADC core measures a differential signal, VIN, that is the difference of VAINP and VAINN. The
converter core consists of a differential, switched-capacitor ΔΣ modulator followed by a digital filter. This
architecture results in a very strong attenuation of any common-mode signals. Input signals are compared to the
internal voltage reference. The digital filter receives a high-speed bitstream from the modulator and outputs a
code proportional to the input voltage.
The TLA202x have two available conversion modes: single-shot and continuous-conversion. In single-shot
conversion mode, the ADC performs one conversion of the input signal upon request, stores the conversion
value to an internal conversion register, and then enters a power-down state. This mode is intended to provide
significant power savings in systems that only require periodic conversions or when there are long idle periods
between conversions. In continuous-conversion mode, the ADC automatically begins a conversion of the input
signal as soon as the previous conversion is complete. The rate of continuous conversion is equal to the
programmed data rate. Data can be read at any time and always reflect the most recently completed conversion.
8.2 Functional Block Diagrams
VDD
TLA2024
Voltage
Reference
Mux
AIN0
ADDR
I2C
Interface
12-Bit
û¯ ADC
PGA
AIN1
SCL
SDA
AIN2
AIN3
Oscillator
GND
Copyright © 2017, Texas Instruments Incorporated
图 5. TLA2024 Block Diagram
VDD
VDD
TLA2022
TLA2021
Voltage
Voltage
Reference
Reference
ADDR
AIN0
AIN1
ADDR
SCL
I2C
Interface
12-Bit
û¯ ADC
AIN0
SCL
PGA
I2C
Interface
12-Bit
û¯ ADC
SDA
AIN1
SDA
Oscillator
Oscillator
GND
Copyright © 2017, Texas Instruments Incorporated
GND
Copyright © 2017, Texas Instruments Incorporated
图 6. TLA2022 Block Diagram
图 7. TLA2021 Block Diagram
8
版权 © 2017, Texas Instruments Incorporated
TLA2021, TLA2022, TLA2024
www.ti.com.cn
ZHCSH32 –NOVEMBER 2017
8.3 Feature Description
8.3.1 Multiplexer
图 8 shows that the TLA2024 contains an analog input multiplexer (MUX). Four single-ended or two differential
signals can be measured. Additionally, AIN0 and AIN1 can be measured differentially to AIN3. The multiplexer is
configured by bits MUX[2:0] in the configuration register. When single-ended signals are measured, the negative
input of the ADC is internally connected to GND by a switch within the multiplexer.
TLA2024
VDD
AIN0
VDD
GND
VDD
AIN
AIN
P
AIN1
AIN2
AIN3
N
GND
VDD
GND
GND
GND
Copyright © 2017, Texas Instruments Incorporated
图 8. Input Multiplexer
The TLA2021 and TLA2022 do not have an input multiplexer and can either measure one differential signal or
one single-ended signal. For single-ended measurements, connect the AIN1 pin to GND externally. In
subsequent sections of this data sheet, AINP refers to AIN0 and AINN refers to AIN1 for the TLA2021 and
TLA2022.
Electrostatic discharge (ESD) diodes connected to VDD and GND protect the TLA202x analog inputs. Keep the
absolute voltage on any input within the range shown in 公式 1 to prevent the ESD diodes from turning on.
GND – 0.3 V < V(AINX) < VDD + 0.3 V
(1)
If the voltages on the analog input pins can potentially violate these conditions, use external Schottky diodes and
series resistors to limit the input current to safe values (see the Absolute Maximum Ratings table).
版权 © 2017, Texas Instruments Incorporated
9
TLA2021, TLA2022, TLA2024
ZHCSH32 –NOVEMBER 2017
www.ti.com.cn
Feature Description (接下页)
8.3.2 Analog Inputs
The TLA202x use a switched-capacitor input stage where capacitors are continuously charged and then
discharged to measure the voltage between AINP and AINN. The frequency at which the input signal is sampled
is referred to as the sampling frequency or the modulator frequency (fMOD). The TLA202x have a 1-MHz internal
oscillator that is further divided by a factor of 4 to generate fMOD at 250 kHz. The capacitors used in this input
stage are small, and to external circuitry, the average loading appears resistive. 图 9 shows this structure. The
capacitor values set the resistance and switching rate. 图 10 shows the timing for the switches in 图 9. During the
sampling phase, switches S1 are closed. This event charges CA1 to VAINP, CA2 to VAINN, and CB to (VAINP – VAINN).
During the discharge phase, S1 is first opened and then S2 is closed. CA1 and CA2 then discharge to
approximately 0.7 V and CB discharges to 0 V. This charging draws a very small transient current from the
source driving the TLA202x analog inputs. The average value of this current can be used to calculate the
effective impedance (Zeff), where Zeff = VIN / IAVERAGE
.
0.7 V
C
A1
Z
Z
CM
Equivalent
Circuit
0.7 V
0.7 V
AIN
P
S2
S2
AIN
AIN
S
P
1
C
B
DIFF
S
1
N
AIN
N
Z
CM
f
= 250 kHz
MOD
C
A2
0.7 V
图 9. Simplified Analog Input Circuit
tSAMPLE
ON
S1
OFF
ON
S2
OFF
图 10. S1 and S2 Switch Timing
The common-mode input impedance is measured by applying a common-mode signal to the shorted AINP and
AINN inputs and measuring the average current consumed by each pin. The common-mode input impedance
changes depending on the full-scale range, but is approximately 6 MΩ for the default full-scale range. In 图 9, the
common-mode input impedance is ZCM
.
The differential input impedance is measured by applying a differential signal to the AINP and AINN inputs where
one input is held at 0.7 V. The current that flows through the pin connected to 0.7 V is the differential current and
scales with the full-scale range. In 图 9, the differential input impedance is ZDIFF
.
Consider the typical value of the input impedance. Unless the input source has a low impedance, the TLA202x
input impedance may affect the measurement accuracy. For sources with high-output impedance, buffering may
be necessary. Active buffers introduce noise, offset, and gain errors. Consider all of these factors in high-
accuracy applications.
The clock oscillator frequency drifts slightly with temperature; therefore, the input impedances also drift. For most
applications, this input impedance drift is negligible and can be ignored.
10
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TLA2021, TLA2022, TLA2024
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Feature Description (接下页)
8.3.3 Full-Scale Range (FSR) and LSB Size
A programmable gain amplifier (PGA) is implemented before the ΔΣ ADC of the TLA2022 and TLA2024. The full-
scale range is configured by bits PGA[2:0] in the configuration register and can be set to ±6.144 V, ±4.096 V,
±2.048 V, ±1.024 V, ±0.512 V, or ±0.256 V. 表 1 shows the FSR together with the corresponding LSB size. 公式
2 shows how to calculate the LSB size from the selected full-scale range.
LSB = FSR / 212
(2)
表 1. Full-Scale Range and Corresponding LSB Size
FSR
LSB SIZE
3 mV
±6.144 V(1)
±4.096 V(1)
±2.048 V
±1.024 V
±0.512 V
±0.256 V
2 mV
1 mV
0.5 mV
0.25 mV
0.125 mV
(1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to this device.
The FSR of the TLA2021 is fixed at ±2.048 V.
Analog input voltages must never exceed the analog input voltage limits given in the Absolute Maximum Ratings
table. If a VDD supply voltage greater than 4 V is used, the ±6.144-V full-scale range allows input voltages to
extend up to the supply. Although in this case (or whenever the supply voltage is less than the full-scale range) a
full-scale ADC output code cannot be obtained. For example, with VDD = 3.3 V and FSR = ±4.096 V, only
signals up to VIN = ±3.3 V can be measured. The code range that represents voltages |VIN| > 3.3 V is not used in
this case.
8.3.4 Voltage Reference
The TLA202x have an integrated voltage reference. An external reference cannot be used with these devices.
Errors associated with the initial voltage reference accuracy and the reference drift with temperature are included
in the gain error and gain drift specifications in the Electrical Characteristics table.
8.3.5 Oscillator
The TLA202x have an integrated oscillator running at 1 MHz. No external clock can be applied to operate these
devices. The internal oscillator drifts over temperature and time. The output data rate scales proportionally with
the oscillator frequency.
8.3.6 Output Data Rate and Conversion Time
The TLA202x offer programmable output data rates. Use the DR[2:0] bits in the configuration register to select
output data rates of 128 SPS, 250 SPS, 490 SPS, 920 SPS, 1600 SPS, 2400 SPS, or 3300 SPS.
Conversions in the TLA202x settle within a single cycle, which means the conversion time equals 1 / DR.
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8.4 Device Functional Modes
8.4.1 Reset and Power-Up
The TLA202x reset on power-up and set all bits in the configuration register to the respective default settings.
The TLA202x enter a power-down state after completion of the reset process. The device interface and digital
blocks are active, but no data conversions are performed. The initial power-down state of the TLA202x relieves
systems with tight power-supply requirements from encountering a surge during power-up.
The TLA202x respond to the I2C general-call reset command. When the TLA202x receive a general-call reset
command (06h), an internal reset is performed as if the device is powered up.
8.4.2 Operating Modes
The TLA202x operate in one of two modes: continuous-conversion or single-shot. The MODE bit in the
configuration register selects the respective operating mode.
8.4.2.1 Single-Shot Conversion Mode
When the MODE bit in the configuration register is set to 1, the TLA202x enter a power-down state, and operate
in single-shot conversion mode. This power-down state is the default state for the TLA202x when power is first
applied. Although powered down, the devices respond to commands. The TLA202x remain in this power-down
state until a 1 is written to the operational status (OS) bit in the configuration register. When the OS bit is
asserted, the device powers up in approximately 25 µs, resets the OS bit to 0, and starts a single conversion.
When conversion data are ready for retrieval, the OS bit is set to 1 and the device powers down again. Writing a
1 to the OS bit while a conversion is ongoing has no effect. To switch to continuous-conversion mode, write a 0
to the MODE bit in the configuration register.
8.4.2.2 Continuous-Conversion Mode
In continuous-conversion mode (MODE bit set to 0), the TLA202x perform conversions continuously. When a
conversion is complete, the TLA202x place the result in the conversion data register and immediately begin
another conversion. When writing new configuration settings, the currently ongoing conversion completes with
the previous configuration settings. Thereafter, continuous conversions with the new configuration settings start.
To switch to single-shot conversion mode, write a 1 to the MODE bit in the configuration register or reset the
device.
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8.5 Programming
8.5.1 I2C Interface
The TLA202x use an I2C-compatible (inter-integrated circuit) interface for serial communication. I2C is a 2-wire,
open-drain communication interface that allows communication of a master device with multiple slave devices on
the same bus through the use of device addressing. Each slave device on an I2C bus must have a unique
address. Communication on the I2C bus always takes place between two devices: one acting as the master and
the other as the slave. Both the master and slave can receive and transmit data, but the slave can only read or
write under the direction of the master. The TLA202x always act as I2C slave devices.
An I2C bus consists of two lines: SDA and SCL. SDA carries data and SCL provides the clock. Devices on the
I2C bus drive the bus lines low by connecting the lines to ground; the devices never drive the bus lines high.
Instead, the bus wires are pulled high by pullup resistors; thus, the bus wires are always high when a device is
not driving the lines low. As a result of this configuration, two devices do not conflict. If two devices drive the bus
simultaneously, there is no driver contention.
See the I2C-Bus Specification and User Manual from NXP Semiconductors™ for more details.
8.5.1.1 I2C Address Selection
The TLA202x have one address pin (ADDR) that configures the I2C address of the device. The ADDR pin can
connect to GND, VDD, or SCL (as shown in 表 2), which allows three different addresses to be selected with one
pin. At the start of every transaction, that is between the START condition (first falling edge of SDA) and the first
falling SCL edge of the address byte, the TLA202x decode its address configuration again.
表 2. ADDR Pin Connection and Corresponding Slave Address
ADDR PIN CONNECTION
SLAVE ADDRESS
1001 000
GND
VDD
SCL
1001 001
1001 011
8.5.1.2 I2C Interface Speed
The TLA202x support I2C interface speeds up to 400 kbit/s. Standard-mode (Sm) with bit rates up to 100 kbit/s,
and fast-mode (Fm) with bit rates up to 400 kbit/s are supported. Fast-mode plus (Fm+) and high-speed mode
(Hs-mode) are not supported.
8.5.1.3 Serial Clock (SCL) and Serial Data (SDA)
The serial clock (SCL) line is used to clock data in and out of the device. The master always drives the clock line.
The TLA202x cannot act as a master and as a result can never drive SCL.
The serial data (SDA) line allows for bidirectional communication between the host (the master) and the TLA202x
(the slave). When the master reads from a TLA202x, the TLA202x drives the data line; when the master writes to
a TLA202x, the master drives the data line.
Data on the SDA line must be stable during the high period of the clock. The high or low state of the data line
can only change when the SCL line is low. One clock pulse is generated for each data bit transferred. When in
an idle state, the master should hold SCL high.
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8.5.1.4 I2C Data Transfer Protocol
图 11 shows the format of the data transfer. The master initiates all transactions with the TLA202x by generating
a START (S) condition. A high-to-low transition on the SDA line while SCL is high defines a START condition.
The bus is considered to be busy after the START condition.
Following the START condition, the master sends the 7-bit slave address corresponding to the address of the
TLA202x that the master wants to communicate with. The master then sends an eighth bit that is a data direction
bit (R/W). An R/W bit of 0 indicates a write operation, and an R/W bit of 1 indicates a read operation. After the
R/W bit, the master generates a ninth SCLK pulse and releases the SDA line to allow the TLA202x to
acknowledge (ACK) the reception of the slave address by pulling SDA low. In case the device does not
recognize the slave address, the TLA202x holds SDA high to indicate a not acknowledge (NACK) signal.
Next follows the data transmission. If the transaction is a read (R/W = 1), the TLA202x outputs data on SDA. If
the transaction is a write (R/W = 0), the host outputs data on SDA. Data are transferred byte-wise, most
significant bit (MSB) first. The number of bytes that can be transmitted per transfer is unrestricted. Each byte
must be acknowledged (via the ACK bit) by the receiver. If the transaction is a read, the master issues the ACK.
If the transaction is a write, the TLA202x issues the ACK.
The master terminates all transactions by generating a STOP (P) condition. A low-to-high transition on the SDA
line while SCL is high defines a STOP condition. The bus is considered free again tBUF (bus-free time) after the
STOP condition.
SDA
SCL
A6 œ A0
D7 œ D0
D7 œ D0
1 - 7
8
9
1 - 8
9
1 - 8
9
S
P
START
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
STOP
Condition
from slave
from receiver
from receiver Condition
图 11. I2C Data Transfer Format
8.5.1.5 Timeout
The TLA202x offer a I2C timeout feature that can be used to recover communication when a serial interface
transmission is interrupted. If the host initiates contact with the TLA202x but subsequently remains idle for 25 ms
before completing a command, the TLA202x interface is reset. If the TLA202x interface resets because of a
timeout condition, the host must abort the transaction and restart the communication again by issuing a new
START condition.
8.5.1.6 I2C General-Call (Software Reset)
The TLA202x respond to the I2C general-call address (0000 000) if the R/W bit is 0. The devices acknowledge
the general-call address and, if the next byte is 06h, the TLA202x reset the internal registers and enter a power-
down state.
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8.5.2 Reading and Writing Register Data
The host can read the conversion data register from the TLA202x, or read and write the configuration register
from and to the TLA202x, respectively. The value of the register pointer (RP), which is the first data byte after the
slave address of a write transaction (R/W = 0), determines the register that is addressed. 表 3 shows the
mapping between the register pointer value and the register that is addressed.
Register data are sent with the most significant byte first, followed by the least significant byte. Within each byte,
data are transmitted most significant bit first.
表 3. Register Pointer (RP)
REGISTER POINTER
REGISTER
(Hex)
00h
01h
Conversion data register
Configuration register
8.5.2.1 Reading Conversion Data or the Configuration Register
Read the conversion data register or configuration register as shown in 图 12 by using two I2C communication
frames. The first frame is an I2C write operation where the R/W bit at the end of the slave address is 0 to indicate
a write. In this frame, the host sends the register pointer that points to the register to read from. The second
frame is an I2C read operation where the R/W bit at the end of the slave address is 1 to indicate a read. The
TLA202x transmits the contents of the register in this second I2C frame. The master can terminate the
transmission after any byte by not acknowledging or issuing a START or STOP condition.
When repeatedly reading the same register, the register pointer does not need to be written every time again
because the TLA202x store the value of the register pointer until a write operation modifies the value.
S
S
SLAVE ADDRESS
W
A
REGISTER POINTER
A
P
(1)
A
SLAVE ADDRESS
R
A
REGISTER DATA (MSB)
REGISTER DATA (LSB)
A
P
(1) The master can terminate the transmission after the first byte by not acknowledging.
图 12. Reading Register Data
8.5.2.2 Writing the Configuration Register
Write the configuration register as shown in 图 13 using a single I2C communication frame. The R/W bit at the
end of the salve address is 0 to indicate a write. The host first sends the register pointer that points to the
configuration register, followed by two bytes that represent the register content to write. The TLA202x
acknowledge each received byte.
S
SLAVE ADDRESS
W
A
REGISTER POINTER
A
•••
•••
REGISTER DATA (MSB)
A
REGISTER DATA (LSB)
A
P
图 13. Writing Register Data
图 14 provides a legend for 图 12 and 图 13.
S
P
A
A
= START condition
From master to slave
= STOP condition
= acknowledge (SDA low)
= not acknowledge (SDA high)
From slave to master
图 14. Legend for the I2C Sequence Diagrams
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8.5.3 Data Format
The TLA202x provide 12 bits of data in binary two's-complement format that is left-justified within the 16-bit data
word. A positive full-scale (+FS) input produces an output code of 7FF0h and a negative full-scale (–FS) input
produces an output code of 8000h. The output clips at these codes for signals that exceed full-scale. 表 4
summarizes the ideal output codes for different input signals. 图 15 shows code transitions versus input voltage.
表 4. Input Signal Versus Ideal Output Code
INPUT SIGNAL
VIN = (VAINP – VAINN
)
IDEAL OUTPUT CODE(1)
≥ +FS (211 – 1) / 211
7FF0h
0010h
0000h
FFF0h
8000h
+FS / 211
0
–FS / 211
≤ –FS
(1) Excludes the effects of noise, INL, offset, and gain errors.
7FF0h
7FE0h
0010h
0000h
FFF0h
8010h
8000h
. . .
. . .
-FS
-FS
0
+FS
Input Voltage VIN
211 - 1
211
211 - 1
+FS
211
图 15. Code Transition Diagram
注
Single-ended signal measurements, where VAINN = 0 V and VAINP = 0 V to +FS, only use
the positive code range from 0000h to 7FF0h. However, because of device offset, the
TLA202x can still output negative codes in case VAINP is close to 0 V.
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8.6 Register Maps
The TLA202x have two registers that are accessible through the I2C interface using the register pointer (RP). The
conversion data register contains the result of the last conversion and the configuration register changes the
TLA202x operating modes and queries the status of the device. 表 5 lists the access codes for the TLA202x.
表 5. TLA202x Access Type Codes
Access Type
Code
R
Description
R
Read
R-W
W
R/W
W
Read or write
Write
-n
Value after reset or the default value
8.6.1 Conversion Data Register (RP = 00h) [reset = 0000h]
The 16-bit conversion data register contains the result of the last conversion in binary two's-complement format.
Following power-up, the conversion data register clears to 0, and remains at 0 until the first conversion is
complete.
图 16. Conversion Data Register
15
D11
R-0h
7
14
D10
R-0h
6
13
D9
12
D8
11
D7
10
D6
9
D5
R-0h
1
8
D4
R-0h
0
R-0h
5
R-0h
4
R-0h
3
R-0h
2
D3
D2
D1
D0
RESERVED
R-0h
R-0h
R-0h
R-0h
R-0h
表 6. Conversion Data Register Field Descriptions
Bit
Field
Type
Reset
Description
15:4
3:0
D[11:0]
R
000h
12-bit conversion result
Always reads back 0h
Reserved
R
0h
8.6.2 Configuration Register (RP = 01h) [reset = 8583h]
The 16-bit configuration register controls the operating mode, input selection, data rate, and full-scale range.
图 17. Configuration Register
15
OS
14
13
MUX[2:0]
R/W-0h
5
12
4
11
3
10
9
1
8
PGA[2:0]
R/W-2h
2
MODE
R/W-1h
0
R/W-1h
7
6
DR[2:0]
R/W-4h
RESERVED
R/W-03h
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表 7. Configuration Register Field Descriptions
Bit
Field
Type
Reset
Description
15
OS
R/W
1h
Operational Status or Single-Shot Conversion Start
This bit determines the operational status of the device. OS can only be written
when in a power-down state and has no effect when a conversion is ongoing.
When writing:
0 : No effect
1 : Start a single conversion (when in a power-down state)
When reading:
0 : The device is currently performing a conversion
1 : The device is not currently performing a conversion (default)
14:12
MUX[2:0]
R/W
0h
Input Multiplexer Configuration (TLA2024 only)
These bits configure the input multiplexer.
These bits serve no function on the TLA2021 and TLA2022 and are always set to
000.
000 : AINP = AIN0 and AINN = AIN1 (default)
001 : AINP = AIN0 and AINN = AIN3
010 : AINP = AIN1 and AINN = AIN3
011 : AINP = AIN2 and AINN = AIN3
100 : AINP = AIN0 and AINN = GND
101 : AINP = AIN1 and AINN = GND
110 : AINP = AIN2 and AINN = GND
111 : AINP = AIN3 and AINN = GND
11:9
PGA[2:0]
R/W
2h
Programmable Gain Amplifier Configuration (TLA2022 and TLA2024 Only)
These bits set the FSR of the programmable gain amplifier.
These bits serve no function on the TLA2021 and are always set to 010.
000 : FSR = ±6.144 V(1)
001 : FSR = ±4.096 V(1)
010 : FSR = ±2.048 V (default)
011 : FSR = ±1.024 V
100 : FSR = ±0.512 V
101 : FSR = ±0.256 V
110 : FSR = ±0.256 V
111 : FSR = ±0.256 V
8
MODE
R/W
R/W
1h
4h
Operating Mode
This bit controls the operating mode.
0 : Continuous-conversion mode
1 : Single-shot conversion mode or power-down state (default)
7:5
DR[2:0]
Data Rate
These bits control the data rate setting.
000 : DR = 128 SPS
001 : DR = 250 SPS
010 : DR = 490 SPS
011 : DR = 920 SPS
100 : DR = 1600 SPS (default)
101 : DR = 2400 SPS
110 : DR = 3300 SPS
111 : DR = 3300 SPS
Always write 03h
4:0
Reserved
R/W
03h
(1) This parameter expresses the full-scale range of the ADC scaling. Do not apply more than VDD + 0.3 V to this device.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The following sections give example circuits and suggestions for using the TLA202x in various applications.
9.1.1 Basic Interface Connections
图 18 shows the principle I2C connections for the TLA202x.
VDD
1-kꢀ to 10-kꢀ
Pullup Resistors
10
Device
SCL
SCL
SDA
1
2
3
4
ADDR
NC
SDA
VDD
AIN3
AIN2
9
8
7
6
VDD
Microcontroller or
Microprocessor
With I2C Port
GND
AIN0
0.1 ꢁF
AIN1
5
Copyright © 2017, Texas Instruments Incorporated
图 18. Typical Interface Connections of the TLA202x
The TLA202x interface directly to standard-mode or fast-mode I2C controllers. Any microcontroller I2C peripheral,
including master-only and single-master I2C peripherals, operates with the TLA202x. The TLA202x do not
perform clock-stretching (that is, the devices never pull the clock line low), so this function does not need to be
provided for unless other clock-stretching devices are present on the same I2C bus.
Pullup resistors are required on both the SDA and SCL lines because I2C bus drivers are open-drain. The size of
these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value resistors
yield lower power consumption when the bus lines are pulled low, but increase the transition times on the bus,
which limits the bus speed. Lower-value resistors allow higher interface speeds, but at the expense of higher
power consumption when the bus lines are pulled low. Long bus lines have higher capacitance and require
smaller pullup resistors to compensate. Do not use resistors that are too small because the bus drivers may be
unable to pull the bus lines low.
See the I2C-Bus Specification and User Manual from NXP Semiconductors for more details on pullup resistor
sizing.
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Application Information (接下页)
9.1.2 Connecting Multiple Devices
Up to three TLA202x devices can be connected to a single I2C bus by using different address pin configurations
for each device. Use the address pin to set the TLA202x to one of three different I2C addresses. 图 19 shows an
example with three TLA202x devices on the same I2C bus. One set of pullup resistors is required per bus line.
The pullup resistor values may need to decrease to compensate for the additional bus capacitance presented by
multiple devices and increased line length.
10
Device
SCL
1
2
3
4
ADDR
NC
SDA
VDD
AIN3
AIN2
9
8
7
6
GND
AIN0
VDD
AIN1
5
Microcontroller or
Microprocessor
With I2C Port
1-kꢀ to 10-kꢀ
Pullup Resistors
SCL
SDA
10
VDD
Device
SCL
1
2
3
4
ADDR
NC
SDA
VDD
AIN3
AIN2
9
8
7
6
GND
AIN0
AIN1
5
10
Device
SCL
1
2
3
4
ADDR
NC
SDA
VDD
AIN3
AIN2
9
8
7
6
GND
AIN0
AIN1
5
Copyright © 2017, Texas Instruments Incorporated
NOTE: The TLA202x power and input connections are omitted for clarity. The ADDR pin selects the I2C address.
图 19. Connecting Multiple TLA202x Devices
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Application Information (接下页)
9.1.3 Single-Ended Signal Measurements
The TLA2021 and TLA2022 can measure one single-ended signal, and the TLA2024 up to four single-ended
signals. To measure single-ended signals with the TLA2021 and TLA2022, connect AIN1 to GND externally. The
TLA2024 measures single-ended signals by properly configuring the MUX[2:0] bits (settings 100 to 111) in the
configuration register. 图 20 shows a single-ended connection scheme for the TLA2024 highlighted in red (a
differential connection scheme is shown in green). The single-ended signal range is from 0 V up to the positive
supply or +FS (whichever is lower). Negative voltages cannot be applied to these devices because the TLA202x
can only accept positive voltages with respect to ground. Only the code range from 0000h to 7FF0h (or a subset
thereof in case +FS > VDD) is used in this case.
VDD
TLA2024
CCM
Mux
Voltage
RFLT
Reference
AIN0
AIN1
+
VDIF
CDIF
ADDR
œ
RFLT
I2C
Interface
12-Bit
û¯ ADC
PGA
SCL
SDA
+
CCM
VCM
œ
AIN2
AIN3
Oscillator
RFLT
+
CSE
VSE
œ
GND
Copyright © 2017, Texas Instruments Incorporated
图 20. Filter Implementation for Single-Ended and Differential Signal Measurements
The TLA2024 also allows AIN3 to serve as a common point for measurements by appropriately setting the
MUX[2:0] bits. AIN0, AIN1, and AIN2 can all be measured with respect to AIN3. In this configuration, the usable
voltage and code range, respectively, is increased over the single-ended configuration because negative
differential voltages are allowed when GND < V(AIN3) < VDD. Assume the following settings for example: VDD =
5 V, FSR = ±2.048 V, AINP = AIN0, and AINN = AIN3 = 2.5 V. In this case, the voltage at AIN0 can swing from
V(AIN0) = 2.5 V – 2.048 V to 2.5 V + 2.048 V using the entire full-scale range.
9.1.4 Analog Input Filtering
Analog input filtering serves two purposes:
1. Limits the effect of aliasing during the ADC sampling process
2. Attenuates unwanted noise components outside the bandwidth of interest
In most cases, a first-order resistor capacitor (RC) filter is sufficient to completely eliminate aliasing or to reduce
the effect of aliasing to a level within the noise floor of the sensor. A good starting point for a system design with
the TLA202x is to use a differential RC filter with a cutoff frequency set somewhere between the selected output
data rate and 25 kHz. Make the series resistor values as small as possible to reduce voltage drops across the
resistors caused by the device input currents to a minimum. However, the resistors should be large enough to
limit the current into the analog inputs to less than 10 mA in the event of an overvoltage. Then choose the
differential capacitor value to achieve the target filter cutoff frequency. Common-mode filter capacitors to GND
can be added as well, but should always be at least ten times smaller than the differential filter capacitor.
图 20 shows an example of filtering a differential signal (AIN0, AIN1), and a single-ended signal (AIN3). 公式 3
and 公式 4 show how to calculate the filter cutoff frequencies (fCO) in the differential and single-ended cases,
respectively.
fCO DIF = 1 / (2π · 2 · RFLT · CDIF
)
(3)
(4)
fCO SE = 1 / (2π · RFLT · CSE
)
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Application Information (接下页)
9.1.5 Duty Cycling To Reduce Power Consumption
For applications where power consumption is critical, the TLA202x support duty cycling that yield significant
power savings by periodically requesting high data rate readings at an effectively lower data rate. For example,
an TLA202x in power-down state with a data rate set to 3300 SPS can be operated by a microcontroller that
instructs a single-shot conversion every 7.81 ms (128 SPS). A conversion at 3300 SPS requires approximately
0.3 ms, so the TLA202x enters power-down state for the remaining 7.51 ms. In this configuration, the TLA202x
consume approximately 1/25th the power that is otherwise consumed in continuous-conversion mode. The duty
cycling rate is arbitrary and is defined by the master controller.
9.1.6 I2C Communication Sequence Example
This section provides an example of an I2C communication sequence between a microcontroller (the master) and
a TLA2024 (the slave) configured with a slave address of 1001 000 to start a single-shot conversion and
subsequently read the conversion result.
1. Write the configuration register as shown in 图 21 to configure the device (for example, write MUX[2:0] =
000, PGA[2:0] = 010, MODE = 1, and DR[2:0] = 110) and start a single-shot conversion (OS = 1):
S
SLAVE ADDRESS (1001 000)
W
A
REGISTER POINTER (01h)
A
P
•••
•••
CONFIGURATION DATA (85h)
A
CONFIGURATION DATA (C0h)
A
图 21. Write the Configuration Register
2. Wait at least t = 1 / DR ± 10% for the conversion to complete.
Alternatively, poll the OS bit for a 1 as shown in 图 22 to determine when the conversion result is ready for
retrieval. This option does not work in continuous-conversion mode because the OS bit always reads 0.
•••
S
SLAVE ADDRESS (1001 000)
R
A
CONFIGURATION DATA (MSB)
A
CONFIGURATION DATA (LSB)
A
P
图 22. Read the Configuration Register to Check for OS = 1
3. Then, as shown in 图 23, read the conversion data register:
S
SLAVE ADDRESS (1001 000)
W
A
REGISTER POINTER (00h)
A
P
S
SLAVE ADDRESS (1001 000)
R
A
CONVERSION DATA (MSB)
A
CONVERSION DATA (LSB)
A
P
图 23. Read the Conversion Data Register
4. Start a new single-shot conversion by writing a 1 to the OS bit in the configuration register.
To save time, a new conversion can also be started (step 4) before reading the conversion result (step 3). 图
24 lists a legend for 图 21 to 图 23.
S
P
A
A
= START condition
From master to slave
= STOP condition
= acknowledge (SDA low)
= not acknowledge (SDA high)
From slave to master
图 24. Legend for the I2C Sequence Diagrams
22
版权 © 2017, Texas Instruments Incorporated
TLA2021, TLA2022, TLA2024
www.ti.com.cn
ZHCSH32 –NOVEMBER 2017
9.2 Typical Application
This application example describes how to use the TLA2024 to monitor two different supply voltage rails in a
system. 图 25 shows a typical implementation for monitoring two supply voltage rails.
3.3 V
0.1 ꢀF
3.3 V
VDD
3.3 V
1-kꢁ to 10-kꢁ
Pullup Resistors
100 ꢁ
Voltage
Reference
AIN0
SCL
0.47 ꢀF
I2C Bus
AIN1
AIN2
12-Bit
û¯
ADC
I2C
Interface
SDA
Mux
PGA
1.8 V
ADDR
100 ꢁ
Oscillator
AIN3
0.47 ꢀF
TLA2024
GND
Copyright © 2017, Texas Instruments Incorporated
图 25. Monitoring Two Supply Voltage Rails Using the TLA2024
9.2.1 Design Requirements
表 8 lists the design requirements for this application.
表 8. Design Requirements
DESIGN PARAMETER
Device supply voltage
Voltage rails to monitor
Measurement accuracy
Update rate
VALUE
3.3 V
1.8 V, 3.3 V
±0.5%
1 ms per rail
9.2.2 Detailed Design Procedure
The analog inputs, AIN0 and AIN3, connect directly to the supply voltage rails that are monitored through RC
filter resistors. Small filter resistor values of 100 Ω are chosen to reduce voltage drops, and therefore offset
errors, caused by the input currents of the TLA2024 to a minimum. Filter capacitors of 0.47 µF are chosen to set
the filter cutoff frequencies at 3.39 kHz. In order to get one reading from each of the two supplies within 2 ms, a
data rate of 2400 SPS is selected. The device is set up for single-ended measurements using MUX[2:0] settings
100 and 101. A FSR = ±4.096 V is selected to measure the 3.3-V rail. The same FSR can also be used to
measure the 1.8-V rail or the FSR can be set to FSR = ±2.048 V.
版权 © 2017, Texas Instruments Incorporated
23
TLA2021, TLA2022, TLA2024
ZHCSH32 –NOVEMBER 2017
www.ti.com.cn
9.2.3 Application Curve
The measurement results in 图 26 show that the two supplies can be measured with ±0.5% accuracy over the
complete operating ambient temperature range without any offset or gain calibration.
0.1
0.075
0.05
0.025
0
-0.025
-0.05
-0.075
-0.1
3.3 V rail monitor
1.8 V rail monitor
-40
-20
0
20
40
60
80
100
Temperature (èC)
图 26. Measurement Error vs Temperature
10 Power Supply Recommendations
The device requires a single unipolar supply (VDD) to power the analog and digital circuitry of the device.
10.1 Power-Supply Sequencing
Wait approximately 50 µs after VDD is stabilized before communicating with the device to allow the power-up
reset process to complete.
10.2 Power-Supply Decoupling
Good power-supply decoupling is important to achieve optimum performance. As shown in 图 27, VDD must be
decoupled with at least a 0.1-µF capacitor to GND. The 0.1-µF bypass capacitor supplies the momentary bursts
of extra current required from the supply when the device is converting. Place the bypass capacitor as close to
the power-supply pin of the device as possible using low-impedance connections. Use multilayer ceramic chip
capacitors (MLCCs) that offer low equivalent series resistance (ESR) and inductance (ESL) characteristics for
power-supply decoupling purposes. For very sensitive systems, or for systems in harsh noise environments,
avoid using vias to connect the capacitors to the device pins for better noise immunity. The use of multiple vias in
parallel lowers the overall inductance and is beneficial for connections to ground planes.
10
Device
SCL
VDD
1
2
3
4
ADDR
NC
SDA
VDD
AIN3
AIN2
9
8
7
6
GND
AIN0
0.1 ꢀF
AIN1
5
图 27. TLA202x Power-Supply Decoupling
24
版权 © 2017, Texas Instruments Incorporated
TLA2021, TLA2022, TLA2024
www.ti.com.cn
ZHCSH32 –NOVEMBER 2017
11 Layout
11.1 Layout Guidelines
Employ best design practices when laying out a printed-circuit board (PCB) for both analog and digital
components. For optimal performance, separate the analog components such as ADCs, amplifiers, references,
digital-to-analog converters (DACs), and analog MUXs from digital components such as microcontrollers,
complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), radio frequency (RF)
transceivers, universal serial bus (USB) transceivers, and switching regulators. 图 28 shows an example of good
component placement. Although 图 28 provides a good example of component placement, the best placement
for each application is unique to the geometries, components, and PCB fabrication capabilities. That is, there is
no single layout that is perfect for every design and careful consideration must always be used when designing
with any analog component.
Ground Fill or
Ground Plane
Ground Fill or
Ground Plane
Supply
Generation
Signal
Conditioning
(RC Filters
and
Interface
Transceiver
Device
Microcontroller
Connector
or Antenna
Amplifiers)
Ground Fill or
Ground Plane
Ground Fill or
Ground Plane
图 28. System Component Placement
The following points outline some basic recommendations for the layout of the TLA202x to get the best possible
performance of the ADC. A good design can be ruined with a bad circuit layout.
•
Separate the analog and digital signals. To start, partition the board into analog and digital sections where the
layout permits. Route digital lines away from analog lines to prevent digital noise from coupling back into
analog signals.
•
•
Fill void areas on signal layers with ground fill.
Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground
plane is cut or has other traces that block the current from flowing right next to the signal trace, the ground
plane must find another path to return to the source and complete the circuit. If the ground plane is forced into
a larger path, there is an increased chance of signal radiation. Sensitive signals are more susceptible to EMI
interference.
•
•
•
Use bypass capacitors on supplies to minimize high-frequency noise. Do not place vias between bypass
capacitors and the active device. For best results, place the bypass capacitors on the same layer as close as
possible to the active device.
Consider the resistance and inductance of the routing. Input traces often have resistances that react with the
input bias current and cause an added error voltage. Reduce the loop area enclosed by the source signal and
the return current to minimize the inductance in the path.
For best input combinations with differential measurements, use adjacent analog input lines such as AIN0,
AIN1 and AIN2, AIN3. The differential capacitors must be of high quality. The best ceramic chip capacitors
are C0G (NPO) capacitors, which have stable properties and low-noise characteristics.
版权 © 2017, Texas Instruments Incorporated
25
TLA2021, TLA2022, TLA2024
ZHCSH32 –NOVEMBER 2017
www.ti.com.cn
11.2 Layout Example
VDD
AIN3
10
SCL
1
2
3
4
9
8
7
6
ADDR
NC
SDA
VDD
AIN3
AIN2
Device
GND
AIN0
AIN1
5
AIN2
Vias connect to either bottom layer or
an internal plane. The bottom layer or
internal plane are dedicated GND planes
图 29. TLA2024 X2QFN Package
26
版权 © 2017, Texas Instruments Incorporated
TLA2021, TLA2022, TLA2024
www.ti.com.cn
ZHCSH32 –NOVEMBER 2017
12 器件和文档支持
12.1 器件支持
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即购买的快速链接。
表 9. 相关链接
器件
产品文件夹
请单击此处
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
请单击此处
工具和软件
请单击此处
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
请单击此处
TLA2021
TLA2022
TLA2024
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的提醒我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
I2C, NXP Semiconductors are trademarks of NXP Semiconductors.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修
订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。
版权 © 2017, Texas Instruments Incorporated
27
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLA2021IRUGR
TLA2021IRUGT
TLA2022IRUGR
TLA2022IRUGT
TLA2024IRUGR
TLA2024IRUGT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
RUG
RUG
RUG
RUG
RUG
RUG
10
10
10
10
10
10
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
9AZ
9AZ
19J
19J
9IJ
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
9IJ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Aug-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLA2021IRUGR
TLA2021IRUGT
TLA2022IRUGR
TLA2022IRUGT
TLA2024IRUGR
TLA2024IRUGT
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
RUG
RUG
RUG
RUG
RUG
RUG
10
10
10
10
10
10
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
1.75
1.75
1.75
1.75
1.75
1.75
2.25
2.25
2.25
2.25
2.25
2.25
0.65
0.65
0.65
0.65
0.65
0.65
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q1
Q1
Q1
Q1
Q1
Q1
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Aug-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLA2021IRUGR
TLA2021IRUGT
TLA2022IRUGR
TLA2022IRUGT
TLA2024IRUGR
TLA2024IRUGT
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
X2QFN
RUG
RUG
RUG
RUG
RUG
RUG
10
10
10
10
10
10
3000
250
200.0
200.0
200.0
200.0
200.0
200.0
183.0
183.0
183.0
183.0
183.0
183.0
25.0
25.0
25.0
25.0
25.0
25.0
3000
250
3000
250
Pack Materials-Page 2
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