TLC1551IFN [TI]

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS; 10位模拟数字转换器具有并行输出


型号：	TLC1551IFN
厂家：	TEXAS INSTRUMENTS
描述：	10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS 10位模拟数字转换器具有并行输出转换器输出元件
文件：	总9页 (文件大小：141K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLC1550I, TLC1550M, TLC1551I

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH PARALLEL OUTPUTS

SLAS043C – MAY 1991 – REVISED MARCH 1995

†

Power Dissipation . . . 40 mW Max

OR NW PACKAGE

(TOP VIEW)

Advanced LinEPIC Single-Poly Process

Provides Close Capacitor Matching for

Better Accuracy

REF+

REF–

ANLG GND

AIN

CLKIN

Fast Parallel Processing for DSP and µP

Interface

Either External or Internal Clock Can Be

Used

ANLG V

DGTL GND1

DGTL GND2

Conversion Time . . . 6 µs

Total Unadjusted Error . . . ±1 LSB Max

CMOS Technology

DGTL V

DD1

DGTL V

DD2

EOC

description

The TLC1550x and TLC1551 are data acquisition

analog-to-digital converters (ADCs) using a 10-bit,

†

Refer to the mechanical data for the JW

package.

switched-capacitor,

successive-approximation

FK OR FN PACKAGE

(TOP VIEW)

network. A high-speed, 3-state parallel port directly

interfaces to a digital signal processor (DSP) or

microprocessor (µP) system data bus. D0 through

D9 are the digital output terminals with D0 being the

least significant bit (LSB). Separate power

terminals for the analog and digital portions

minimize noise pickup in the supply leads.

Additionally, the digital power is divided into two

parts to separate the lower current logic from the

higher current bus drivers. An external clock can be

applied to CLKIN to override the internal system

clock if desired.

2 1 28 27 26

AIN

ANLG V

DGTL GND1

DGTL GND2

25 CS

24 D9

DGTL V

DD1

DGTL V

DD2

The TLC1550I and TLC1551I are characterized for

operation from –40°C to 85°C. The TLC1550M is

characterized over the full military range of –55°C

to 125°C.

12 13 14 15 16 17 18

NC – No internal connection

AVAILABLE OPTIONS

PACKAGE

CERAMIC CHIP CARRIER PLASTIC CHIP CARRIER

CERAMIC DIP

(J)

PLASTIC DIP

(NW)

(FK)

(FN)

TLC1550IFN

TLC1551IFN

TLC1550INW

–40°C to 85°C

–55°C to 125°C

–

TLC1550MFK

–

TLC1550MJ

–

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These

circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,

Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated

voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device

should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,

preferably either V

or ground.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Advanced LinEPIC is a trademark of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

2–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1550I, TLC1550M, TLC1551I

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH PARALLEL OUTPUTS

SLAS043C – MAY 1991 – REVISED MARCH 1995

functional block diagram

EOC

Successive-

Approximation

D0–D9

Control

Logic

Frequency

Divided by 2

Internal

Clock

DGTL

Comp

DD1

10-Bit

100 kΩ

Capacitor

NOM

DAC and S/H

Clock Detector

CLKIN

REF+

REF–

AIN

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

AIN

C = 60 pF TYP

(equivalent input

capacitance)

5 MΩ TYP

2–2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1550I, TLC1550M, TLC1551I

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH PARALLEL OUTPUTS

SLAS043C – MAY 1991 – REVISED MARCH 1995

Terminal Functions

TERMINAL

DESCRIPTION

†

‡

NAME

ANLG GND

AIN

NO.

Analog ground. The reference point for the voltage applied on terminals ANLG V , AIN, REF+, and REF–.

Analog voltage input. The voltage applied to AIN is converted to the equivalent digital output.

ANLG V

CLKIN

Analog positive power supply voltage. The voltage applied to this terminal is designated V .

DD3

Clock input. CLKIN is used for external clocking instead of using the internal system clock. It usually takes a

few microseconds before the internal clock is disabled. To use the internal clock, CLKIN should be tied high

or left unconnected.

Chip-select. CS must be low for RD or WR to be recognized by the A/D converter.

Data bus output. D0 is bit 1 (LSB).

Data bus output. D1 is bit 2.

Data bus output. D2 is bit 3.

Data bus output. D3 is bit 4.

Data bus output. D4 is bit 5.

Data bus output. D5 is bit 6.

Data bus output. D6 is bit 7.

Data bus output. D7 is bit 8.

Data bus output. D8 is bit 9.

Data bus output. D9 is bit 10 (MSB).

DGTL GND1

DGTL GND2

Digital ground 1. The ground for power supply DGTL V

Digital ground 2. The ground for power supply DGTL V

and is the substrate connection.

DD1

DD2

DGTL V

EOC

Digital positive power-supply voltage 1. DGTL V

supplies the logic. The voltage applied to DGTL V is

DD1

designated V

DD1

Digitalpositivepower-supplyvoltage2.DGTLV

suppliesonlythehigher-currentoutputbuffers.Thevoltage

DD2

applied to DGTL V

DD2

is designated V .

DD2

End-of-conversion. EOC goes low indicating that conversion is complete and the results have been transferred

to the output latch. EOC can be connected to the µP- or DSP-interrupt terminal or can be continuously polled.

Read input. When CS is low and RD is taken low, the data is placed on the data bus from the output latch. The

output latch stores the conversion results at the most recent negative edge of EOC. The falling edge of RD

resets EOC to a high within the t

specifications.

d(EOC)

REF+

Positive voltage-reference input. Any analog input that is greater than or equal to the voltage on REF+ converts

to 1111111111. AnaloginputvoltagesbetweenREF+andREF–converttotheappropriateresultinaratiometric

manner.

REF–

Negative voltage reference input. Any analog input that is less than or equal to the voltage on REF– converts

to 0000000000.

Write input. When CS is low, conversion is started on the rising edge of WR. On this rising edge, the ADC holds

the analog input until conversion is completed. Before and after the conversion period, which is given by t

the ADC remains in the sampling mode.

conv

†

‡

Terminal numbers for FK and FN packages.

Terminal numbers for J and NW packages.

2–3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1550I, TLC1550M, TLC1551I

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH PARALLEL OUTPUTS

SLAS043C – MAY 1991 – REVISED MARCH 1995

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

, V

, and V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V

DD3

DD1 DD2

Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Output voltage range, V

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V

Peak input current (any digital input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA

Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA

Operating free-air temperature range, T : TLC1550I, TLC1551I . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

TLC1550M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

Case temperature for 10 seconds: FK or FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: J or NW package . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1:

isthevoltagemeasuredatDGTLV

with respect to DGND1. V

isthevoltagemeasuredatDGTLV

withrespecttothe

with respect to AGND. For these specifications, all ground terminals are tied

DD1

DGND2. V

DD1

DD2

is the voltage measured at ANLG V

DD3

, and V

together (and represent 0 V). When V

, V

are equal, they are referred to simply as V

DD1 DD2

DD3

recommended operating conditions

MIN

NOM MAX

UNIT

Supply voltage, V

, V

4.75

5.5

DD1 DD2 DD3

Positive reference voltage, V (see Note 2)

DD3

ref+

Negative reference voltage, V

(see Note 2)

ref–

Differential reference voltage, V

– V

ref–

(see Note 2)

0.3

ref+

Analog input voltage range

DD3

High-level control input voltage, V

Low-level control input voltage, V

0.8

7.8

Input clock frequency, f

(CLKIN)

Setup time, CS low before WR or RD goes low, t

0.5

MHz

su(CS)

Hold time, CS low after WR or RD goes high, t

h(CS)

WR or RD pulse duration, t

w(WR)

40% of

period

80% of

period

Input clock low pulse duration, t

wL(CLKIN)

TLC155xI

–40

–55

Operating free-air temperature, T

°C

TLC1550M

125

NOTE 2: Analog input voltages greater than that applied to REF+ convert to all 1s (1111111111), while input voltages less than that applied to

REF– convert to all 0s (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V.

2–4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1550I, TLC1550M, TLC1551I

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH PARALLEL OUTPUTS

SLAS043C – MAY 1991 – REVISED MARCH 1995

electrical characteristics over recommended operating free-air temperature range,

= V

= 4.75 to 5.5 V and V

= 0 (unless otherwise noted)

ref+

ref–

†

TYP

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

High-level output voltage

= 4.75 V,

= –360 µA

= 25°C

2.4

0.4

0.5

= 4.75 V,

= 2.4 mA

Low-level output voltage

= –55°C to 125°C

= V

= 0,

CS and RD at V

Off-state (high-impedance-state) output current

µA

–10

2.5

High-level input current

V = V

I DD

0.005

–2.5 –0.005

µA

Low-level input current (except CLKIN)

Low-level input current (CLKIN)

V = 0

–150

–50

–12

= 5 V,

= 0,

= 25°C

Short-circuit output current

–6

Operating supply current

CS low and RD high

Analog inputs

Input capacitance

90*

15*

See typical equivalent inputs TLC1550/1I

Digital inputs

* On products compliant to MIL-STD-883, Class B, this parameter is not production tested.

†

All typical values are at V

= 5 V, T = 25°C.

2–5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1550I, TLC1550M, TLC1551I

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH PARALLEL OUTPUTS

SLAS043C – MAY 1991 – REVISED MARCH 1995

operating characteristics over recommended operating free-air temperature range with internal

clock and minimum sampling time of 4 µs, V

= V

= 5 V and V

= 0 (unless otherwise noted)

ref+

ref–

†

‡

PARAMETER

TLC1550I

TEST CONDITIONS

MIN TYP

MAX

±0.5

±1

UNIT

Full range

25°C

TLC1551I

Linearity error

Zero-scale error

Full-scale error

See Note 3

LSB

±0.5

±1

TLC1550M

Full range

25°C

TLC1550I

TLC1551I

±0.5

±1

See Notes 2 and 4

LSB

±0.5

±1

TLC1550M

Full range

25°C

TLC1550I

TLC1551I

±0.5

±1

See Notes 2 and 4

See Note 5

±0.5

±1

TLC1550M

Full range

25°C

TLC1550I

TLC1551I

TLC1550M

±0.5

±1

Total unadjusted error

Conversion time

LSB

±1

= 4.2 MHz or

clock(external)

internal clock

µs

conv

Data access time after RD goes low

Data valid time after RD goes high

a(D)

v(D)

See Figure 3

Disable time, delay time from RD high to high

impedance

dis(D)

Delay time, RD low to EOC high

d(EOC)

†

‡

Full range is –40°C to 85°C for the TL155xI devices and –55°C to 125°C for the TLC1550M.

All typical values are at V

= 5 V, T = 25°C.

NOTES: 2. Analog input voltages greater than that applied to REF+ convert to all 1s (1111111111), while input voltages less than that applied

to REF– convert to all 0s (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V.

3. Linearity error is the difference between the actual analog value at the transition between any two adjacent steps and its ideal value

after zero-scale error and full-scale error have been removed.

4. Zero-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified zero scale.

Full-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified full scale.

5. Total unadjusted error is the difference between the actual analog value at the transition between any two adjacent steps and its

ideal value. It includes contributions from zero-scale error, full-scale error, and linearity error.

PARAMETER MEASUREMENT INFORMATION

Source Current = 6 mA

Test Point

See Note A

Output

Under Test

= 1 V

= 62 pF

Sink Current = 6 mA

= voltage commutation point for switching between source and sink currents

NOTE A: Equivalent load circuit of the Teradyne A500 tester for timing parameter measurement

Figure 1. Test Load Circuit

2–6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1550I, TLC1550M, TLC1551I

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH PARALLEL OUTPUTS

SLAS043C – MAY 1991 – REVISED MARCH 1995

APPLICATION INFORMATION

simplified analog input analysis

Using the circuit in Figure 2, the time required to charge the analog input capacitance from 0 to V within 1/2

LSB can be derived as follows:

The capacitance charging voltage is given by

–t R C

(1)

(2)

1–e

where

R = R + r

The final voltage to 1/2 LSB is given by

V (1/2 LSB) = V – (V /1024)

Equating equation 1 to equation 2 and solving for time t gives

–t R C

(3)

(4)

512

1–e

and

t (1/2 LSB) = R × C × ln(1024)

Therefore, with the values given, the time for the analog input signal to settle is

t (1/2 LSB) = (R + 1 kΩ) × 60 pF × ln(1024)

(5)

This time must be less than the converter sample time shown in the timing diagrams.

†

Driving Source

TLC1550/1

1 kΩ MAX

50 pF MAX

= Input voltage at AIN

= External driving source voltage

R = Source resistance

= Input resistance

C = Input capacitance

†

Driving source requirements:

•

Noise and distortion for the source must be equivalent to the

resolution of the converter.

•

R must be real at the input frequency.

Figure 2. Input Circuit Including the Driving Source

2–7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLC1550I, TLC1550M, TLC1551I

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH PARALLEL OUTPUTS

SLAS043C – MAY 1991 – REVISED MARCH 1995

PRINCIPLES OF OPERATION

The operating sequence for complete data acquisition is shown in Figure 3. Processors can address the TLC1550

and TLC1551 as an external memory device by simply connecting the address lines to a decoder and the decoder

output to CS. Like other peripheral devices, the write (WR) and read (RD) input signals are valid only when CS is low.

Once CS is low, the on-board system clock permits the conversion to begin with a simple write command and the

converted data to be presented to the data bus with a simple read command. The device remains in a sampling (track)

mode from the rising edge of EOC until conversion begins with the rising edge of WR, which initiates the hold mode.

After the hold mode begins, the clock controls the conversion automatically. When the conversion is complete, the

end-of-conversion (EOC) signal goes low indicating that the digital data has been transferred to the output latch.

Lowering CS and RD then resets EOC and transfers the data to the data bus for the processor read cycle.

h(CS)

su(CS)

0.8 V

conv

w(WR)

2 V

1.4 V

0.8 V

h(CS)

su(CS)

2 V

0.8 V

v(D)

a(D)

dis(D)

2 V

0.8 V

2 V

0.8 V

D0–D9

EOC

Data Valid

d(EOC)

2 V

0.8 V

Figure 3. TLC1550 or TLC1551 Operating Sequence

2–8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue

any product or service without notice, and advise customers to obtain the latest version of relevant information

to verify, before placing orders, that information being relied on is current and complete. All products are sold

subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those

pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily

performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF

DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL

APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR

WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER

CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO

BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other

intellectual property right of TI covering or relating to any combination, machine, or process in which such

semiconductor products or services might be or are used. TI’s publication of information regarding any third

party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

TLC1551IFN [TI]

相关型号：

TLC1551IFNG4

TLC1551IFNR

TLC1551IJ

TLC1551IN

TLC1551INW

TLC155D

TLC155ED

TLC155EM

TLC155EP

TLC155ER