TLC2652Q-8DG4 [TI]
高精密 1µV 失调电压、斩波稳定型运算放大器 | D | 8;
| 型号： | TLC2652Q-8DG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高精密 1µV 失调电压、斩波稳定型运算放大器 | D | 8 放大器 运算放大器 |
| 文件： | 总39页 (文件大小：869K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢈ
ꢓꢔꢕ ꢂꢖꢒ ꢖꢑ ꢗ ꢂꢘꢑ ꢓꢓ ꢕꢔꢙꢒ ꢀꢇ ꢚꢖ ꢁꢖ ꢛꢕ ꢜ
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SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
D008, JG, OR P PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
D
Extremely Low Offset Voltage . . . 1 µV Max
Extremely Low Change on Offset Voltage
With Temperature . . . 0.003 µV/°C Typ
Low Input Offset Current
C
C
V
1
2
3
4
8
7
6
5
XA
XB
IN−
IN+
DD+
500 pA Max at T = − 55°C to 125°C
A
OUT
A
. . . 135 dB Min
V
CLAMP
VD
DD−
CMRR . . . 120 dB Min
. . . 110 dB Min
D014, J, OR N PACKAGE
(TOP VIEW)
k
SVR
Single-Supply Operation
Common-Mode Input Voltage Range
Includes the Negative Rail
C
C
INT/EXT
CLK IN
1
2
3
4
5
6
7
14
13
12
11
10
9
XB
XA
NC
IN−
IN+
NC
CLK OUT
D
No Noise Degradation With External
V
Capacitors Connected to V
DD+
DD−
OUT
description
CLAMP
C RETURN
V
8
DD−
The TLC2652 and TLC2652A are high-precision
chopper-stabilized operational amplifiers using
Texas Instruments Advanced LinCMOS pro-
cess. This process, in conjunction with unique
chopper-stabilization circuitry, produces opera-
tional amplifiers whose performance matches or
exceeds that of similar devices available today.
FK PACKAGE
(TOP VIEW)
Chopper-stabilization techniques make possible
extremely high dc precision by continuously
nulling input offset voltage even during variations
in temperature, time, common-mode voltage, and
power supply voltage. In addition, low-frequency
noise voltage is significantly reduced. This high
precision, coupled with the extremely high input
impedance of the CMOS input stage, makes the
TLC2652 and TLC2652A an ideal choice for
low-level signal processing applications such as
strain gauges, thermocouples, and other
transducer amplifiers. For applications that
require extremely low noise and higher usable
bandwidth, use the TLC2654 or TLC2654A
device, which has a chopping frequency of
10 kHz.
3
4
2
1
20 19
18
CLK OUT
NC
NC
IN−
NC
IN+
NC
V
17
5
6
7
8
16
15
14
DD+
NC
OUT
9 10 11 12 13
NC − No internal connection
The TLC2652 and TLC2652A input common-mode range includes the negative rail, thereby providing superior
performance in either single-supply or split-supply applications, even at power supply voltage levels as low as
1.9 V.
Two external capacitors are required for operation of the device; however, the on-chip chopper-control circuitry
is transparent to the user. On devices in the 14-pin and 20-pin packages, the control circuitry is made accessible
to allow the user the option of controlling the clock frequency with an external frequency source. In addition, the
clock threshold level of the TLC2652 and TLC2652A requires no level shifting when used in the single-supply
configuration with a normal CMOS or TTL clock input.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments.
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Copyright 1988−2005, Texas Instruments Incorporated
ꢑ ꢌ ꢦ ꢡ ꢠꢉ ꢥꢍ ꢣꢤ ꢍꢠ ꢢꢦ ꢨꢏ ꢋꢌ ꢣ ꢣꢠ ꢐꢖ ꢁꢙ ꢓꢔ ꢝ ꢙꢯꢰꢅ ꢯꢅꢆ ꢋꢨꢨ ꢦꢋ ꢡ ꢋ ꢢꢎ ꢣꢎꢡ ꢤ ꢋ ꢡ ꢎ ꢣꢎ ꢤꢣꢎ ꢉ
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1
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ꢑꢓ ꢕ ꢔꢇꢀ ꢖ ꢑꢗ ꢇ ꢁ ꢇꢐ ꢓꢁ ꢖ ꢝꢖ ꢕ ꢔꢒ
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ꢓ ꢔꢕ ꢂꢖ ꢒꢖ ꢑ ꢗ ꢂꢘ ꢑꢓꢓ ꢕꢔꢙꢒ ꢀꢇꢚꢖ ꢁ ꢖꢛ ꢕꢜ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
description (continued)
Innovative circuit techniques are used on the TLC2652 and TLC2652A to allow exceptionally fast overload
recovery time. If desired, an output clamp pin is available to reduce the recovery time even further.
The device inputs and output are designed to withstand 100-mA surge currents without sustaining latch-up.
Additionally the TLC2652 and TLC2652A incorporate internal ESD-protection circuits that prevent functional
failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be
exercised in handling these devices, as exposure to ESD may result in degradation of the device parametric
performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from −40°C to 85°C. The Q-suffix devices are characterized for operation from −40°C to125°C.
The M-suffix devices are characterized for operation over the full military temperature range of −55°C to125°C.
(1)
AVAILABLE OPTIONS
PACKAGED DEVICES
8 PIN
14 PIN
20 PIN
CHIP
FORM
(Y)
V
max
IO
T
A
SMALL
OUTLINE
(D008)
CERAMIC
DIP
(JG)
PLASTIC
DIP
SMALL
OUTLINE
(D014)
CERAMIC
DIP
PLASTIC
DIP
CHIP
CARRIER
(FK)
AT 25°C
(P)
(J)
(N)
0°C
to
70°C
1 µV
3 µV
TLC2652AC-8D
TLC2652C-8D
—
—
TLC2652ACP TLC2652AC-14D
—
—
TLC2652ACN
TLC2652CN
—
—
TLC2652Y
TLC2652CP
TLC2652C-14D
−40°C
to
85°C
1 µV
3 µV
TLC2652AI-8D
TLC2652A-8D
—
—
TLC2652AIP
TLC2652IP
TLC2652AI-14D
TLC2652I-14D
—
—
TLC2652AIN
TLC2652IN
—
—
—
—
—
−40°C
to
125°C
3.5 µV
TLC2652Q-8D
—
—
—
—
—
—
−55°C
to
125°C
3 µV
3.5 µV
TLC2652AM-8D TLC2652AMJG TLC2652AMP TLC2652AM-14D TLC2652AMJ TLC2652AMN TLC2652AMFK
TLC2652M-8D TLC2652MJG TLC2652MP TLC2652M-14D TLC2652MJ TLC2652MN TLC2652MFK
The D008 and D014 packages are available taped and reeled. Add R suffix to the device type (e.g., TLC2652AC-8DR). Chips are tested at 25°C.
NOTE (1): For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
functional block diagram
DISTRIBUTION OF TLC2652
INPUT OFFSET VOLTAGE
V
DD+
7
36
32
150 Units Tested From 1 Wafer Lot
5 V
= 25°C
5
6
Clamp
Circuit
V
=
DD
CLAMP
OUT
T
A
3
2
IN+
IN−
28
24
N Package
+
−
C
IC A
Main
B
B
A
20
16
12
8
+
−
Compensation-
Biasing
A
B
Circuit
Null
External Components
C
C
XA
XB
4
8
4
0
C RETURN
V
DD−
−3
−2
V
−1
0
1
2
3
− Input Offset Voltage − µV
Pin numbers shown are for the D (14 pin), JG, and N packages.
IO
2
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ꢓꢔꢕ ꢂꢖꢒ ꢖꢑ ꢗ ꢂꢘꢑ ꢓꢓ ꢕꢔꢙꢒ ꢀꢇ ꢚꢖ ꢁꢖ ꢛꢕ ꢜ
ꢑ ꢓꢕꢔ ꢇꢀ ꢖꢑ ꢗꢇꢁ ꢇꢐꢓ ꢁꢖ ꢝ ꢖꢕ ꢔꢒ
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SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
TLC2652Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC2652C. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(13)
(14)
(12)
(11)
(10)
(9)
(8)
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
T max = 150°C
J
80
TOLERANCES ARE 10%.
ALL DIMENSIONS ARE IN MILS.
(1)
PIN (7) IS INTERNALLY CONNECTED
TO BACK SIDE OF CHIP.
FOR THE PINOUT, SEE THE FUNCTIONAL
BLOCK DIAGRAM.
(2)
(4)
(5)
(7)
90
3
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SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage V
Supply voltage V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −8 V
DD+
DD−
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
ID
Input voltage, V (any input, see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
I
Voltage range on CLK IN and INT/EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
− to V
+ 5.2 V
DD
DD−
Input current, I (each input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
Duration of short-circuit current at (or below) 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Current into CLK IN and INT/EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Q suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
M suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or P package . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or JG package . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between V
and V .
DD+
DD−
2. Differential voltages are at IN+ with respect to IN−.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING POWER RATING
A
D008
D014
FK
J
725 mV
5.8 mW/°C
7.6 mW/°C
11.0 mW/°C
11.0 mW/°C
8.4 mW/°C
12.6 mW/°C
8.0 mW/°C
464 mW
608 mW
880 mW
880 mW
672 mW
1008 mW
640 mW
377 mW
494 mW
715 mW
715 mW
546 mW
819 mW
520 mW
145 mW
190 mW
275 mW
275 mW
210 mW
315 mW
200 mW
950 mV
1375 mV
1375 mV
1050 mV
1575 mV
1000 mV
JG
N
P
recommended operating conditions
C SUFFIX
I SUFFIX
Q SUFFIX
M SUFFIX
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Supply voltage, V
DD
1.9
8
1.9
8
1.9
8
1.9
8
V
V
Common-mode input voltage, V
V
V
V
−1.9
V
V
V
−1.9
V
V
V
−1.9
V
V
V
−1.9
IC
DD−
DD+
DD−
DD+
DD−
DD+
DD−
DD+
Clock input voltage
V
+5
V
+5
V
+5
V
+5
V
DD−
0
DD−
70
DD−
−40
DD−
85
DD−
−40
DD−
125
DD−
−55
DD−
125
Operating free-air temperature, T
°C
A
4
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SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLC2652C
MIN TYP MAX
TLC2652AC
MIN TYP MAX
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
25°C
0.6
3
0.5
1
V
IO
Input offset voltage
µV
Full range
4.35
2.35
Temperature coefficient of
input offset voltage
α
Full range
0.003
0.03
0.06
0.003
0.03 µV/°C
VIO
Input offset voltage long-term
drift (see Note 4)
25°C
0.003
2
0.003
2
0.02 µV/mo
V
IC
= 0,
R = 50 Ω
S
25°C
Full range
25°C
60
100
60
60
I
I
Input offset current
Input bias current
pA
IO
100
4
4
60
pA
IB
Full range
100
100
−5
to
3.1
−5
to
3.1
Common-mode input voltage
range
V
R
= 50 Ω
Full range
V
ICR
S
25°C
Full range
25°C
4.7
4.7
4.8
4.7
4.7
4.8
Maximum positive peak
output voltage swing
V
V
R
R
= 10 kΩ,
= 10 kΩ,
See Note 5
See Note 5
V
V
OM+
L
L
−4.7 −4.9
−4.7
−4.7 −4.9
−4.7
Maximum negative peak
output voltage swing
OM−
Full range
25°C
120
120
150
135
130
150
Large-signal differential
voltage amplification
A
VD
V
O
=
4 V,
R
= 10 kΩ
dB
Hz
L
Full range
25°C
f
ch
Internal chopping frequency
Clamp on-state current
450
450
25°C
25
25
25
25
R
= 100 kΩ
µA
L
Full range
25°C
100
100
100
Clamp off-state current
V
V
= −4 V to 4 V
pA
O
Full range
25°C
100
120
120
110
110
140
135
1.5
120
120
110
110
140
135
1.5
Common-mode rejection
ratio
= 0,
= 50 Ω
V
= V
min,
O
IC
ICR
CMRR
dB
dB
R
Full range
25°C
S
V
V
= 1.9 V to 8 V,
Supply-voltage rejection ratio
DD
k
SVR
(∆V
DD
/∆V )
IO
= 0,
R
= 50 Ω Full range
25°C
O
S
2.4
2.5
2.4
mA
2.5
I
Supply current
DD
Full range
†
Full range is 0° to 70°C.
NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated
A
at T = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
5. Output clamp is not connected.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢃ ꢈ
ꢖ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢑꢓ ꢕ ꢔꢇꢀ ꢖ ꢑꢗ ꢇ ꢁ ꢇꢐ ꢓꢁ ꢖ ꢝꢖ ꢕ ꢔꢒ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢂ
ꢐ
ꢑ
ꢒ
ꢓ
ꢔ
ꢕ
ꢂ
ꢒꢖ
ꢑ
ꢗ
ꢂ
ꢘ
ꢑ
ꢓ
ꢓ
ꢕ
ꢔ
ꢙ
ꢒ
ꢀꢇ
ꢚ
ꢖ
ꢁ
ꢖ
ꢛ
ꢕ
ꢜ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
operating characteristics specified free-air temperature, V
= 5 V
DD
TLC2652C
TLC2652AC
TEST
CONDITIONS
†
PARAMETER
T
A
UNIT
V/µs
MIN
TYP
MAX
MIN
TYP
MAX
25°C
Full range
25°C
2
1.5
2.3
1.8
2.8
2
1.5
2.3
1.8
2.8
SR+
SR−
Positive slew rate at unity gain
Negative slew rate at unity gain
V
R
C
= 2.3 V,
= 10 kΩ,
= 100 pF
O
L
L
3.1
3.1
V/µs
Full range
25°C
f = 10 Hz
94
23
94
23
140
35
Equivalent input noise voltage
(see Note 6)
nV/√Hz
V
V
n
f = 1 kHz
25°C
f = 0 to 1 Hz
f = 0 to 10 Hz
f = 10 kHz
f = 10 kHz,
25°C
0.8
0.8
Peak-to-peak equivalent input
noise voltage
µV
N(PP)
25°C
2.8
2.8
I
n
Equivalent input noise current
25°C
0.004
0.004
fA/√Hz
R
C
= 10 kΩ,
Gain-bandwidth product
25°C
25°C
1.9
1.9
MHz
L
L
= 100 pF
R
C
= 10 kΩ,
= 100 pF
L
L
Phase margin at unity gain
48°
48°
φm
†
Full range is 0° to 70°C.
NOTE 6: This parameter is tested on a sample basis for the TLC2652A. For other test requirements, please contact the factory. This statement
has no bearing on testing or nontesting of other parameters.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢈ
ꢓꢔꢕ ꢂꢖꢒ ꢖꢑ ꢗ ꢂꢘꢑ ꢓꢓ ꢕꢔꢙꢒ ꢀꢇ ꢚꢖ ꢁꢖ ꢛꢕ ꢜ
ꢑ ꢓꢕꢔ ꢇꢀ ꢖꢑ ꢗꢇꢁ ꢇꢐꢓ ꢁꢖ ꢝ ꢖꢕ ꢔꢒ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢂ
ꢐ
ꢑ
ꢒ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLC2652I
TYP
TLC2652AI
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
MAX
3
MIN
TYP
MAX
1
25°C
0.6
0.5
V
IO
Input offset voltage
µV
Full range
4.95
2.95
Temperature coefficient of
input offset voltage
α
Full range
0.003
0.03
0.06
0.003
0.03 µV/°C
VIO
Input offset voltage
long-term drift (see Note 4)
25°C
0.003
2
0.003
2
0.02 µV/mo
V
IC
= 0,
R = 50 Ω
S
25°C
Full range
25°C
60
150
60
60
I
I
Input offset current
Input bias current
pA
IO
150
4
4
60
pA
IB
Full range
150
150
−5
to
3.1
−5
to
3.1
Common-mode input
voltage range
V
R
= 50 Ω
Full range
V
ICR
S
25°C
Full range
25°C
4.7
4.7
4.8
−4.9
150
4.7
4.7
4.8
−4.9
150
Maximum positive peak
output voltage swing
V
V
R
R
= 10 kΩ, See Note 5
= 10 kΩ, See Note 5
V
V
OM+
L
L
−4.7
−4.7
120
120
−4.7
−4.7
135
125
Maximum negative peak
output voltage swing
OM−
Full range
25°C
Large-signal differential
voltage amplification
A
VD
V
O
=
4 V,
R = 10 kΩ
L
dB
Hz
Full range
25°C
Internal chopping frequency
Clamp on-state current
450
450
25°C
25
25
25
25
R
= 100 kΩ
µA
L
Full range
25°C
100
100
100
Clamp off-state current
V
V
= −4 V to 4 V
pA
O
Full range
25°C
100
120
120
110
110
140
135
1.5
120
120
110
110
140
135
1.5
Common-mode rejection
ratio
= 0,
= 50 Ω
V
= V min,
ICR
O
IC
CMRR
dB
dB
R
Full range
25°C
S
V
V
=
1.9 V to 8 V,
= 50 Ω
Supply-voltage rejection
DD
k
SVR
ratio (∆V
DD
/∆V )
IO
= 0,
R
Full range
25°C
O
O
S
2.4
2.5
2.4
mA
2.5
I
Supply current
V
= 0,
No load
DD
Full range
†
Full range is −40° to 85°C.
NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated
A
at T = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
A
5. Output clamp is not connected.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢃ ꢈ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢑꢓ ꢕ ꢔꢇꢀ ꢖ ꢑꢗ ꢇ ꢁ ꢇꢐ ꢓꢁ ꢖ ꢝꢖ ꢕ ꢔꢒ
ꢂ
ꢐ
ꢑ
ꢒ
ꢓ ꢔꢕ ꢂꢖ ꢒꢖ ꢑ ꢗ ꢂꢘ ꢑꢓꢓ ꢕꢔꢙꢒ ꢀꢇꢚꢖ ꢁ ꢖꢛ ꢕꢜ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
operating characteristics at specified free-air temperature, V
= 5 V
DD
TLC2652I
TYP
TLC2652AI
TEST
CONDITIONS
†
PARAMETER
T
A
UNIT
V/µs
MIN
2
MAX
MIN
TYP
MAX
25°C
Full range
25°C
2.8
2
1.4
2.3
1.7
2.8
SR+
SR−
Positive slew rate at unity gain
Negative slew rate at unity gain
V
R
C
= 2.3 V,
= 10 kΩ,
= 100 pF
O
L
L
1.4
2.3
1.7
3.1
3.1
V/µs
Full range
25°C
f = 10 Hz
94
23
94
23
140
35
Equivalent input noise voltage
(see Note 6)
nV/√Hz
V
V
n
f = 1 kHz
25°C
f = 0 to 1 Hz
f = 0 to 10 Hz
f = 1 kHz
25°C
0.8
0.8
Peak-to-peak equivalent input
noise voltage
µV
N(PP)
25°C
2.8
2.8
I
n
Equivalent input noise current
25°C
0.004
0.004
pA/√Hz
f = 10 kHz,
R
C
= 10 kΩ,
Gain-bandwidth product
25°C
25°C
1.9
1.9
MHz
L
L
= 100 pF
R
C
= 10 kΩ,
= 100 pF
L
L
Phase margin at unity gain
48°
48°
φm
†
Full range is −40° to 85°C.
NOTE 6: This parameter is tested on a sample basis for the TLC2652A. For other test requirements, please contact the factory. This statement
has no bearing on testing or nontesting of other parameters.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢈ
ꢓꢔꢕ ꢂꢖꢒ ꢖꢑ ꢗ ꢂꢘꢑ ꢓꢓ ꢕꢔꢙꢒ ꢀꢇ ꢚꢖ ꢁꢖ ꢛꢕ ꢜ
ꢑ ꢓꢕꢔ ꢇꢀ ꢖꢑ ꢗꢇꢁ ꢇꢐꢓ ꢁꢖ ꢝ ꢖꢕ ꢔꢒ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢂ
ꢐ
ꢑ
ꢒ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLC2652Q
TLC2652M
TLC2652AM
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX
3.5
MIN
TYP
MAX
25°C
0.6
0.5
3
8
Input offset voltage
(see Note 7)
V
IO
µV
Full range
10
Temperature coefficient of
input offset voltage
∗
∗
α
VIO
Full range
0.003 0.03
0.003 0.06
0.003 0.03
0.003 0.02
µV/°C
Input offset voltage
long-term drift (see Note 4)
∗
∗
25°C
µV/mo
V
IC
= 0,
R = 50 Ω
S
25°C
Full range
25°C
2
4
60
500
60
2
4
60
500
60
I
I
Input offset current
Input bias current
pA
pA
IO
IB
Full range
500
500
−5
to
3.1
−5
to
3.1
Common-mode input
voltage range
V
ICR
R
= 50 Ω
Full range
V
S
25°C
Full range
25°C
4.7
4.7
4.8
−4.9
150
4.7
4.7
4.8
−4.9
150
Maximum positive peak
output voltage swing
V
V
R
R
= 10 kΩ, See Note 5
= 10 kΩ, See Note 5
V
V
OM+
L
L
−4.7
−4.7
120
120
−4.7
−4.7
135
120
Maximum negative peak
output voltage swing
OM−
Full range
25°C
Large-signal differential
voltage amplification
A
VD
V
O
=
4 V,
R = 10 kΩ
L
dB
Hz
Full range
25°C
f
ch
Internal chopping frequency
Clamp on-state current
450
450
25°C
25
25
25
25
V
O
= −5 V to 5 V
µA
pA
dB
dB
mA
Full range
25°C
100
500
100
500
Clamp off-state current
R
= 100 kΩ
L
Full range
25°C
120
120
110
110
140
135
1.5
120
120
110
110
140
135
1.5
Common-mode rejection
ratio
V
R
= 0,
= 50 Ω
V
= V min,
ICR
O
IC
CMRR
Full range
25°C
S
V
V
=
1.9 V to 8 V,
= 50 Ω
Supply-voltage rejection
DD
k
SVR
ratio (∆V
DD
/∆V )
IO
= 0,
R
Full range
25°C
O
O
S
2.4
2.5
2.4
2.5
I
Supply current
V
= 0,
No load
DD
Full range
∗
†
On products compliant to MIL-PRF-38535, this parameter is not production tested.
Full range is −40° to 125°C for Q suffix, −55° to 125°C for M suffix.
NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated
A
at T = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
5. Output clamp is not connected.
A
7. This parameter is not production tested. Thermocouple effects preclude measurement of the actual V
of these devices in high
IO
speed automated testing. V is measured to a limit determined by the test equipment capability at the temperature extremes. The
IO
test ensures that the stabilization circuitry is performing properly.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢃ ꢈ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢑꢓ ꢕ ꢔꢇꢀ ꢖ ꢑꢗ ꢇ ꢁ ꢇꢐ ꢓꢁ ꢖ ꢝꢖ ꢕ ꢔꢒ
ꢂ
ꢐ
ꢑ
ꢒ
ꢓ ꢔꢕ ꢂꢖ ꢒꢖ ꢑ ꢗ ꢂꢘ ꢑꢓꢓ ꢕꢔꢙꢒ ꢀꢇꢚꢖ ꢁ ꢖꢛ ꢕꢜ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
operating characteristics at specified free-air temperature, V
= 5 V
DD
TLC2652Q
TLC2652M
TLC2652AM
†
T
PARAMETER
TEST CONDITIONS
UNIT
A
MIN
TYP
MAX
25°C
Full range
25°C
2
1.3
2.3
1.6
2.8
SR+
SR−
Positive slew rate at unity gain
Negative slew rate at unity gain
Equivalent input noise voltage
V/µs
V/µs
V
R
C
= 2.3 V,
= 10 kΩ,
= 100 pF
O
L
L
3.1
Full range
25°C
f = 10 Hz
94
23
nV/√Hz
V
V
n
f = 1 kHz
25°C
f = 0 to 1 Hz
f = 0 to 10 Hz
f = 1 kHz
25°C
0.8
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
µV
N(PP)
25°C
2.8
I
n
25°C
0.004
pA/√Hz
f = 10 kHz,
Gain-bandwidth product
R
C
= 10 kΩ,
25°C
25°C
1.9
MHz
L
L
= 100 pF
R
C
= 10 kΩ,
= 100 pF
L
L
φ
m
Phase margin at unity gain
48°
†
Full range is −40° to 125°C for the Q suffix, −55° to 125°C for the M suffix.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢈ
ꢓꢔꢕ ꢂꢖꢒ ꢖꢑ ꢗ ꢂꢘꢑ ꢓꢓ ꢕꢔꢙꢒ ꢀꢇ ꢚꢖ ꢁꢖ ꢛꢕ ꢜ
ꢑ ꢓꢕꢔ ꢇꢀ ꢖꢑ ꢗꢇꢁ ꢇꢐꢓ ꢁꢖ ꢝ ꢖꢕ ꢔꢒ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢂ
ꢐ
ꢑ
ꢒ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
electrical characteristics at V
= 5 V, T = 25°C (unless otherwise noted)
DD
A
TLC2652Y
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
V
IO
Input offset voltage
0.6
3
µV
Input offset voltage long-term drift (see Note 4)
Input offset current
0.003 0.006 µV/mo
V
IC
= 0,
R = 50 Ω
S
I
I
2
4
60
60
pA
pA
IO
Input bias current
IB
−5
to
3.1
V
ICR
Common-mode input voltage range
R
= 50 Ω
V
S
V
V
Maximum positive peak output voltage swing
Maximum negative peak output voltage swing
Large-signal differential voltage amplification
Internal chopping frequency
R
R
= 10 kΩ,
= 10 kΩ,
See Note 5
See Note 5
4.7
−4.7
120
4.8
−4.9
150
V
OM+
L
L
V
OM−
A
VD
V
O
=
4 V,
R
= 10 kΩ
dB
Hz
µA
pA
L
f
ch
450
Clamp on-state current
R
= 100 kΩ
25
L
Clamp off-state current
V
O
= −4 V to 4 V
100
2.4
V
R
= 0,
= 50 Ω
V
IC
= V min,
ICR
O
CMRR Common-mode rejection ratio
120
110
140
dB
S
V
DD
=
1.9 V to 8 V,
= 0,
k
Supply-voltage rejection ratio (∆V /∆V
DD IO
)
135
1.5
dB
SVR
R
= 50 Ω
= 0,
V
O
S
I
Supply current
V
O
No load
mA
DD
NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at T = 150°C extrapolated
A
at T = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
5. Output clamp is not connected.
A
operating characteristics at V
= 5 V, T = 25°C
A
DD
TLC2652Y
TYP
2.8
PARAMETER
TEST CONDITIONS
UNIT
MIN
2
MAX
SR+
SR−
Positive slew rate at unity gain
Negative slew rate at unity gain
V/µs
V/µs
V
C
=
2.3 V,
R
= 10 kΩ,
O
L
L
= 100 pF
2.3
3.1
f = 10 Hz
94
nV/√Hz
V
n
Equivalent input noise voltage
f = 1 kHz
23
f = 0 to 1 Hz
f = 0 to 10 Hz
f = 1 kHz
0.8
V
Peak-to-peak equivalent input noise voltage
Equivalent input noise current
Gain-bandwidth product
µV
N(PP)
2.8
I
n
pA/√Hz
MHz
f = 10 kHz,
R
C
= 10 kΩ,
L
L
1.9
C
= 100 pF
L
L
φ
m
Phase margin at unity gain
R
= 10 kΩ,
= 100 pF
48°
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢃ ꢈ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢑꢓ ꢕ ꢔꢇꢀ ꢖ ꢑꢗ ꢇ ꢁ ꢇꢐ ꢓꢁ ꢖ ꢝꢖ ꢕ ꢔꢒ
ꢂ
ꢐ
ꢑ
ꢒ
ꢓ ꢔꢕ ꢂꢖ ꢒꢖ ꢑ ꢗ ꢂꢘ ꢑꢓꢓ ꢕꢔꢙꢒ ꢀꢇꢚꢖ ꢁ ꢖꢛ ꢕꢜ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
V
IO
Normalized input offset voltage
vs Chopping frequency
1
vs Common-mode input voltage
vs Chopping frequency
vs Free-air temperature
2
3
4
I
IB
Input bias current
vs Chopping frequency
vs Free-air temperature
5
6
I
IO
Input offset current
Clamp current
vs Output voltage
vs Frequency
7
8
V
V
Maximum peak-to-peak output voltage
(OPP)
vs Output current
vs Free-air temperature
9, 10
11, 12
Maximum peak output voltage
Large-signal differential voltage amplification
Chopping frequency
OM
vs Frequency
vs Free-air temperature
13
14
A
VD
vs Supply voltage
vs Free-air temperature
15
16
vs Supply voltage
vs Free-air temperature
17
18
I
I
Supply current
DD
vs Supply voltage
vs Free-air temperature
19
20
Short-circuit output current
Slew rate
OS
vs Supply voltage
vs Free-air temperature
21
22
SR
Small-signal
Large-signal
23
24
Voltage-follower pulse response
V
V
Peak-to-peak equivalent input noise voltage
Equivalent input noise voltage
vs Chopping frequency
vs Frequency
25, 26
27
N(PP)
n
vs Supply voltage
vs Free-air temperature
28
29
Gain-bandwidth product
vs Supply voltage
vs Free-air temperature
vs Load capacitance
30
31
32
φ
m
Phase margin
Phase shift
vs Frequency
13
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢈ
ꢓꢔꢕ ꢂꢖꢒ ꢖꢑ ꢗ ꢂꢘꢑ ꢓꢓ ꢕꢔꢙꢒ ꢀꢇ ꢚꢖ ꢁꢖ ꢛꢕ ꢜ
ꢑ ꢓꢕꢔ ꢇꢀ ꢖꢑ ꢗꢇꢁ ꢇꢐꢓ ꢁꢖ ꢝ ꢖꢕ ꢔꢒ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢂ
ꢐ
ꢑ
ꢒ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
†
TYPICAL CHARACTERISTICS
NORMALIZED INPUT OFFSET VOLTAGE
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
vs
CHOPPING FREQUENCY
70
60
25
20
V
V
T
A
=
5 V
V
T
=
5 V
DD
= 0
DD
A
= 25°C
IC
= 25°C
50
40
30
15
10
5
20
10
0
−10
0
100
1 k
10 k
100 k
−5 −4 −3 −2 −1
0
1
2
3
4
5
Chopping Frequency − Hz
V
IC
− Common-Mode Input Voltage − V
Figure 1
Figure 2
INPUT BIAS CURRENT
vs
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
CHOPPING FREQUENCY
100
70
V
V
V
= 5 V
= 0
= 0
DD
O
IC
V
V
T
A
=
5 V
DD
= 0
IC
= 25°C
60
50
40
30
20
10
10
0
1
25
45
65
85
105
125
100
1 k
10 k
100 k
Chopping Frequency − Hz
T
A
− Free-Air Temperature − °C
Figure 3
Figure 4
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢃ ꢈ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢑꢓ ꢕ ꢔꢇꢀ ꢖ ꢑꢗ ꢇ ꢁ ꢇꢐ ꢓꢁ ꢖ ꢝꢖ ꢕ ꢔꢒ
ꢂ
ꢐ
ꢑ
ꢒ
ꢓ ꢔꢕ ꢂꢖ ꢒꢖ ꢑ ꢗ ꢂꢘ ꢑꢓꢓ ꢕꢔꢙꢒ ꢀꢇꢚꢖ ꢁ ꢖꢛ ꢕꢜ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
†
TYPICAL CHARACTERISTICS
INPUT OFFSET CURRENT
INPUT OFFSET CURRENT
vs
vs
CHOPPING FREQUENCY
FREE-AIR TEMPERATURE
10
8
25
20
15
10
5
V
V
T
A
=
5 V
V
V
=
5 V
DD
= 0
DD
= 0
IC
IC
= 25°C
6
4
2
0
0
100
25
45
65
85
105
125
1 k
10 k
100 k
Chopping Frequency − Hz
T
A
− Free-Air Temperature − °C
Figure 5
Figure 6
MAXIMUM PEAK-TO-PEAK OUTPUT
CLAMP CURRENT
vs
VOLTAGE
vs
OUTPUT VOLTAGE
FREQUENCY
10
8
100 µA
10 µA
1 µA
V
T
A
=
5 V
DD
= 25°C
T
= −55°C
= 125°C
Positive Clamp Current
A
100 nA
6
10 nA
T
A
4
1 nA
100 pA
10 pA
2
0
Negative Clamp Current
V
R
=
5 V
DD
L
= 10 kΩ
1 pA
100
1 k
10 k
1 M
4
4.2
4.4
4.6
4.8
5
f − Frequency − Hz
|V | − Output Voltage − V
O
Figure 7
Figure 8
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢈ
ꢓꢔꢕ ꢂꢖꢒ ꢖꢑ ꢗ ꢂꢘꢑ ꢓꢓ ꢕꢔꢙꢒ ꢀꢇ ꢚꢖ ꢁꢖ ꢛꢕ ꢜ
ꢑ ꢓꢕꢔ ꢇꢀ ꢖꢑ ꢗꢇꢁ ꢇꢐꢓ ꢁꢖ ꢝ ꢖꢕ ꢔꢒ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢂ
ꢐ
ꢑ
ꢒ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
†
TYPICAL CHARACTERISTICS
MAXIMUM PEAK OUTPUT VOLTAGE
MAXIMUM PEAK OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
5
4.8
4.6
7.5
V
T
A
=
5 V
DD
= 25°C
V
T
A
= 7.5 V
= 25°C
DD
7.3
7.1
V
OM+
V
OM−
V
V
OM+
OM−
4.4
4.2
4
6.9
6.7
0
0.4
0.8
1.2
1.6
2
0
0.4
0.8
1.2
1.6
2
|I | − Output Current − mA
O
|I | − Output Current − mA
O
Figure 9
Figure 10
MAXIMUM PEAK OUTPUT VOLTAGE
MAXIMUM PEAK OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5
8
2.5
4
0
V
R
=
7.5 V
V
=
5 V
R = 10 kΩ
L
DD
L
DD
= 10 kΩ
0
−2.5
−4
−8
−5
−50 −25
−75
0
25
50
75 100 125
−50 −25
−75
0
25
50
75 100 125
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 11
Figure 12
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢃ ꢈ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢑꢓ ꢕ ꢔꢇꢀ ꢖ ꢑꢗ ꢇ ꢁ ꢇꢐ ꢓꢁ ꢖ ꢝꢖ ꢕ ꢔꢒ
ꢂ
ꢐ
ꢑ
ꢒ
ꢓ ꢔꢕ ꢂꢖ ꢒꢖ ꢑ ꢗ ꢂꢘ ꢑꢓꢓ ꢕꢔꢙꢒ ꢀꢇꢚꢖ ꢁ ꢖꢛ ꢕꢜ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
†
TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
120
100
60°
80°
Phase Shift
80
60
100°
120°
A
VD
40
20
140°
160°
180°
200°
220°
0
−20
−40
V
R
C
= 5 V
DD
L
L
= 10 kΩ
= 100 pF
= 25°C
T
A
10
100
1 k
10 k
100 k
1 M
10 M
f − Frequency − Hz
Figure 13
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION
vs
FREE-AIR TEMPERATURE
155
V
R
= 7.5 V
DD
= 10 kΩ
L
V
O
=
4 V
150
145
140
135
−50 −25
−75
0
25
50
75
100 125
T
A
− Free-Air Temperature − °C
Figure 14
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢈ
ꢓꢔꢕ ꢂꢖꢒ ꢖꢑ ꢗ ꢂꢘꢑ ꢓꢓ ꢕꢔꢙꢒ ꢀꢇ ꢚꢖ ꢁꢖ ꢛꢕ ꢜ
ꢑ ꢓꢕꢔ ꢇꢀ ꢖꢑ ꢗꢇꢁ ꢇꢐꢓ ꢁꢖ ꢝ ꢖꢕ ꢔꢒ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢂ
ꢐ
ꢑ
ꢒ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
†
TYPICAL CHARACTERISTICS
CHOPPING FREQUENCY
vs
CHOPPING FREQUENCY
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
460
450
440
430
420
410
400
540
520
500
480
460
440
420
V
= 5 V
DD
T
= 25°C
A
−75 −50 −25
0
25
50
75
100 125
0
1
2
3
4
5
6
7
8
T − Free-Air Temperature − °C
A
|V
DD
| − Supply Voltage − V
Figure 15
Figure 16
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
2
1.6
1.2
2
V
= 0
O
V
V
=
=
7.5 V
5 V
DD
No Load
1.6
1.2
0.8
0.4
0
DD
T
= 25°C
A
V
DD
= 2.5 V
T
= −55°C
A
0.8
0.4
0
T
= 125°C
A
V
= 0
O
No Load
−75 −50 −25
0
25
50
75 100 125
0
1
2
3
4
5
6
7
8
T
A
− Free-Air Temperature − °C
|V
DD
| − Supply Voltage − V
Figure 17
Figure 18
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢃ ꢈ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢑꢓ ꢕ ꢔꢇꢀ ꢖ ꢑꢗ ꢇ ꢁ ꢇꢐ ꢓꢁ ꢖ ꢝꢖ ꢕ ꢔꢒ
ꢂ
ꢐ
ꢑ
ꢒ
ꢓ ꢔꢕ ꢂꢖ ꢒꢖ ꢑ ꢗ ꢂꢘ ꢑꢓꢓ ꢕꢔꢙꢒ ꢀꢇꢚꢖ ꢁ ꢖꢛ ꢕꢜ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
†
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT OUTPUT CURRENT
SHORT-CIRCUIT OUTPUT CURRENT
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
12
8
15
10
5
V
T
A
= 0
= 25°C
V = 5 V
DD
V = 0
O
O
4
V
ID
= −100 mV
V
ID
= −100 mV
0
0
−5
−4
−8
V
ID
= 100 mV
−10
−15
V
ID
= 100 mV
−12
0
1
2
3
4
5
6
7
8
−75 −50 −25
0
25
50
75
100 125
|V
DD
| − Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 19
Figure 20
SLEW RATE
vs
FREE-AIR TEMPERATURE
SLEW RATE
vs
SUPPLY VOLTAGE
4
3
4
V
R
C
= 5 V
= 10 kΩ
= 100 pF
DD
L
L
SR−
SR−
SR+
3
SR+
2
1
2
1
R
C
T
A
= 10 kΩ
= 100 pF
= 25°C
L
L
0
0
−75 −50 −25
0
25
50
75 100 125
0
1
2
3
4
5
6
7
8
T
A
− Free-Air Temperature − °C
|V
DD
| − Supply Voltage − V
Figure 21
Figure 22
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢈ
ꢓꢔꢕ ꢂꢖꢒ ꢖꢑ ꢗ ꢂꢘꢑ ꢓꢓ ꢕꢔꢙꢒ ꢀꢇ ꢚꢖ ꢁꢖ ꢛꢕ ꢜ
ꢑ ꢓꢕꢔ ꢇꢀ ꢖꢑ ꢗꢇꢁ ꢇꢐꢓ ꢁꢖ ꢝ ꢖꢕ ꢔꢒ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢂ
ꢐ
ꢑ
ꢒ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
TYPICAL CHARACTERISTICS
VOLTAGE-FOLLOWER
VOLTAGE-FOLLOWER
LARGE-SIGNAL
SMALL-SIGNAL
PULSE RESPONSE
PULSE RESPONSE
4
3
100
75
V
R
C
= 5 V
DD
L
L
= 10 kΩ
= 100 pF
= 25°C
T
A
2
50
V
R
C
= 5 V
DD
L
L
1
25
= 10 kΩ
= 100 pF
= 25°C
0
0
T
A
−1
−2
−25
−50
−3
−4
−75
−100
0
5
10 15 20 25 30 35 40
0
1
2
3
4
5
6
7
t − Time − µs
t − Time − µs
Figure 23
Figure 24
PEAK-TO-PEAK INPUT NOISE VOLTAGE
PEAK-TO-PEAK INPUT NOISE VOLTAGE
vs
vs
CHOPPING FREQUENCY
CHOPPING FREQUENCY
1.8
5
V
R
=
5 V
DD
S
V
R
=
5 V
DD
S
1.6
1.4
1.2
= 20 Ω
= 20 Ω
f = 0 to 1 Hz
T
A
f = 0 to 10 Hz
T
A
4
3
2
1
0
= 25°C
= 25°C
1
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
0
2
4
6
8
10
f
− Chopping Frequency − kHz
f
− Chopping Frequency − kHz
ch
ch
Figure 25
Figure 26
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢃ ꢈ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢑꢓ ꢕ ꢔꢇꢀ ꢖ ꢑꢗ ꢇ ꢁ ꢇꢐ ꢓꢁ ꢖ ꢝꢖ ꢕ ꢔꢒ
ꢂ
ꢐ
ꢑ
ꢒ
ꢓ ꢔꢕ ꢂꢖ ꢒꢖ ꢑ ꢗ ꢂꢘ ꢑꢓꢓ ꢕꢔꢙꢒ ꢀꢇꢚꢖ ꢁ ꢖꢛ ꢕꢜ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
†
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
GAIN-BANDWIDTH PRODUCT
vs
vs
FREQUENCY
SUPPLY VOLTAGE
100
80
2.1
R
C
T
A
= 10 kΩ
= 100 pF
= 25°C
L
L
2
60
40
1.9
20
0
V
R
T
A
= 5 V
= 20 Ω
= 25°C
DD
S
1.8
1
10
100
1 k
0
1
2
3
4
5
6
7
8
f − Frequency − Hz
|V
CC
| − Supply Voltage − V
Figure 27
Figure 28
PHASE MARGIN
vs
SUPPLY VOLTAGE
GAIN-BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
50°
2.6
2.4
2.2
2
R
C
T
A
= 10 kΩ
= 100 pF
= 25°C
L
L
V
R
C
= 5 V
= 10 kΩ
= 100 pF
DD
L
L
48°
46°
44°
42°
40°
1.8
1.4
1.2
0
1
2
3
4
5
6
7
8
−75 −50 −25
0
25
50
75
100 125
|V
CC
| − Supply Voltage − V
T
A
− Free-Air Temperature − °C
Figure 29
Figure 30
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢈ
ꢓꢔꢕ ꢂꢖꢒ ꢖꢑ ꢗ ꢂꢘꢑ ꢓꢓ ꢕꢔꢙꢒ ꢀꢇ ꢚꢖ ꢁꢖ ꢛꢕ ꢜ
ꢑ ꢓꢕꢔ ꢇꢀ ꢖꢑ ꢗꢇꢁ ꢇꢐꢓ ꢁꢖ ꢝ ꢖꢕ ꢔꢒ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢂ
ꢐ
ꢑ
ꢒ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
†
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
PHASE MARGIN
vs
LOAD CAPACITANCE
FREE-AIR TEMPERATURE
50°
60°
V
R
T
A
= 5 V
= 10 kΩ
= 25°C
DD
L
50°
40°
48°
46°
30°
20°
10°
44°
42°
40°
V
R
C
=
5 V
DD
L
L
= 10 kΩ
= 100 pF
0°
0
200
400
600
800
1000
−75
0
25
50
75 100 125
−50 −25
C
− Load Capacitance − pF
T
A
− Free-Air Temperature − °C
L
Figure 31
Figure 32
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
APPLICATION INFORMATION
capacitor selection and placement
The two important factors to consider when selecting external capacitors C
and C
are leakage and
XA
XB
dielectric absorption. Both factors can cause system degradation, negating the performance advantages
realized by using the TLC2652.
Degradation from capacitor leakage becomes more apparent with the increasing temperatures. Low-leakage
capacitors and standoffs are recommended for operation at T = 125°C. In addition, guard bands are
A
recommended around the capacitor connections on both sides of the printed circuit board to alleviate problems
caused by surface leakage on circuit boards.
Capacitors with high dielectric absorption tend to take several seconds to settle upon application of power, which
directly affects input offset voltage. In applications where fast settling of input offset voltage is needed, it is
recommended that high-quality film capacitors, such as mylar, polystyrene, or polypropylene, be used. In other
applications, however, a ceramic or other low-grade capacitor can suffice.
Unlike many choppers available today, the TLC2652 is designed to function with values of C and C in the
XA
XB
range of 0.1 µF to 1 µF without degradation to input offset voltage or input noise voltage. These capacitors
should be located as close as possible to the C and C pins and returned to either V or C RETURN. On
XA
XB
DD−
many choppers, connecting these capacitors to V
is eliminated on the TLC2652.
causes degradation in noise performance. This problem
DD−
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢃ ꢈ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢑꢓ ꢕ ꢔꢇꢀ ꢖ ꢑꢗ ꢇ ꢁ ꢇꢐ ꢓꢁ ꢖ ꢝꢖ ꢕ ꢔꢒ
ꢂ
ꢐ
ꢑ
ꢒ
ꢓ ꢔꢕ ꢂꢖ ꢒꢖ ꢑ ꢗ ꢂꢘ ꢑꢓꢓ ꢕꢔꢙꢒ ꢀꢇꢚꢖ ꢁ ꢖꢛ ꢕꢜ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
internal/external clock
The TLC2652 has an internal clock that sets the chopping frequency to a nominal value of 450 Hz. On 8-pin
packages, the chopping frequency can only be controlled by the internal clock; however, on all 14-pin packages
and the 20-pin FK package, the device chopping frequency can be set by the internal clock or controlled
externally by use of the INT/EXT and CLK IN pins. To use the internal 450-Hz clock, no connection is necessary.
If external clocking is desired, connect INT/EXT to V
and the external clock to CLK IN. The external clock
DD−
trip point is 2.5 V above the negative rail; however, CLK IN can be driven from the negative rail to 5 V above
the negative rail. If this level is exceeded, damage could occur to the device unless the current into CLK IN is
limited to 5 mA. When operating in the single-supply configuration, this feature allows the TLC2652 to be driven
directly by 5-V TTL and CMOS logic. A divide-by-
0
two frequency divider interfaces with CLK IN and
V
T
A
= 5 V
= 25°C
DD
sets the clock chopping frequency. The duty cycle
of the external clock is not critical but should be
kept between 30% and 60%.
overload recovery/output clamp
−5
0
When large differential input voltage conditions
are applied to the TLC2652, the nulling loop
attempts to prevent the output from saturating by
driving C and C to internally-clamped voltage
XA
XB
levels. Once the overdrive condition is removed,
a period of time is required to allow the built-up
charge to dissipate. This time period is defined as
overload recovery time (see Figure 33). Typical
overload recovery time for the TLC2652 is
significantly faster than competitive products;
however, if required, this time can be reduced
further by use of internal clamp circuitry
accessible through CLAMP if required.
−50
0
10 20 30 40 50 60 70 80
t − Time − ms
Figure 33. Overload Recovery
The clamp is a switch that is automatically activated when the output is approximately 1 V from either supply
rail. When connected to the inverting input (in parallel with the closed-loop feedback resistor), the closed-loop
gain is reduced, and the TLC2652 output is prevented from going into saturation. Since the output must source
or sink current through the switch (see Figure 7), the maximum output voltage swing is slightly reduced.
thermoelectric effects
To take advantage of the extremely low offset voltage drift of the TLC2652, care must be taken to compensate
for the thermoelectric effects present when two dissimilar metals are brought into contact with each other (such
as device leads being soldered to a printed circuit board). Dissimilar metal junctions can produce thermoelectric
voltages in the range of several microvolts per degree Celsius (orders of magnitude greater than the 0.01-µV/°C
typical of the TLC2652).
To help minimize thermoelectric effects, careful attention should be paid to component selection and
circuit-board layout. Avoid the use of nonsoldered connections (such as sockets, relays, switches, etc.) in the
input signal path. Cancel thermoelectric effects by duplicating the number of components and junctions in each
device input. The use of low-thermoelectric-coefficient components, such as wire-wound resistors, is also
beneficial.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢀ ꢁꢂ ꢃ ꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢈ
ꢓꢔꢕ ꢂꢖꢒ ꢖꢑ ꢗ ꢂꢘꢑ ꢓꢓ ꢕꢔꢙꢒ ꢀꢇ ꢚꢖ ꢁꢖ ꢛꢕ ꢜ
ꢑ ꢓꢕꢔ ꢇꢀ ꢖꢑ ꢗꢇꢁ ꢇꢐꢓ ꢁꢖ ꢝ ꢖꢕ ꢔꢒ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢂ
ꢐ
ꢑ
ꢒ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
latch-up avoidance
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC2652 inputs
and output are designed to withstand −100-mA surge currents without sustaining latch-up; however, techniques
to reduce the chance of latch-up should be used whenever possible. Internal protection diodes should not, by
design, be forward biased. Applied input and output voltages should not exceed the supply voltage by more than
300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients
should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails as close
to the device as possible.
The current path established if latch-up occurs is usually between the supply rails and is limited only by the
impedance of the power supply and the forward resistance of the parasitic thyristor. The chance of latch-up
occurring increases with increasing temperature and supply voltage.
electrostatic discharge protection
The TLC2652 incorporates internal ESD-protection circuits that prevent functional failures at voltages at or
below 2000 V. Care should be exercised in handling these devices, as exposure to ESD may result in
degradation of the device parametric performance.
theory of operation
Chopper-stabilized operational amplifiers offer the best dc performance of any monolithic operational amplifier.
This superior performance is the result of using two operational amplifiers, a main amplifier and a nulling
amplifier, plus oscillator-controlled logic and two external capacitors to create a system that behaves as a single
amplifier. With this approach, the TLC2652 achieves submicrovolt input offset voltage, submicrovolt noise
voltage, and offset voltage variations with temperature in the nV/°C range.
The TLC2652 on-chip control logic produces two dominant clock phases: a nulling phase and an amplifying
phase. The term chopper-stabilized derives from the process of switching between these two clock phases.
Figure 34 shows a simplified block diagram of the TLC2652. Switches A and B are make-before-break types.
During the nulling phase, switch A is closed shorting the nulling amplifier inputs together and allowing the nulling
amplifier to reduce its own input offset voltage by feeding its output signal back to an inverting input node.
Simultaneously, external capacitor C stores the nulling potential to allow the offset voltage of the amplifier to
XA
remain nulled during the amplifying phase.
Main Amplifier
IN+
IN−
+
V
O
−
B
C
XB
B
A
+
−
V
DD−
Null
Amplifier
A
C
XA
Figure 34. TLC2652 Simplified Block Diagram
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ ꢀ ꢁ ꢂ ꢃꢄ ꢅꢃ ꢇ ꢆ ꢀꢁ ꢂꢃ ꢄ ꢅ ꢃ ꢈ
ꢇ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢎ
ꢉ
ꢁ
ꢏ
ꢌ
ꢑꢓ ꢕ ꢔꢇꢀ ꢖ ꢑꢗ ꢇ ꢁ ꢇꢐ ꢓꢁ ꢖ ꢝꢖ ꢕ ꢔꢒ
ꢂ
ꢐ
ꢑ
ꢒ
ꢓ ꢔꢕ ꢂꢖ ꢒꢖ ꢑ ꢗ ꢂꢘ ꢑꢓꢓ ꢕꢔꢙꢒ ꢀꢇꢚꢖ ꢁ ꢖꢛ ꢕꢜ
SLOS019E − SEPTEMBER 1988 − REVISED FEBRUARY 2005
APPLICATION INFORMATION
theory of operation (continued)
During the amplifying phase, switch B is closed connecting the output of the nulling amplifier to a noninverting
input of the main amplifier. In this configuration, the input offset voltage of the main amplifier is nulled. Also,
external capacitor C
nulled during the next nulling phase.
stores the nulling potential to allow the offset voltage of the main amplifier to remain
XB
This continuous chopping process allows offset voltage nulling during variations in time and temperature over
the common-mode input voltage range and power supply range. In addition, because the low-frequency signal
path is through both the null and main amplifiers, extremely high gain is achieved.
The low-frequency noise of a chopper amplifier depends on the magnitude of the component noise prior to
chopping and the capability of the circuit to reduce this noise while chopping. The use of the Advanced LinCMOS
process, with its low-noise analog MOS transistors and patent-pending input stage design, significantly reduces
the input noise voltage.
The primary source of nonideal operation in chopper-stabilized amplifiers is error charge from the switches. As
charge imbalance accumulates on critical nodes, input offset voltage can increase, especially with increasing
chopping frequency. This problem has been significantly reduced in the TLC2652 by use of a patent-pending
compensation circuit and the Advanced LinCMOS process.
The TLC2652 incorporates a feed-forward design that ensures continuous frequency response. Essentially, the
gain magnitude of the nulling amplifier and compensation network crosses unity at the break frequency of the
main amplifier. As a result, the high-frequency response of the system is the same as the frequency response
of the main amplifier. This approach also ensures that the slewing characteristics remain the same during both
the nulling and amplifying phases.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-9089501M2A
ACTIVE
LCCC
CDIP
FK
20
14
1
TBD
POST-PLATE
A42
N / A for Pkg Type
-55 to 125
5962-
9089501M2A
TLC2652MFKB
5962-9089501MCA
ACTIVE
J
1
TBD
N / A for Pkg Type
-55 to 125
5962-9089501MC
A
TLC2652MJB
5962-9089501MPA
5962-9089503M2A
ACTIVE
ACTIVE
CDIP
JG
FK
8
1
1
TBD
TBD
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
9089501MPA
TLC2652M
LCCC
20
POST-PLATE
5962-
9089503M2A
TLC2652AMFKB
5962-9089503MCA
ACTIVE
CDIP
J
14
1
TBD
TBD
A42
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9089503MC
A
TLC2652AMJB
5962-9089503MPA
TLC2652AC-14D
TLC2652AC-14DG4
TLC2652AC-8D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
SOIC
SOIC
SOIC
SOIC
JG
D
8
14
14
8
1
A42
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
9089503MPA
TLC2652AM
50
50
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
2652AC
2652AC
2652AC
2652AC
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
TLC2652AC-8DG4
D
8
Green (RoHS
& no Sb/Br)
TLC2652AC-8DR
TLC2652ACN
OBSOLETE
ACTIVE
SOIC
PDIP
D
N
0
TBD
Call TI
Call TI
14
25
25
50
50
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
TLC2652ACN
TLC2652ACN
TLC2652AC
TLC2652AC
2652AI
TLC2652ACNE4
TLC2652ACP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PDIP
PDIP
PDIP
SOIC
N
P
P
D
14
8
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Pb-Free
(RoHS)
TLC2652ACPE4
TLC2652AI-14D
8
Pb-Free
(RoHS)
14
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TLC2652AI-14DG4
TLC2652AI-8D
TLC2652AI-8DG4
TLC2652AI-8DR
TLC2652AI-8DRG4
TLC2652AIN
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
PDIP
PDIP
LCCC
D
14
8
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
2652AI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
75
75
Green (RoHS
& no Sb/Br)
2652AI
8
Green (RoHS
& no Sb/Br)
2652AI
D
8
2500
2500
25
Green (RoHS
& no Sb/Br)
2652AI
D
8
Green (RoHS
& no Sb/Br)
2652AI
N
14
14
8
Pb-Free
(RoHS)
TLC2652AIN
TLC2652AIN
TLC2652AI
TLC2652AI
TLC2652AINE4
TLC2652AIP
N
25
Pb-Free
(RoHS)
P
50
Pb-Free
(RoHS)
TLC2652AIPE4
TLC2652AMFKB
P
8
50
Pb-Free
(RoHS)
FK
20
1
TBD
-55 to 125
-55 to 125
5962-
9089503M2A
TLC2652AMFKB
TLC2652AMJB
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
5962-9089503MC
A
TLC2652AMJB
TLC2652AMJG
TLC2652AMJGB
ACTIVE
ACTIVE
CDIP
CDIP
JG
JG
8
8
1
1
TBD
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
TLC2652
AMJG
9089503MPA
TLC2652AM
TLC2652C-14D
TLC2652C-8D
OBSOLETE
ACTIVE
SOIC
SOIC
D
D
14
8
Call TI
Call TI
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
2652C
2652C
2652C
TLC2652C-8DG4
TLC2652C-8DR
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
2500
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TLC2652C-8DRG4
TLC2652CN
ACTIVE
SOIC
PDIP
PDIP
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
LCCC
D
8
14
14
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
N / A for Pkg Type
2652C
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
N
N
P
25
25
Pb-Free
(RoHS)
TLC2652CN
TLC2652CN
TLC2652CP
TLC2652CP
2652I
TLC2652CNE4
TLC2652CP
Pb-Free
(RoHS)
50
Pb-Free
(RoHS)
TLC2652CPE4
TLC2652I-8D
P
8
50
Pb-Free
(RoHS)
D
D
D
D
P
8
75
Green (RoHS
& no Sb/Br)
TLC2652I-8DG4
TLC2652I-8DR
TLC2652I-8DRG4
TLC2652IP
8
75
Green (RoHS
& no Sb/Br)
2652I
8
2500
2500
50
Green (RoHS
& no Sb/Br)
2652I
8
Green (RoHS
& no Sb/Br)
2652I
8
Pb-Free
(RoHS)
TLC2652IP
TLC2652IP
T2652M
TLC2652IPE4
TLC2652M-8DG4
TLC2652MFKB
P
8
50
Pb-Free
(RoHS)
D
FK
8
1000
1
Green (RoHS
& no Sb/Br)
20
TBD
-55 to 125
5962-
9089501M2A
TLC2652MFKB
TLC2652MJG
ACTIVE
ACTIVE
CDIP
CDIP
JG
JG
8
8
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
TLC2652MJG
TLC2652MJGB
9089501MPA
TLC2652M
TLC2652Q-8D
ACTIVE
ACTIVE
SOIC
SOIC
D
D
8
8
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
T2652Q
TLC2652Q-8DG4
Green (RoHS
& no Sb/Br)
T2652Q
(1) The marketing status values are defined as follows:
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC2652, TLC2652A, TLC2652AM, TLC2652M :
Catalog: TLC2652A, TLC2652
•
Military: TLC2652M, TLC2652AM
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Military - QML certified for Military and Defense Applications
•
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC2652AI-8DR
TLC2652C-8DR
TLC2652I-8DR
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
6.4
6.4
6.4
5.2
5.2
5.2
2.1
2.1
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC2652AI-8DR
TLC2652C-8DR
TLC2652I-8DR
SOIC
SOIC
SOIC
D
D
D
8
8
8
2500
2500
2500
340.5
340.5
340.5
338.1
338.1
338.1
20.6
20.6
20.6
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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