TLC2810ZP [TI]
LinCMOSE PRECISION DUAL OPERATIONAL AMPLIFIERS;
| 型号： | TLC2810ZP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LinCMOSE PRECISION DUAL OPERATIONAL AMPLIFIERS 放大器 光电二极管 |
| 文件： | 总23页 (文件大小：336K) |
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TLC2810Z, TLC2810Y
LinCMOS PRECISION
DUAL OPERATIONAL AMPLIFIERS
SLOS120A – AUGUST 1993 – REVISED AUGUST 1994
Trimmed Input Offset Voltage:
10 mV Max at 25°C, V = 5 V
Low Noise . . . 25 nV/√Hz Typ at f = 1 kHz
DD
Output Voltage Range Includes Negative
Rail
Input Offset Voltage Drift Typically
0.1 µV/Month, Including the First 30 Days
12
High Input Impedance . . . 10 Ω Typ
Wide Range of Supply Voltages Over
Specified Temperature Range:
–40°C to 150°C . . . 4 V to 16 V
ESD-Protection Circuitry
Small-Outline Package Option Also
Available in Tape and Reel
Single-Supply Operation
Designed-In Latch-Up Immunity
Common-Mode Input Voltage Range
Extends to the Negative Rail
D OR P PACKAGE
(TOP VIEW)
description
1OUT
1IN–
1IN+
GND
V
DD
1
2
3
4
8
7
6
5
The TLC2810Z dual operational amplifiers
combine low offset voltage drift with high input
impedance, low noise, and speeds approaching
that ofgeneral-purposeJFETdevices. Inaddition,
the use of Texas Instruments silicon-gate
LinCMOS technology assures offset stability that
greatly exceeds the stability available with
conventional metal-gate processes.
2OUT
2IN–
2IN+
The high input impedance, low bias current, and high slew rate make the TLC2810Z ideal for applications that
have previously been reserved for JFET and NFET products. These advantages, in combination with an upper
operating temperature of 150°C, make the TLC2810Z an ideal choice for precision, extremely high-temperature
applications.
In general, many features associated with bipolar technology are available on the TLC2810Z without the power
penalties of bipolar technology. General applications such as transducer interfacing, analog calculations,
amplifier blocks, active filters, and signal buffering are designed easily with the TLC2810Z.
The TLC2810Z package options include a small-outline version for high-density system applications.
The device inputs and outputs are designed to withstand –100-mA surge currents without sustaining latch-up
at 25°C. The TLC2810Z incorporates internal ESD-protection circuits that prevent functional failures atvoltages
up to 2000 V as tested under MIL-STD 883C, Method 3015.2. However, care should be exercised in handling
the TLC2810Z as exposure to ESD may result in the degradation of the device parametric performance.
Additional care should be exercised to prevent V
supply line transients under power conditions. Transients
DD
of greater than 20 V can trigger the ESD-protection structure, inducing a low-impedance path to GND. Should
this condition occur, the sustained current supplied to the device must be limited to 100 mA or less. Failure to
do so can result in a latched condition and device failure.
The TLC2810Z is characterized for operation over the extended temperature range from –40°C to 150°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL OUTLINE PLASTIC DIP
CHIP
FORM
(Y)
T
A
†
(D)
(P)
–40°C to 150°C
TLC2810ZD
TLC2810ZP
TLC2810Y
†
The D packages are available taped and reeled. Add R suffix to the device type when
ordering (e.g., TLC2810ZDR).
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2810Z, TLC2810Y
LinCMOS PRECISION
DUAL OPERATIONAL AMPLIFIERS
SLOS120A – AUGUST 1993 – REVISED AUGUST 1994
TLC2810Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC2810Z. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
V
DD
(8)
(3)
(2)
1IN+
1IN–
2IN+
2IN–
+
–
(4)
(1)
(7)
(3)
(2)
(5)
(6)
1OUT
2OUT
(5)
(6)
+
–
(4)
GND
59
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
T max = 165°C
J
TOLERANCES ARE ±10%.
(1)
(7)
ALL DIMENSIONS ARE IN MILS.
(8)
PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
72
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2810Z, TLC2810Y
LinCMOS PRECISION
DUAL OPERATIONAL AMPLIFIERS
SLOS120A – AUGUST 1993 – REVISED AUGUST 1994
equivalent schematic (each amplifier)
V
DD
P3
P4
R6
P1
P2
N5
IN–
IN+
R2
R1
P6
P5
C1
R5
N3
OUT
N4
N1
D1
N2
N6
R7
D2
R3
R4
N7
GND
†
COMPONENT COUNT
Transistors
Diodes
26
4
Resistors
Capacitors
14
2
†
Includes both amplifiers
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2810Z, TLC2810Y
LinCMOS PRECISION
DUAL OPERATIONAL AMPLIFIERS
SLOS120A – AUGUST 1993 – REVISED AUGUST 1994
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
ID
DD
DD
I
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
I
Output current, I (each output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA
O
Total current into V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
DD
Total current out of GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 mA
Duration of short-circuit current at (or below) T = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
A
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
A
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 165°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN–.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded (see application selection).
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 105°C
T
= 125°C
T = 150°C
A
A
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING POWER RATING POWER RATING
A
D
P
812 mV
5.8 mW/°C
8.0 mW/°C
551 mW
760 mW
348 mW
480 mW
232 mW
320 mW
87 mW
1120 mV
120 mW
recommended operating conditions
MIN
4
MAX
UNIT
Supply voltage, V
16
3.5
3.5
150
V
V
DD
Common-mode input voltage, V
V
V
= 5 V,
= 5 V
T = 25°C
A
–0.2
–0.2
–40
IC
DD
Input voltage, V
V
I
DD
Operating free-air temperature, T
°C
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2810Z, TLC2810Y
LinCMOS PRECISION
DUAL OPERATIONAL AMPLIFIERS
SLOS120A – AUGUST 1993 – REVISED AUGUST 1994
electrical characteristics, V
= 5 V (unless otherwise noted)
DD
TLC2810Z
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
TYP
MAX
10
25°C
1.8
V
R
= 1 V,
= 50 Ω,
V
R
= 1 V,
= 10 kΩ
O
IC
V
IO
Input offset voltage
mV
Full range
12
S
L
25°C to
150°C
α
Average temperature coefficient of input offset voltage
Input offset current (see Note 4)
3.5
µV/°C
VIO
25°C
150°C
25°C
2.4
5.2
7
100
30
pA
nA
pA
nA
I
IO
V
V
= 1 V,
= 1 V,
V
V
= 1 V
= 1 V
IC
O
100
150
I
IB
Input bias current (see Note 4)
IC
O
150°C
50
–0.2
to
–0.3
to
4.2
25°C
V
V
4
V
Common-mode input voltage range (see Note 5)
R
V
= 50 Ω
S
ICR
–0.2
to
Full range
3.8
= 1 V,
= 100 mV,
= –1 mA
25°C
Full range
25°C
3.2
3
3.8
80
25
90
IC
ID
V
V
A
High-level output voltage
V
V
OH
I
OH
V
V
= 1 V,
= –100 mV,
= 1 mA
150
190
IC
ID
Low-level output voltage
mV
V/mV
dB
OL
Full range
25°C
I
OL
V
V
R
= 1 V,
= 0.25 V to 2 V,
5
4
IC
O
Large-signal differential voltage amplification
VD
Full range
25°C
= 10 kΩ
L
V
= 1 V,
65
60
65
60
O
CMRR Common-mode rejection ratio
V
IC
= V
min,
ICR
Full range
25°C
R
= 50 Ω
S
V
V
R
= 4 V to 16 V,
75
1
DD
O
S
k
Supply-voltage rejection ratio (∆V /∆V
DD IO
)
dB
= 1 V,
V
IC
= 1 V,
SVR
Full range
= 50 Ω
25°C
3.2
4.4
V
= 1 V,
V
IC
= 1 V,
O
I
Supply current
mA
DD
No load
Full range
†
Full range is –40°C to 150°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2810Z, TLC2810Y
LinCMOS PRECISION
DUAL OPERATIONAL AMPLIFIERS
SLOS120A – AUGUST 1993 – REVISED AUGUST 1994
operating characteristics, V
= 5 V (unless otherwise noted)
DD
TLC2810Z
TYP
3.6
PARAMETER
TEST CONDITIONS
T
UNIT
A
MIN
MAX
25°C
150°C
25°C
V
= 1 V
I(PP)
I(PP)
R
C
= 10 kΩ,
L
L
2.8
SR
Slew rate at unity gain
V/µs
= 20 pF,
2.2
See Figure 26
V
= 2.5 V
150°C
2.1
f =1 kHz,
See Figure 27
R
= 20 Ω,
S
V
n
Equivalent input noise voltage
25°C
25
nV/√Hz
25°C
150°C
25°C
320
200
1.7
0.8
46°
40°
V
R
= V
,
C
= 20 pF,
O
L
OH
= 10 kΩ,
L
B
B
Maximum output-swing bandwidth
Unity-gain bandwidth
Phase margin
kHz
OM
1
See Figure 26
C = 20 pF,
L
V = 10 mV,
I
See Figure 28
MHz
150°C
25°C
V = 10 mV,
f = B ,
1
See Figure 28
I
φ
m
C
= 20 pF,
L
150°C
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2810Z, TLC2810Y
LinCMOS PRECISION
DUAL OPERATIONAL AMPLIFIERS
SLOS120A – AUGUST 1993 – REVISED AUGUST 1994
electrical characteristics at V
= 5 V, T = 25°C (unless otherwise noted)
A
DD
TLC2810Y
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
10
V
IO
Input offset voltage
mV
pA
pA
V
R
= 1 V,
V
O
= 1 V,
IC
S
I
Input offset current (see Note 4)
Input bias current (see Note 4)
100
100
IO
IB
= 50 Ω
I
–0.2
to
V
ICR
Common-mode input voltage range (see Note 5)
R
= 50 Ω
V
S
4
V
= 1 V,
= –1 mA
V
V
= 100 mV,
= –100 mV,
= 10 kΩ,
IC
ID
V
V
High-level output voltage
3.2
V
mV
V/mV
dB
OH
I
OH
V
= 1 V,
= 1 mA
IC
ID
Low-level output voltage
150
OL
I
OL
V
V
= 0.25 V to 2 V,
= 1 V
R
O
IC
L
A
VD
Large-signal differential voltage amplification
5
65
65
V
R
= 1 V,
= 50 Ω
V
V
= V
min,
ICR
O
IC
CMRR Common-mode rejection ratio
S
V
V
= 4 V to 16 V,
= 1 V,
= 1 V,
= 50 Ω
DD
O
IC
k
Supply-voltage rejection ratio (∆V
/∆V )
IO
dB
SVR
DD±
R
S
V
= 1 V,
V
IC
= 1 V,
O
I
Supply current
3.2
mA
DD
No load
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
operating characteristics, V
= 5 V, T = 25°C
A
DD
TLC2810Y
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
R
C
= 10 kΩ,
= 20 pF,
V
V
= 1 V
3.6
2.9
L
L
I(PP)
SR
Slew rate at unity gain
V/µs
= 2.5 V
See Figure 26
I(PP)
f =1 kHz,
See Figure 27
R
= 20 Ω,
S
L
V
n
Equivalent input noise voltage
Maximum output-swing bandwidth
Unity-gain bandwidth
25
320
1.7
nV/√Hz
kHz
V
R
= V
OH
= 10 kΩ,
,
C
= 20 pF,
O
L
B
OM
1
See Figure 26
C = 20 pF,
L
V = 10 mV,
I
See Figure 28
B
MHz
V = 10 mV,
f = B ,
1
See Figure 28
I
φ
m
Phase margin
46°
C
= 20 pF,
L
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2810Z, TLC2810Y
LinCMOS PRECISION
DUAL OPERATIONAL AMPLIFIERS
SLOS120A – AUGUST 1993 – REVISED AUGUST 1994
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
V
Input offset voltage
Distribution
Distribution
1
2
IO
α
Input offset voltage temperature coefficient
VIO
vs Output current
vs Supply voltage
vs Free-air temperature
3
4
5
V
V
A
High-level output voltage
OH
OL
vs Common-mode input voltage
vs Differential input voltage
vs Free-air temperature
6
7
8
9
Low-level output voltage
vs Low-level output current
vs Supply voltage
vs Free-air temperature
vs Frequency
10
11
21
Large-signal differential voltage amplification
VD
I
/I
Input bias and offset current
Common-mode input voltage
vs Free-air temperature
vs Supply voltage
12
13
IB IO
V
IC
vs Supply voltage
vs Free-air temperature
14
15
I
Supply current
DD
vs Supply voltage
vs Free-air temperature
16
17
SR
Slew rate
V
B
Maximum peak-to-peak output voltage
Gain-bandwidth product
vs Frequency
18
O(PP)
vs Free-air temperature
vs Supply voltage
19
20
1
vs Supply voltage
vs Free-air temperature
vs Load capacitance
22
23
24
φ
m
Phase margin
V
n
Equivalent input noise voltage
Phase shift
vs Frequency
vs Frequency
25
21
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2810Z, TLC2810Y
LinCMOS PRECISION
DUAL OPERATIONAL AMPLIFIERS
SLOS120A – AUGUST 1993 – REVISED AUGUST 1994
TYPICAL CHARACTERISTICS
DISTRIBUTION OF TLC2810Z
INPUT OFFSET VOLTAGE
TEMPERATURE COEFFICIENT
DISTRIBUTION OF TLC2810Z
INPUT OFFSET VOLTAGE
60
50
60
50
V
= 5 V
= 25°C to 150°C
DD
V
= 5 V
= 25°C
DD
T
A
T
A
P Package
Outliers:
P Package
(1) 20.5 mV/°C
40
30
40
30
20
20
10
0
10
0
–10 – 8 – 6 – 4 – 2
0
2
4
6
8
10
– 5 – 4 – 3 – 2 –1
0
1
2
3
4
5
α
– Temperature Coefficient – µV/°C
VIO
V
IO
– Input Offset Voltage – mV
Figure 1
Figure 2
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vs
vs
SUPPLY VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
16
12
8
5
4
3
V
V
= 1 V
V
V
V
T
= 5 V
= 1 V
= 100 mV
= 25°C
IC
ID
L
DD
IC
ID
= 100 mV
= 10 kΩ
= 25°C
R
T
A
A
2
1
0
4
0
0
– 2
– 4
– 6
– 8
0
4
8
12
16
V
DD
– Supply Voltage – V
I
– High-Level Output Current – mA
OH
Figure 3
Figure 4
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2810Z, TLC2810Y
LinCMOS PRECISION
DUAL OPERATIONAL AMPLIFIERS
SLOS120A – AUGUST 1993 – REVISED AUGUST 1994
TYPICAL CHARACTERISTICS
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
COMMON-MODE INPUT VOLTAGE
700
650
600
550
4.5
4
V
I
T
A
= 5 V
= 5 mA
= 25°C
DD
OL
3.5
3
V
ID
= –100 mV
500
450
I
= –500 µA
OH
I
I
I
I
= –1 mA
400
350
OH
= –2 mA
= –3 mA
= –4 mA
V
= –1 V
2.5
2
OH
OH
OH
ID
V
V
V
= 5 V
= 1 V
= 100 mV
DD
IC
ID
300
–75 –50 –25
0
25 50 75 100 125 150
0
0.5
1
1.5
2
2.5
3
3.5
4
T
A
– Free-Air Temperature – °C
V
IC
– Common-Mode Input Voltage – V
Figure 5
Figure 6
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
FREE-AIR TEMPERATURE
800
700
600
500
900
800
700
600
500
V
V
= 5 V
= |V /2|
ID
= 5 mA
DD
IC
V
V
V
= 5 V
= 1 V
= –1 V
= 5 mA
DD
IC
ID
I
T
OL
= 25°C
A
I
OL
400
300
400
300
200
100
200
100
0
0
–75 –50 –25
0
25 50 75 100 125 150
0
–1
–2
–3
–4
V
ID
– Differential Input Voltage – V
T
A
– Free-Air Temperature – °C
Figure 7
Figure 8
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2810Z, TLC2810Y
LinCMOS PRECISION
DUAL OPERATIONAL AMPLIFIERS
SLOS120A – AUGUST 1993 – REVISED AUGUST 1994
TYPICAL CHARACTERISTICS
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
LOW-LEVEL OUTPUT CURRENT
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
60
50
40
30
20
10
0
T
= –40°C
A
V
V
V
= 5 V
= 1 V
= –100 mV
= 25°C
R
= 10 kΩ
DD
IC
ID
L
T
A
T
= 25°C
A
T
= 85°C
A
T
A
= 150°C
0.2
0.1
0
0
2
4
6
8
10
12
14
16
0
1
2
3
4
5
6
7
8
V
DD
– Supply Voltage – V
I
– Low-Level Output Current – mA
OL
Figure 9
Figure 10
LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
INPUT BIAS CURRENT AND INPUT
OFFSET CURRENT
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
5
10
50
45
V
R
= 5 V
= 10 kΩ
DD
L
V
V
= 5 V
DD
= 1 V
IC
See Note A
4
3
2
1
0
10
10
10
10
10
40
35
30
I
IB
25
20
15
10
5
I
IO
0
25
50
75
100
125
150
–75 – 50 – 25
0
25 50 75 100 125 150
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
NOTE A: The typical values of input bias current and input offset current
below 5 pA were determined mathematically.
Figure 11
Figure 12
11
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TYPICAL CHARACTERISTICS
COMMON-MODE INPUT VOLTAGE
POSITIVE LIMIT
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
vs
SUPPLY VOLTAGE
16
14
12
5
T
A
= 25°C
V
V
= 1 V
= 1 V
IC
O
4.5
4
No Load
3.5
3
10
8
2.5
2
T
A
= 150°C
6
4
T
A
= – 40°C
1.5
1
T
A
= 25°C
2
0
0.5
0
0
4
8
12
16
2
6
10
14
0
2
4
6
8
10
12
14 16
V
DD
– Supply Voltage – V
V
DD
– Supply Voltage – V
Figure 13
Figure 14
SLEW RATE
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
vs
SUPPLY VOLTAGE
8
7
6
5
4
3
2
3
A
= 1
V
V
V
V
= 5
= 1 V
= 1 V
DD
IC
O
V
R
C
= 2.5 V
I(PP)
= 10 kΩ
= 20 pF
= 25°C
L
L
2.5
No Load
T
A
2
1.5
1
0.5
1
0
0
0
2
4
6
8
10
– Supply Voltage – V
DD
12
14
16
–75 – 50 – 25
0
25 50 75 100 125 150
V
T
A
– Free-Air Temperature – °C
Figure 15
Figure 16
12
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TYPICAL CHARACTERISTICS
SLEW RATE
vs
MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
FREQUENCY
8
7
6
5
4
3
2
5
4
3
V
R
= 5 V
= 10 kΩ
V
V
= 5 V
DD
L
DD
= 1 V
I(PP)
= 1
A
V
R
C
= 10 kΩ
= 20 pF
L
L
V
= 5 V
DD
2
1
0
T
A
= –40°C
T
A
= 25°C
T
= 150°C
A
1
0
10
100
1000
10000
–75 – 50 – 25
0
25 50 75 100 125 150
f – Frequency – kHz
T
A
– Free-Air Temperature – °C
Figure 17
Figure 18
UNITY-GAIN BANDWIDTH
vs
UNITY-GAIN BANDWIDTH
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
2.5
3.5
V
= 5 V
V = 10 mV
DD
I
V = 10 mV
R
C
T
= 10 kΩ
= 20 pF
= 25°C
I
L
L
R
C
= 10 kΩ
= 20 pF
L
L
2.9
2.3
A
2
1.7
1.5
1.1
0.5
1
0
2
4
6
8
10
12
14
16
–75 – 50 – 25
0
25 50 75 100 125 150
T
A
– Free-Air Temperature – °C
V
DD
– Supply Voltage – V
Figure 19
Figure 20
13
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TYPICAL CHARACTERISTICS
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
7
6
5
4
3
2
1
10
10
10
10
10
10
10
V
R
C
= 5 V
= 10 kΩ
= 20 pF
= 25°C
DD
L
L
T
A
0°
30°
60°
A
VD
90°
Phase Shift
120°
150°
180°
1
0.1
10
100
1 k
10 k
100 k
1 M
10 M
f – Frequency – Hz
Figure 21
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
PHASE MARGIN
vs
SUPPLY VOLTAGE
53°
52°
51°
50°
60°
V
= 5 V
DD
V = 10 mV
58°
56°
54°
I
R
C
= 10 kΩ
= 20 pF
L
L
52°
50°
48°
46°
44°
42°
40°
49°
48°
47°
V = 10 mV
I
R
C
T
A
= 10 kΩ
= 20 pF
= 25°C
L
L
46°
45°
0
2
4
6
8
10
12
14
16
–75 –50 –25
0
25
50
75 100 125 150
V
DD
– Supply Voltage – V
T
A
– Free-Air Temperature – °C
Figure 22
Figure 23
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TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
EQUIVALENT INPUT NOISE VOLTAGE
vs
LOAD CAPACITANCE
FREQUENCY
400
350
300
250
200
150
100
50
50°
45°
V
= 5 V
= 20 Ω
= 25°C
V
= 5 V
DD
S
DD
R
T
V = 10 mV
I
R
= 10 kΩ
= 25°C
A
L
T
A
40°
35°
30°
25°
0
0
20
40
60
80
100
1
10
100
1000
f – Frequency – Hz
C
– Load Capacitance – pF
L
Figure 24
Figure 25
15
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PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLC2810Z is optimized for single-supply operation, circuit configurations used for the various tests
often present some inconvenience since the input signal, in many cases, must be offset from ground. This
inconvenience can be avoided by testing the device with split supplies and the output load tied to the negative
rail. A comparison of single-supply and split-supply test circuits is shown below. The use of either circuit gives
the same result.
V
DD
V
DD+
–
+
–
+
V
O
V
O
V
I
V
I
C
R
L
C
L
L
R
L
V
DD–
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 26. Unity-Gain Amplifier
2 kΩ
2 kΩ
V
DD
V
DD+
20 Ω
–
+
–
1/2 V
V
O
V
O
DD
+
20 Ω
20 Ω
20 Ω
V
DD–
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 27. Noise-Test Circuit
10 kΩ
10 kΩ
V
DD+
V
DD
100 Ω
100 Ω
V
I
V
–
+
–
+
I
V
O
V
O
1/2 V
DD
C
C
L
L
V
DD–
(a) SINGLE SUPPLY
(b) SPLIT SUPPLY
Figure 28. Gain-of-100 Inverting Amplifier
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PARAMETER MEASUREMENT INFORMATION
input bias current
Because of the high input impedance of the TLC2810Z operational amplifier, attempts to measure the input bias
current can result in erroneous readings. The bias current at normal ambient temperature is typically less than
1 pA, a value that is easily exceeded by leakages on the test socket. Two suggestions are offered to avoid
erroneous measurements:
1. Isolate the device from other potential leakage sources. Use a grounded shield around and between the
device inputs (see Figure 29). Leakages that would otherwise flow to the inputs are shunted away.
2. Compensate for the leakage of the test socket by actually performing an input bias current test (using a
picoammeter) with no device in the test socket. The actual input bias current can then be calculated by
subtracting the open-socket leakage readings from the readings obtained with a device in the test socket.
One word of caution: many automatic testers as well as some bench-top operational amplifier testers use the
servo-loop technique with a resistor in series with the device input to measure the input bias current (the voltage
drop across the series resistor is measured and the bias current is calculated). This method requires that a
device be inserted into a test socket to obtain a correct reading: therefore, an open-socket reading is notfeasible
using this method.
8
5
V = V
IC
1
4
Figure 29. Isolation Metal Around Device Inputs (P package)
low-level output voltage
To obtain low-supply-voltage operation, some compromise is necessary in the input stage. This compromise
results in the device low-level output being dependent on both the common-mode input voltage level as well
as the differential input voltage level. When attempting to correlate low-level output readings with those quoted
in the electrical specifications, these two conditions should be observed. If conditions other than these are to
be used, please refer to the Typical Characteristics of this data sheet.
input offset voltage temperature coefficient
Erroneous readings often result from attempts to measure temperature coefficient of input offset voltage. This
parameter is actually a calculation using input offset voltage measurements obtained at two different
temperatures. When one (or both) of the temperatures is below freezing, moisture can collect on both the device
and the test socket. This moisture results in leakage and contact resistance that can cause erroneous input
offset voltage readings. The isolation techniques previously mentioned have no effect on the leakage since the
moisture also covers the isolation metal itself, thereby rendering it useless. It is suggested that these
measurements be performed at temperatures above freezing to minimize error.
full-power response
Full-power response, the frequency above which the operational amplifier slew rate limits the output voltage
swing, is often specified two ways: full-linear response and full-peak response. The full-linear response is
generallymeasuredbymonitoringthedistortionleveloftheoutputwhileincreasingthefrequencyofasinusoidal
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full-power response (continued)
input signal until the maximum frequency above which the output contains significant distortion is found. The
full-peak response is defined as the maximum output frequency, without regard to distortion, above which full
peak-to-peak output swing cannot be maintained.
Because there is no industry-wide accepted value for significant distortion, the full-peak response is specified
in this data sheet and is measured using the circuit of Figure 26. The initial setup involves the use of a sinusoidal
input to determine the maximum peak-to-peak output of the device (the amplitude of the sinusoidal wave is
increased until clipping occurs). The sinusoidal wave is then replaced with a square wave of the same
amplitude. Thefrequencyisthenincreaseduntilthemaximumpeak-to-peakoutputcannolongerbemaintained
(Figure 30). A square wave is used to allow a more accurate determination of the point at which the maximum
peak-to-peak output is reached.
(a) f = 100 Hz
(b) B
OM
> f > 100 Hz
(c) f = B
OM
(d) f > B
OM
Figure 30. Full-Power-Response Output Signal
test time
Inadequate test time is a frequent problem, especially when testing CMOS devices in a high-volume,
short-test-time environment. Internal capacitances are inherently higher in CMOS than in bipolar and BiFET
devices; hence, CMOS devices require longer test times than their bipolar and BiFET counterparts. The
problem becomes more pronounced with reduced power supply levels and lower temperatures.
18
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APPLICATION INFORMATION
V
DD
single-supply operation
While the TLC2810Z performs well using
dual-power supplies (also called balanced or split
supplies), the design is optimized for single-
supply operation. This includes an input common-
mode voltage range that encompasses ground as
well as an output voltage range that pulls down to
ground. The supply voltage range extends down
to 4 V, thus allowing operation with supply levels
commonly available for TTL and CMOS.
R2
R1
V
I
–
V
O
+
TLE2426
V
V
V
DD
I
R2
R1
DD
2
V
(
)
O
2
Many single-supply applications require that a
voltage be applied to one input to establish a
reference level that is above ground. This virtual
ground can be generated using two large
resistors, but a preferred technique is to use a
Figure 31. Inverting Amplifier With Voltage
Reference
virtualgroundgeneratorsuchastheTLE2426(seeFigure31). TheTLE2426suppliesanaccuratevoltageequal
to V /2, while consuming very little power and is suitable for supply voltages of greater than 4 V.
DD
The TLC2810Z works well in conjunction with digital logic. However, when powering both linear devices and
digital logic from the same power supply, the following precautions are recommended:
1. Power the linear devices from separate bypassed supply lines (see Figure 32). Otherwise, the linear
device supply rails can fluctuate due to voltage drops caused by high switching currents in the digital logic.
2. Use proper bypass techniques to reduce the probability of noise-induced errors. Single capacitive
decoupling is often adequate. However, RC decoupling may be necessary in high-frequency applications.
–
Power
Supply
Logic
Logic
Logic
Output
+
(a) COMMON SUPPLY RAILS
–
+
Power
Supply
Logic
Logic
Logic
Output
(b) SEPARATE BYPASSED SUPPLY RAILS (preferred)
Figure 32. Common Versus Separate Supply Rails
19
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APPLICATION INFORMATION
input characteristics
The TLC2810Z is specified with a minimum and a maximum input voltage that, if exceeded at either input, could
cause the device to malfunction. Exceeding this specified range is a common problem, especially in
single-supply operation. The lower range limit includes the negative rail, while the upper range limit is specified
at V
–1 V at T = 25°C and at V – 1.2 V at all other temperatures.
DD
A DD
The use of the polysilicon-gate process and the careful input circuit design give the TLC2810Z very good input
offset voltage drift characteristics relative to conventional metal-gate processes. Offset voltage drift in CMOS
devices is influenced by threshold voltage shifts caused by polarization of the phosphorus dopant implanted
in the oxide. Placing the phosphorus dopant in a conductor (such as a polysilicon gate) alleviates the
polarization problem, thus reducing threshold voltage shifts by more than an order of magnitude. The offset
voltage drift with time has been calculated to be typically 0.1 µV/month, including the first month of operation.
Because of the extremely high input impedance and resulting low-bias current requirements, the TLC2810Z is
well suited for low-level signal processing; however, leakage currents on printed-circuit boards and sockets can
easily exceed bias-current requirements and cause a degradation in device performance. It is good practice
to include guard rings around inputs (similar to those of Figure 29 in the Parameter Measurement Information
section). These guards should be driven from a low-impedance source at the same voltage level as the
common-mode input (see Figure 33).
Unused amplifiers should be connected as grounded voltage followers to avoid possible oscillation.
V
I
–
+
–
+
–
+
V
O
V
O
V
O
V
I
V
I
(c) UNITY-GAIN AMPLIFIER
(a) NONINVERTING AMPLIFIER
(b) INVERTING AMPLIFIER
Figure 33. Guard-Ring Schemes
noise performance
The noise specifications in operational amplifier circuits are greatly dependent on the current in the first-stage
differential amplifier. The low input bias current requirements of the TLC2810Z results in a very low noise
current, which is insignificant in most applications. This feature makes the devices especially favorable over
bipolar devices when using values of circuit impedance greater than 50 kΩ since bipolar devices exhibit greater
noise currents.
20
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APPLICATION INFORMATION
feedback
Operational amplifier circuits nearly always
employ feedback and, since feedback is the first
prerequisite for oscillation, a little caution is
appropriate. Most oscillation problems result from
driving capacitive loads and ignoring stray input
capacitance. A small-value capacitor connected
in parallel with the feedback resistor is an effective
remedy (see Figure 34). The value of this
capacitor is optimized empirically.
–
+
Figure 34. Compensation for Input
Capacitance
electrostatic discharge protection
The TLC2810Z incorporates an internal electrostatic discharge (ESD) protection circuit that prevents functional
failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2. Care should be exercised,
however, when handling these devices, as exposure to ESD may result in the degradation of the device
parametric performance. The protection circuit also causes the input bias currents to be temperature dependent
and have the characteristics of a reverse-biased diode.
latch-up
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC2810Z
inputs and outputs are designed to withstand –100-mA surge currents without sustaining latch-up; however,
techniques should be used to reduce the chance of latch-up whenever possible. Internal protection diodes
should not by design be forward biased. Applied input and output voltages should not exceed the supply voltage
by more than 300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply
transients should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails
as close to the device as possible.
The current path established if latch-up occurs is usually between the positive supply rail and ground and can
be triggered by surges on the supply lines and/or voltages on either the output or inputs that exceed the supply
voltage. Once latch-up occurs, the current flow is limited only by the impedance of the power supply and the
forward resistance of the parasitic thyristor and usually results in the destruction of the device. The chance of
latch-up occurring increases with increasing temperature and supply voltages.
21
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APPLICATION INFORMATION
V
DD
output characteristics
The output stage of the TLC2810Z is designed to
sink and source relatively high amounts of current
(see Typical Characteristics). If the output is
subjected to a short-circuit condition, this high-
current capability can cause device damage
undercertainconditions. Outputcurrentcapability
increases with supply voltage.
R
P
L
I
I
V
F
V
V
I
P
–
+
DD
O
I
R
I
P
I
I
L
P
V
O
= Pullup Current
Required by the
Operational Amplifier
(typically 500 µA)
P
F
R
2
I
R
R
L
1
Although the TLC2810Z possesses excellent
high-level output voltage and current capability,
methods are available for boosting this capability
if needed. The simplest method involves the use
Figure 35. Resistive Pullup to Increase V
OH
of a pullup resistor (R )connectedfromtheoutput
P
to the positive supply rail (see Figure 35). There
are two disadvantages to the use of this circuit.
First, the NMOS pulldown transistor, N4 (see
equivalent schematic), must sink a comparatively
largeamountofcurrent. Inthiscircuit, N4behaves
like a linear resistor with an on-resistance
between approximately 60 Ω and 180 Ω,
depending on how hard the operational amplifier
2.5 V
–
V
O
+
V
I
C
L
input is driven. With very low values of R , a
voltage offset from 0 V at the output occurs.
T
= 25°C
P
A
f = 1 kHz
= 1 V
V
I(PP)
Secondly, pullup resistor R acts as a drain load
P
–2.5 V
to N4, and the gain of the operational amplifier is
reduced at output voltage levels where N5 is not
supplying the output current.
Figure 36. Test Circuit for Output Characteristics
All operating characteristics of the TLC2810Z are measured using a 20-pF load. The devices can drive higher
capacitive loads; however, as output load capacitance increases, the resulting response pole occurs at lower
frequencies, thereby causing ringing, peaking, or even oscillation (see Figure 37). In many cases, adding some
compensation in the form of a series resistor in the feedback loop alleviates the problem.
(a) C = 20 pF, R = NO LOAD
(c) C = 150 pF, R = NO LOAD
L L
(b) C = 130 pF, R = NO LOAD
L
L
L
L
Figure 37. Effect of Capacitive Loads
22
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