TLC352CPW [TI]

DUAL COMPARATOR, 6500uV OFFSET-MAX, 650ns RESPONSE TIME, PDSO8;
TLC352CPW
型号: TLC352CPW
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

DUAL COMPARATOR, 6500uV OFFSET-MAX, 650ns RESPONSE TIME, PDSO8

放大器 光电二极管
文件: 总9页 (文件大小:138K)
中文:  中文翻译
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TLC352  
LinCMOS DUAL DIFFERENTIAL COMPARATOR  
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990  
TLC352C, TLC352I . . . D OR P PACKAGE  
TLC352M . . . JG PACKAGE  
(TOP VIEW)  
Single- or Dual-Supply Operation  
Wide Range of Supply Voltages  
1.5 V to 18 V  
Very Low Supply Current Drain  
150 µA Typ at 5 V  
1OUT  
1IN–  
1IN+  
GND  
V
DD  
1
2
3
4
8
7
6
5
2OUT  
2IN–  
2IN+  
65 µA Typ at 1.4 V  
Built-In ESD Protection  
12  
High Input Impedance . . . 10 Typ  
Extremely Low Input Bias Current 5 pA Typ  
Ultrastable Low Input Offset Voltage  
TLC352M . . . FK PACKAGE  
(TOP VIEW)  
Input Offset Voltage Change at Worst-Case  
Input Conditions Typically 0.23 µV/ Month,  
Including the First 30 Days  
3
2
1
20 19  
18  
Common-Mode Input Voltage Range  
Includes Ground  
NC  
NC  
1IN–  
NC  
4
5
6
7
8
2OUT  
NC  
17  
16  
15  
14  
Outputs Compatible With TTL, MOS, and  
CMOS  
2IN–  
NC  
1IN+  
NC  
Pin-Compatible With LM393  
9 10 11 12 13  
description  
This device is fabricated using LinCMOS  
technology and consists of two independent  
voltage comparators, each designed to operate  
from a single power supply. Operation from dual  
supplies is also possible if the difference between  
the two supplies is 1.4 V to 18 V. Each device  
features extremely high input impedance  
NC — No Internal connection  
symbol (each comparator)  
IN+  
IN–  
OUT  
12  
(typically greater than 10 ), which allows direct  
interface to high-impedance sources. The output  
are n-channel open-drain configurations and can  
beconnectedtoachievepositive-logicwired-AND  
relationships. The capability of the TLC352 to  
operate from 1.4-V supply makes this device ideal  
for low-voltage battery applications.  
The TLC352 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 2000-V  
ESD rating tested under MIL-STD-883C, Method 3015. However, care should be exercised in handling this  
device as exposure to ESD may result in degradation of the device parametric performance.  
The TLC352C is characterized for operation from 0°C to 70°C. The TLC352I is characterized for operation over  
the industrial temperature range of – 40°C to 85°C. The TLC352M is characterized for operation over the full  
military temperature range – 55°C to 125°C.  
LinCMOS is a trademark of Texas Instruments Incorporated.  
Copyright 1990, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLC352  
LinCMOS DUAL DIFFERENTIAL COMPARATOR  
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990  
AVAILABLE OPTIONS  
PACKAGE  
CHIP-CARRIER  
V
max  
IO  
T
SMALL-OUTLINE  
CERAMIC DIP  
(JG)  
PLASTIC DIP  
(P)  
A
AT 25°C  
(D)  
TLC352CD  
TLC352ID  
(FK)  
0°C to 70°C  
– 40°C to 85°C  
– 55°C to 125°C  
5 mV  
5 mV  
5 mV  
TLC352CP  
TLC352IP  
TLC352MFK  
TLC352MJG  
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC352 CDR).  
equivalent schematic (each comparator)  
Common to All Channels  
V
DD  
OUT  
GND  
IN–  
IN+  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLC352  
LinCMOS DUAL DIFFERENTIAL COMPARATOR  
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage, V  
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V  
DD  
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V  
ID  
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V  
I
DD  
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 18 V  
I
Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V  
O
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA  
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA  
O
Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited  
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table  
Operating free-air temperature range, T TLC352C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C  
A
TLC352I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C  
TLC352M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C  
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C  
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package . . . . . . . . . . . . . . . . . 260°C  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. All voltage values except differential voltages are with respect to the network ground.  
2. Differential voltages are at IN+ with respect to IN –.  
3. Short circuits from outputs to V  
can cause excessive heating and eventual device destruction.  
DD  
DISSIPATION RATING TABLE  
T
25°C  
DERATING  
FACTOR  
DERATE  
ABOVE T  
T
= 70°C  
T
= 85°C  
T = 125°C  
A
A
A
A
PACKAGE  
POWER RATING  
POWER RATING POWER RATING POWER RATING  
A
D
FK  
JG  
P
500 mW  
500 mW  
500 mW  
500 mW  
5.8 mW/°C  
11.0 mW/°C  
8.4 mW/°C  
N/A  
64°C  
104°C  
90°C  
N/A  
464 mW  
500 mW  
500 mW  
500 mW  
377 mW  
500 mW  
500 mW  
500 mW  
N/A  
275 mW  
210 mW  
N/A  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
recommended operating conditions  
TLC352C  
TLC352I  
TLC352M  
UNIT  
V
MIN  
1.4  
0
MAX  
MIN  
1.4  
0
MAX  
MIN  
1.4  
0
MAX  
Supply voltage, V  
16  
3.5  
8.5  
70  
16  
3.5  
8.5  
85  
16  
3.5  
8.5  
125  
DD  
V
V
= 5 V  
DD  
Common-mode input voltage, V  
V
IC  
Operating free-air temperature, T  
= 10 V  
0
0
0
DD  
0
– 40  
– 55  
°C  
A
electrical characteristics at specified free-air temperature, V  
= 1.4 V (unless otherwise noted)  
DD  
TLC352C  
MIN TYP  
2
TLC352I  
MIN TYP  
2
TLC352M  
PARAMETER  
Input offset voltage  
Input offset current  
Input bias current  
TEST CONDITIONS  
T
A
UNIT  
MAX  
5
MAX  
MIN TYP  
MAX  
5
25°C  
5
7
2
V
V
IC  
= V min, See Note 4  
ICR  
mV  
IO  
Full range  
25°C  
6.5  
10  
1
5
1
5
1
5
pA  
nA  
pA  
nA  
I
IO  
MAX  
0.3  
0.6  
1
2
10  
20  
25°C  
I
IB  
MAX  
Common-mode input voltage  
range  
0 to  
0.2  
0 to  
0.2  
0 to  
0.2  
V
V
Full range  
V
ICR  
25°C  
Full range  
25°C  
100  
200  
200  
100  
200  
200  
100  
200  
200  
Low-level output voltage  
mV  
mA  
µA  
OL  
I
I
Low-level output current  
V
V
= – 0.5 V,  
= 0.5 V,  
V
= 0.3 V  
1
1.6  
65  
1
1.6  
65  
1
1.6  
65  
OL  
ID  
OL  
25°C  
150  
200  
150  
200  
150  
200  
Supply current (two comparators)  
No load  
DD  
ID  
Full range  
All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC352C, – 40°C to 85°C for TLC352I, – 55°C to 125°C  
for TLC352M. IMPORTANT: See Parameter Measurement Information.  
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 1.25 V or below 150 mV with a 10-kresistor between the output and V . They  
DD  
can be verified by applying the limit value to the input and checking for the appropriate output state.  
electrical characteristics at specified free-air temperature, V  
= 5 V (unless otherwise noted)  
DD  
TLC352C  
TLC352I  
TYP  
1
TLC352M  
PARAMETER  
TEST CONDITIONS  
T
A
UNIT  
MIN  
TYP  
MAX  
5
MIN  
MAX  
MIN  
TYP  
MAX  
5
25°C  
Full range  
25°C  
1
5
7
1
V
IO  
Input offset voltage  
Input offset current  
Input bias current  
V
IC  
= V  
min, See Note 5  
ICR  
mV  
6.5  
10  
1
5
1
5
1
5
pA  
nA  
pA  
nA  
I
IO  
MAX  
0.3  
0.6  
1
2
10  
20  
25°C  
I
IB  
MAX  
0 to  
0 to  
0 to  
25°C  
V
– 1  
V
– 1  
V
– 1  
DD  
0 to  
– 1.5  
DD  
0 to  
– 1.5  
DD  
0 to  
– 1.5  
Common-mode  
input voltage range  
V
ICR  
V
Full range  
V
V
V
DD  
DD  
DD  
V
V
= 5 V  
25°C  
Full range  
25°C  
0.1  
0.1  
0.1  
nA  
High-level output  
current  
OH  
I
V
ID  
= 1 V  
OH  
= 15 V  
1
400  
700  
1
400  
700  
1
400  
700  
µA  
OH  
150  
150  
150  
Low-level output  
voltage  
V
V
ID  
V
ID  
V
ID  
= 1 V,  
I
= 4 mA  
mV  
mA  
mA  
OL  
OL  
Full range  
Low-level output  
current  
I
I
= – 1 V,  
= 1 V,  
V
OL  
= 1.5 V  
25°C  
6
16  
6
16  
6
16  
OL  
25°C  
0.15  
0.3  
0.4  
0.15  
0.3  
0.4  
0.15  
0.3  
0.4  
Supply current  
(two comparators)  
No load  
DD  
Full range  
All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC352C, – 40°C to 85°C for TLC352I, – 55°C to 125°C  
for TLC352M. IMPORTANT: See Parameter Measurement Information.  
NOTE 5: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kresistor between the output and V . They  
DD  
can be verified by applying the limit value to the input and checking for the appropriate output state.  
switching characteristics, V  
= 5 V, T = 25°C  
A
DD  
TLC352C, TLC352I  
TLC352M  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
TYP  
650  
200  
MAX  
R
C
connected to 5 V through 5.1 k,,  
100-mV input step with 5-mV overdrive  
TTL-level input step  
L
L
Response time  
ns  
= 15 pF ,  
See Note 6  
C
includes probe and jig capacitance.  
L
NOTE 6: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.  
TLC352  
LinCMOS DUAL DIFFERENTIAL COMPARATOR  
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990  
PARAMETER MEASUREMENT INFORMATION  
The digital output stage of the TLC352 can be damaged if it is held in the linear region of the transfer curve.  
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force  
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the  
following alternative for measuring parameters such as input offset voltage, common-mode rejection, etc., are  
offered.  
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown  
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With  
the input polarity reversed, the output should be low.  
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can  
be slewed as shown in Figure 1(b) for the V  
accuracy.  
test, rather than changing the input voltages, to provide greater  
ICR  
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the  
differential input voltage while monitoring the output state. When the applied input voltage differential is equal but  
opposite in polarity to the input offset voltage, the output changes state.  
5 V  
1 V  
5.1 kΩ  
5.1 kΩ  
+
+
Applied V  
Limit  
Applied V  
Limit  
IO  
IO  
V
O
V
O
– 4 V  
(a) V WITH V = 0  
IO IC  
(b) V WITH V = 4 V  
IO IC  
Figure 1. Method for Verifying That Input Offset Voltage Is Within Specified Limits  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLC352  
LinCMOS DUAL DIFFERENTIAL COMPARATOR  
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990  
PARAMETER INFORMATION  
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the  
comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a  
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual  
dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input  
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop  
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which  
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input  
exactly equals the input offset voltage.  
Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement  
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is  
suggested that their tolerance level be 1% or lower.  
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and  
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage  
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from  
the measurement obtained with a device in the socket to obtain the actual input current of the device.  
R5  
1.8 kΩ, 1%  
V
DD  
C3 0.68 µF  
U1b  
1/4 TLC274CN  
C2  
U1c  
1/4 TLC274CN  
1 µF  
R6  
Buffer  
+
5.1 kΩ  
+
DUT  
V
IO  
(X100)  
R7  
1MΩ  
R4  
47 kΩ  
R1  
Integrator  
240 kΩ  
R8  
1.8 k, 1%  
C4  
0.1 µF  
U1a  
+
1/4 TLC274CN  
C1  
0.1 µF  
Triangle  
Generator  
R9  
10 k, 1%  
R10  
100 , 1%  
R2  
10 kΩ  
R3  
100 kΩ  
Figure 2. Circuit for Input Offset Voltage Measurement  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
TLC352  
LinCMOS DUAL DIFFERENTIAL COMPARATOR  
SLCS016 – SEPTEMBER 1985 – REVISED OCTOBER 1990  
PARAMETER MEASUREMENT INFORMATION  
Response time is defined as the interval between the application of an input step function and the instant when the  
output reaches 50% of its maximum value. Response time, low-to-high-level output, is measured from the leading  
edge of the input pulse, while response time, high-to-low level output, is measured from the trailing edge of the input  
pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The  
offset voltage should be balanced by the adjustment at the inverting input (as shown in Figure 3) so that the circuit  
is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change  
state.  
V
DD  
5.1 kΩ  
1 µF  
Pulse Generator  
DUT  
50 Ω  
C
L
(see Note A)  
1 V  
Input  
Offset Voltage  
Compensation  
Adjustment  
10 Ω  
10 Turn  
1 kΩ  
0.1 mF  
– 1 V  
TEST CIRCUIT  
Overdrive  
Overdrive  
Input  
Input  
100 mV  
100 mV  
90%  
50%  
10%  
90%  
10%  
Low-to-High-  
Level Output  
50 %  
High-to-Low-  
Level Output  
t
r
t
t
f
t
PLH  
PHL  
VOLTAGE WAVEFORMS  
NOTE A: C includes probe and jig capacitance.  
L
Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL  
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR  
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER  
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO  
BE FULLY AT THE CUSTOMER’S RISK.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
intellectual property right of TI covering or relating to any combination, machine, or process in which such  
semiconductor products or services might be or are used. TI’s publication of information regarding any third  
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.  
Copyright 1998, Texas Instruments Incorporated  

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