TLC372Q [TI]
LinCMOSE DUAL DIFFERENTIAL COMPARATORS; LinCMOSE双差分比较仪
| 型号： | TLC372Q |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LinCMOSE DUAL DIFFERENTIAL COMPARATORS |
| 文件： | 总12页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
TLC372C, TLC372I, TLC372M, TLC372Q
D, P, OR PW PACKAGE
TLC372M . . . JG PACKAGE
(TOP VIEW)
Single or Dual-Supply Operation
Wide Range of Supply Voltages
2 V to 18 V
Very Low Supply Current Drain
1OUT
1IN–
1IN+
GND
V
CC
1
2
3
4
8
7
6
5
150 µA Typ at 5 V
2OUT
2IN–
2IN+
Fast Response Time . . . 200 ns Typ for
TTL-Level Input Step
Built-in ESD Protection
12
High Input Impedance . . . 10 Ω Typ
TLC372M . . . FK PACKAGE
(TOP VIEW)
Extremely Low Input Bias Current
5 pA Typ
Ultrastable Low Input Offset Voltage
Input Offset Voltage Change at Worst-Case
Input Conditions Typically 0.23 µV/Month,
Including the First 30 Days
3
2
1
20 19
18
NC
NC
1IN–
NC
4
5
6
7
8
2OUT
NC
17
16
15
14
Common-Mode Input Voltage Range
Includes Ground
2IN–
NC
1IN+
NC
Output Compatible With TTL, MOS, and
CMOS
9 10 11 12 13
Pin-Compatible With LM393
description
NC – No internal connection
This device is fabricated using LinCMOS
technology and consists of two independent
voltage comparators, each designed to operate
from a single power supply. Operation from dual
supplies is also possible if the difference between
the two supplies is 2 V to 18 V. Each device
features extremely high input impedance
symbol (each comparator)
IN+
IN –
OUT
12
(typically greater than 10 Ω), allowing direct
interfacing with high-impedance sources. The
outputs are n-channel open-drain configurations
and can be connected to achieve positive-logic
wired-AND relationships.
The TLC372 has internal electrostatic discharge (ESD) protection circuits and has been classified with a 1000-V
ESD rating using human body model testing. However, care should be exercised in handling this device as
exposure to ESD may result in a degradation of the device parametric performance.
The TLC372C is characterized for operation from 0°C to 70°C. The TLC372I is characterized for operation from
–40°C to 85°C. The TLC372M is characterized for operation over the full military temperature range of –55°C
to 125°C. The TLC372Q is characterized for operation from –40°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
equivalent schematic (each comparator)
Common to All Channels
V
DD
OUT
GND
IN +
IN –
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
FORM
(Y)
V
max
IO
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
PLASTIC
DIP
T
A
TSSOP
(PW)
AT 25°C
(JG)
(P)
0°C to 70°C
–40°C to 85°C
–55°C to 125°C
–40°C to 125°C
5 mV
5 mV
5 mV
5 mV
TLC372CD
TLC372ID
TLC372MD
TLC372QD
—
—
—
—
TLC372CP
TLC372IP
TLC372MP
TLC372QP
TLC372CPW
TLC372Y
—
—
—
—
—
—
TLC372MFK
—
TLC372MJG
—
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLC372CDR).
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
TLC372Y chip information
These chips, when properly assembled, display characteristics similar to the TLC372C. Thermal compression
or ultrasonic bonding can be used on the doped-aluminum bonding pads. Chips can be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
V
CC+
(8)
(3)
(2)
(7)
(6)
(5)
1IN+
1IN–
+
–
(1)
1OUT
(5)
(6)
+
2IN+
2IN–
(7)
2OUT
–
(4)
(8)
57
(4)
GND
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 3.6 × 3.6 MINIMUM
T max = 150°C
J
TOLERANCES ARE ±10%.
(2)
(3)
(1)
ALL DIMENSIONS ARE IN MILS.
PIN (4) INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
57
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
DD
Differential input voltage, V (see Note 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 18 V
ID
I
Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
O
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
I
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
O
Duration of output short circuit to ground (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : TLC372C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLC372I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
TLC372M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
TLC372Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values except differential voltages are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN –.
3. Short circuits from outputs to V
can cause excessive heating and eventual device destruction.
DD
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING
FACTOR
DERATE
ABOVE T
T
= 70°C
T
= 85°C
T = 125°C
A
A
A
A
PACKAGE
POWER RATING
POWER RATING POWER RATING POWER RATING
A
D
FK
JG
P
500 mW
5.8 mW/°C
11.0 mW/°C
8.4 mW/°C
8.0 mW/°C
4.2 mW/°C
64°C
104°C
90°C
87°C
25°C
464 mW
500 mW
500 mW
500 mW
336 mW
377 mW
500 mW
500 mW
500 mW
N/A
145 mW
275 mW
210 mW
200 mW
N/A
500 mW
500 mW
500 mW
PW
525 mW
recommended operating conditions
TLC372C
TLC372I
TLC372M
TLC372Q
UNIT
V
MIN
3
MAX
16
MIN
3
MAX
16
MIN
4
MAX
MIN
4
MAX
Supply voltage, V
DD
16
3.5
8.5
125
16
3.5
8.5
125
V
V
= 5 V
0
3.5
8.5
70
0
3.5
8.5
85
0
0
DD
Common-mode input voltage, V
V
IC
= 10 V
0
0
0
0
DD
Operating free-air temperature, T
0
–40
–55
–40
°C
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, V
= 5 V (unless otherwise noted)
DD
TLC372C
TYP MAX
TLC372I
TYP MAX
TLC372M, TLC372Q
†
PARAMETER
TEST CONDITIONS
UNIT
T
A
MIN
MIN
MIN
TYP MAX
25°C
Full range
25°C
1
1
5
5
1
5
7
1
1
5
5
V
Input offset voltage
Input offset current
Input bias current
V
IC
= V
min, See Note 4
ICR
mV
IO
6.5
10
1
5
pA
nA
pA
nA
I
IO
MAX
0.3
0.6
1
2
10
20
25°C
I
IB
MAX
0 to
–1
0 to
0 to
25°C
V
V
–1
V
–1
DD
0 to
–1.5
DD
0 to
–1.5
DD
0 to
–1.5
Common-mode input
voltage range
V
ICR
V
Full range
V
V
V
DD
DD
DD
V
V
= 5 V
25°C
Full range
25°C
0.1
0.1
0.1
nA
OH
I
High-level output current
V
ID
= 1 V
OH
= 15 V
1
400
700
1
400
700
3
400
700
µA
OH
150
150
150
V
Low-level output voltage
Low-level output current
V
ID
V
ID
V
ID
= –1 V,
= –1 V,
= 1 V,
I
= 4 mA
mV
mA
µA
OL
OL
Full range
25°C
I
I
V
OL
= 1.5 V
6
16
6
16
6
16
OL
25°C
150
300
400
150
300
400
150
300
400
Supply current
(two comparators)
No load
DD
Full range
†
All characteristics are measured with zero common-mode input voltage unless otherwise noted. Full range is 0°C to 70°C for TLC372C, –40°C to 85°C for TLC372I, and –55°C to
125°C for TLC372M and –40°C to 125°C for TLC372Q. IMPORTANT: See Parameter Measurement Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor between the output and V . They can
DD
be verified by applying the limit value to the input and checking for the appropriate output state.
switching characteristics, V
= 5 V, T = 25°C
A
DD
PARAMETER
TEST CONDITIONS
100-mV input step with 5-mV overdrive
TTL-level input step
MIN
TYP
650
200
MAX
UNIT
‡
connected to 5 V through 5.1 kΩ, C = 15 pF ,
L
R
L
Response time
ns
See Note 5
‡
C
includes probe and jig capacitance.
L
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses 1.4 V.
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
electrical characteristics at specified free-air temperature, V
noted)
= 5 V, T = 25°C (unless otherwise
DD
A
TLC372Y
†
PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP
MAX
V
Input offset voltage
V
IC
= V min, See Note 4
1
1
5
5
mV
pA
pA
IO
ICR
I
I
Input offset current
Input bias current
IO
IB
0 to
–1
V
ICR
Common-mode input voltage range
V
V
DD
I
High-level output current
Low-level output voltage
Low-level output current
V
ID
V
ID
V
ID
V
ID
= 1 V,
V
= 5 V
0.1
150
16
nA
mV
mA
µA
OH
OH
= 4 mA
V
= –1 V,
= –1 V,
= 1 V,
I
400
300
OL
OL
I
I
V
= 1.5 V
6
OL
OL
No load
Supply current (two comparators)
150
DD
†
All characteristics are measured with zero common-mode input voltage unless otherwise noted. IMPORTANT: See Parameter Measurement
Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V or below 400 mV with a 10-kΩ resistor
between the output and V . They can be verified by applying the limit value to the input and checking for the appropriate output state.
DD
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLC372 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 1(b) for the V
accuracy.
test, rather than changing the input voltages, to provide greater
ICR
5 V
1 V
5.1 kΩ
5.1 kΩ
+
–
+
–
Applied V
Limit
IO
Applied V
Limit
IO
V
O
V
O
–4 V
(a) V WITH V = 0
IO IC
(b) V WITH V = 4 V
IO IC
Figure 1. Method for Verifying That Input Offset Voltage is Within Specified Limits
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal, but
opposite in polarity, to the input offset voltage, the output changes states.
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator into the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer, with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test, while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage divider R9 and R10 provides a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
C3
0.68 µF
V
DD
R5
1.8 kΩ, 1%
U1b
1/4 TLC274C
C2
1 µF
U1c
1/4 TLC274CN
R6
5.1 kΩ
Buffer
+
–
–
+
DUT
R7
1 MΩ
V
IO
(X100)
R4
47 kΩ
R1
240 kΩ
R8
1.8 kΩ, 1%
Integrator
C4
0.1 µF
U1a
–
+
1/4 TLC274CN
C1
0.1 µF
Triangle
Generator
R9
10 kΩ, 1%
R10
100 kΩ, 1%
R2
10 kΩ
R3
100 kΩ
Figure 2. Circuit for Input Offset Voltage Measurement
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
Response time is defined as the interval between the application of an input step function and the instant when the
output reaches 50% of its maximum value. Response time, low-to-high-level output, is measured from the leading
edge of the input pulse, while response time, high-to-low-level output, is measured from the trailing edge of the input
pulse. Response-time measurement at low input signal levels can be greatly affected by the input offset voltage. The
offset voltage should be balanced by the adjustment at the inverting input as shown in Figure 3, so that the circuit
is just at the transition point. Then a low signal, for example 105-mV or 5-mV overdrive, causes the output to change
state.
V
DD
1 µF
5.1 kΩ
Pulse
Generator
DUT
50 Ω
C
1 V
L
(see Note A)
Input Offset Voltage
10 Ω
Compensation Adjustment
10 Turn
1 kΩ
–1 V
0.1 µF
TEST CIRCUIT
Overdrive
100 mV
Input
Overdrive
Input
100 mV
90%
50%
10%
90%
50%
Low-to-High-
Level Output
High-to-Low-
Level Output
10%
t
t
f
r
t
t
PLH
PHL
VOLTAGE WAVEFORMS
NOTE A: C includes probe and jig capacitance.
L
Figure 3. Response, Rise, and Fall Times Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
PRINCIPLES OF OPERATION
LinCMOS process
The LinCMOS process is a Linear polysilicon-gate complementary-MOS process. Primarily designed for
single-supply applications, LinCMOS products facilitate the design of a wide range of high-performance
analog functions, from operational amplifiers to complex mixed-mode converters.
While digital designers are experienced with CMOS, MOS technologies are relatively new for analog designers.
This short guide is intended to answer the most frequently asked questions related to the quality and reliability
of LinCMOS products. Further questions should be directed to the nearest TI field sales office.
electrostatic discharge
CMOS circuits are prone to gate oxide breakdown when exposed to high voltages even if the exposure is only
for very short periods of time. Electrostatic discharge (ESD) is one of the most common causes of damage to
CMOS devices. It can occur when a device is handled without proper consideration for environmental
electrostatic charges, e.g. during board assembly. If a circuit in which one amplifier from a dual operational
amplifier is being used and the unused pins are left open, high voltages tends to develop. If there is no provision
for ESD protection, these voltages may eventually punch through the gate oxide and cause the device to fail.
To prevent voltage buildup, each pin is protected by internal circuitry.
Standard ESD-protection circuits safely shunt the ESD current by providing a mechanism whereby one or more
transistors break down at voltages higher than the normal operating voltages but lower than the breakdown
voltage of the input gate. This type of protection scheme is limited by leakage currents which flow through the
shunting transistors during normal operation after an ESD voltage has occurred. Although these currents are
small, on the order of tens of nanoamps, CMOS amplifiers are often specified to draw input currents as low as
tens of picoamps.
To overcome this limitation, TI design engineers developed the patented ESD-protection circuit shown in
Figure 4. This circuit can withstand several successive 1-kV ESD pulses, while reducing or eliminating leakage
currents that may be drawn through the input pins. A more detailed discussion of the operation of TI’s ESD-
protection circuit is presented on the next page.
All input and output pins on LinCMOS and Advanced LinCMOS products have associated ESD-protection
circuitry that undergoes qualification testing to withstand 1000 V discharged from a 100-pF capacitor through
a 1500-Ω resistor (human body model) and 200 V from a 100-pF capacitor with no current-limiting resistor
(charged device model). These tests simulate both operator and machine handling of devices during normal
test and assembly operations.
V
DD
R1
Input
To Protected Circuit
R2
Q1
Q2
D1
D2
D3
V
SS
Figure 4. LinCMOS ESD-Protection Schematic
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
PRINCIPLES OF OPERATION
input protection circuit operation
Texas Instruments patented protection circuitry allows for both positive-and negative-going ESD transients.
These transients are characterized by extremely fast rise times and usually low energies, and can occur both
when the device has all pins open and when it is installed in a circuit.
positive ESD transients
Initial positive charged energy is shunted through Q1 to V . Q1 turns on when the voltage at the input rises
SS
EB
above the voltage on the V
pin by a value equal to the V of Q1. The base current increases through R2
DD
with input current as Q1 saturates. The base current through R2 forces the voltage at the drain and gate of Q2
to exceed its threshold level (V ~ 22 V to 26 V) and turn Q2 on. The shunted input current through Q1 to V
T
SS
is now shunted through the n-channel enhancement-type MOSFET Q2 to V . If the voltage on the input pin
SS
continues to rise, the breakdown voltage of the zener diode D3 is exceeded, and all remaining energy is
dissipated in R1 and D3. The breakdown voltage of D3 is designed to be 24 to 27 V, which is well below the gate
oxide voltage of the circuit to be protected.
negative ESD transients
The negative charged ESD transients are shunted directly through D1. Additional energy is dissipated in R1
and D2 as D2 becomes forward biased. The voltage seen by the protected circuit is –0.3 V to –1 V (the forward
voltage of D1 and D2).
circuit-design considerations
LinCMOS products are being used in actual circuit environments that have input voltages that exceed the
recommended common-mode input voltage range and activate the input protection circuit. Even under normal
operation, these conditions occur during circuit power up or power down, and in many cases, when the device
is being used for a signal conditioning function. The input voltages can exceed V
only if the inputs are current limited. The recommended current limit shown on most product data sheets is
and not damage the device
ICR
±5 mA. Figures 5 and 6 show typical characteristics for input voltage versus input current.
Normal operation and correct output state can be expected even when the input voltage exceeds the positive
supply voltage. Again, the input current should be externally limited even though internal positive current limiting
is achieved in the input protection circuit by the action of Q1. When Q1 is on, it saturates and limits the current
to approximately 5-mA collector current by design. When saturated, Q1 base current increases with input
current. This base current is forced into the V
producing the current limiting effects shown in Figure 5. This internal limiting lasts only as long as the input
pin and into the device I
or the V
supply through R2
DD
DD
DD
voltage is below the V of Q2.
T
When the input voltage exceeds the negative supply voltage, normal operation is affected and output voltage
states may not be correct. Also, the isolation between channels of multiple devices (duals and quads) can be
severely affected. External current limiting must be used since this current is directly shunted by D1 and D2 and
no internal limiting is achieved. If normal output voltage states are required, an external input voltage clamp is
required (see Figure 7).
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC372, TLC372Q, TLC372Y
LinCMOS DUAL DIFFERENTIAL COMPARATORS
SLCS114B – NOVEMBER 1983 – REVISED MARCH 1999
PRINCIPLES OF OPERATION
circuit-design considerations (continued)
INPUT CURRENT
vs
INPUT CURRENT
vs
INPUT VOLTAGE
INPUT VOLTAGE
8
7
6
5
4
3
2
1
0
10
T
= 25°C
T
= 25°C
A
A
9
8
7
6
5
4
3
2
1
0
V
V
DD
+ 4
V
DD
+ 8
V
DD
+ 12
V
DD
– 0.3
V
– 0.5
V
DD
– 0.7
V
DD
– 0.9
DD
DD
Input Voltage – V
Input Voltage – V
Figure 5
Figure 6
V
DD
Positive Voltage Input Current LImit:
+V – V – 0.3 V
I
DD
5 mA
R =
I
R
I
R
L
Negative Voltage Input Current LImit:
–V – V – (–0.3 V)
V
I
+
I
DD
5 mA
R =
I
TLC372
–
V
ref
See Note A
NOTE A: If the correct output state is required when the negative input exceeds V , a schottky clamp is required.
SS
Figure 7. Typical Input Current-Limiting Configuration for a LinCMOS Comparator
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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