TLC5733AIPM [TI]
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER WITH HIGH-PRECISION CLAMP; 配合高精度夹具20 MSPS的3通道模拟数字转换器
| 型号： | TLC5733AIPM |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER WITH HIGH-PRECISION CLAMP |
| 文件： | 总24页 (文件大小：347K) |
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TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
3-Channel CMOS ADC
Analog Input Bandwidth . . . >14 MHz
5-V Single-Supply Operation or 5-V Analog
Supply with Digital Supply from
2.7 V to 5.25 V
Suitable for YUV or RGB Applications
Digital Clamp Optimized for NTSC or PAL
YUV Component
8-Bit Resolution
High-Precision Clamp . . . ±1 LSB
Automatic Clamp Pulse Generator
Output-Data Format Multiplexer
Low Power Consumption
Differential Linearity Error . . . ±0.5 LSB Max
Linearity Error . . . ±0.75 LSB Max
Maximum Conversion Rate
20 Megasamples per Second
(MSPS) Min
Analog Input Voltage Range
2 V
Min
I(PP)
64-Pin Shrink QFP Package
description
The TLC5733A is a 3-channel 8-bit semiflash analog-to-digital converter (ADC) that operates from a single 5-V
power supply. It converts a wide-band analog signal (such as a video signal) to digital data at sampling rates
up to 20 MSPS minimum. The TLC5733A contains a feed-back type high-precision clamp circuit for each ADC
†
channel for video (YUV) applications and a clamp pulse generator that detects COMPOSITE SYNC pulses
automatically. A clamp pulse can also be supplied externally. The output-data format multiplexer selects a ratio
of Y:U:V of 4:4:4, 4:1:1, or 4:2:2. For RGB applications, the 4:4:4 output format without clamp function can be
used. The TLC5733A is characterized for operation from –20°C to 75°C.
AVAILABLE OPTIONS
PACKAGE
T
A
QUAD FLATPACK
–20°C to 75°C
TLC5733AIPM
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
COMPOSITE SYNC refers to the externally generated synchronizing signal that is a combination of vertical and horizontal sync information
used in display and TV systems.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
PM PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
RB A
OE A
RB B
1
2
3
4
5
6
7
8
9
10
48
47
46
45
44
43
42
41
40
OE B
NT/PAL
TEST
QA DGND
AD8
MODE0
MODE1
QC DGND
CD1
AD7
CD2
AD6
CD3
AD5
CD4
AD4
39 CD5
38 CD6
37 CD7
AD3 11
AD2 12
13
14
15
16
36
35
34
33
AD1
CD8
QA DV
QC DV
OE C
RB C
DD
DD
DGND
QB DV
DD
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
functional block diagram
CLK A
8
8
8
ADC
AD1–8
AIN
(Sampling
Comparators)
RT A
Output Data
Latch
8
RB A
Clamp
Circuit
CLPV A
CLP OUT A
OE A
CLK B
8
8
8
BD1–8
BIN
ADC
(Sampling
Comparators)
Output Data
Latch
RT B
8
RB B
Clamp
Circuit
CLPV B
Multiplexer
For
CLP OUT B
OE B
Output Format
CLK C
8
8
8
CIN
CD1–8
ADC
(Sampling
Comparators)
RT C
Output Data
Latch
8
RB C
Clamp
Circuit
CLPV C
CLP OUT C
OE C
MODE0
MODE1
TEST
Output
Format
Selector
and Test
Clock
Generator
EXTCLP
CLPEN
Control For
INT/EXT
Clamp Circuit
NT/PAL
CLK
INIT
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
62
A AV
I
O
I
Analog supply voltage of ADC A
Data output of ADC A (LSB: AD1, MSB:AD8)
Analog input of ADC A
CC
AD8–AD1
6–13
63
AIN
B AV
CC
51
I
Analog supply voltage of ADC B
Data output of ADC B (LSB: BD1, MSB:BD8)
Analog input of ADC B
BD8–BD1
BIN
17–24
50
O
I
C AV
30
I
Analog supply voltage of ADC C
CC
CD8–CD1
36–43
O
Data output of ADC C (LSB:CD1, MSB: CD8)
When MODE0 = L, MODE1 = L, CD8 outputs MSB flag of BD8–BD5
When MODE0 = L, MODE1 = L, CD7 outputs MSB flag of BD8–BD5
When MODE0 = L, MODE1 = H, CD8 outputs B channel flag of CD8–BD1
When MODE0 = L, MODE1 = H, CD8 outputs B channel flag of CD8–BD1
CIN
31
56
I
I
Analog input of ADC C
CLK
Clock input. The clock frequency is normally 4 × the frequency subcarrier (fsc) for most video systems (see
Table 3). The nominal clock frequency is 14.31818 MHz for National Television System Committee (NTSC)
and 17.745 MHz for phase alteration line (PAL).
CLPEN
57
I
Clamp enable. When using an internal clamp pulse, CLPEN should be high. When using an external clamp
pulse, CLPEN should be low.
CLP OUT A
CLP OUT B
CLP OUT C
CLPV A
59
54
27
60
O
O
O
O
Clamping bias current of ADC A. A resistor-capacitor combination that sets the clamp timing.
Clamping bias current of ADC B. A resistor-capacitor combination that sets the clamp timing.
Clamping bias current of ADC C. A resistor-capacitor combination that sets the clamp timing.
Clamping level of ADC A. A capacitor is connected to CLPV A to set the clamp timing. The clamp level at
CLPV A is connected to an output code of 16 (0010000).
CLPV B
CLPV C
DGND
53
28
O
O
Clamping level of ADC B. A capacitor is connected to CLPV B to set the clamp timing. The clamp level at
CLPV B is connected to an output code of 128 (1000000).
Clamping level of ADC C. A capacitor is connected to CLPV C to set the clamp timing. The clamp level at
CLPV C is connected to an output code of 128 (1000000).
15
26
55
I
I
I
Digital ground
DV
Digital supply voltage
DD
EXTCLP
External clamp pulse input. When EXTCLP and CLPEN are low, the internal clamp circuit cannot be used.
The external clamp pulse when used is active high.
GND A
GND B
GND C
INIT
64
49
32
58
I
I
I
I
Ground of ADC A
Ground of ADC B
Ground of ADC C
Outputinitialized. Theoutput data is synchronous when INIT is taken high from low. INIT is a control terminal
that allows the external system to initialize the TLC5733A data conversion cycle. INIT is usually used at
power up or system reset.
MODE0
MODE1
46
45
I
I
Output format mode selector 0. When MODE1 is low and MODE0 is low, output data format1 is selected.
When MODE1 is low and MODE0 is high, output data format2 is selected. When MODE1 is high and
MODE0 is low, output data format3 is selected. A high level on MODE1 and a high level on MODE0 is not
used.
Output format mode selector 1. When MODE1 is low and MODE0 is low, output data format1 is selected.
When MODE1 is low and MODE0 is high, output data format2 is selected. When MODE1 is high and
MODE0 is low, output data format3 is selected. A high level on MODE1 and a high level on MODE0 is not
used.
NT/PAL
OE A
3
2
I
I
I
NTSC/PAL control. NTSC/PAL should be low for NTSC and high for PAL.
Output enable A. OE A enables the output of ADC A.
OE B
47
Output enable B. OE B enables the output of ADC B.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
Terminal Functions (Continued)
TERMINAL
NAME NO.
OE C
QA DGND
QA DV
I/O
DESCRIPTION
34
5
I
I
I
I
Output enable C. OE C enables the output of ADC C.
Digital ground for output of ADC A
14
25
Digital supply voltage for output of ADC A
Digital ground for output of ADC B
DD
QB DGND
QB DV
16
44
35
1
I
I
I
I
Digital supply voltage for output of ADC B
Digital ground for output of ADC C
DD
QC DGND
QC DV
RB A
Digital supply voltage for output of ADC C
DD
Bottom reference voltage of ADC A. The nominal externally applied dc voltage between RT A and RB A is
2 V for video signals.
RB B
RB C
RT A
RT B
RT C
TEST
48
33
61
52
29
4
I
I
I
I
Bottom reference voltage of ADC B. The nominal externally applied dc voltage between RT B and RB B is
2 V for video signals.
Bottom reference voltage of ADC C. The nominal externally applied dc voltage between RT C and RB C
is 2 V for video signals.
Top reference voltage of ADC A. The nominal externally applied dc voltage between RT A and RB A is 2
V for video signals.
Top reference voltage of ADC B. The nominal externally applied dc voltage between RT B and RB B is 2
V for video signals.
Top reference voltage of ADC C. The nominal externally applied dc voltage between RT C and RB C is 2
V for video signals.
I
Test. TEST should be tied low when using this device.
†
absolute maximum ratings
Supply voltage, V , V
Reference voltage input range,V , V , V , V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC DD
,
ref(RT A) ref(RT B) ref(RT C) ref(RB A)
V
, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to V
ref(RB B) ref(RB C)
CC
CC
DD
DD
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to V
Digital input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to V
Digital output voltage range, V
Operating free-air temperature range, T
Storage temperature range, T
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 75°C
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
recommended operating conditions
MIN
4.75
2.7
NOM
MAX
5.25
5.25
100
UNIT
V
V
–AGND
–DGND
5
5
0
CC
V
‡
Supply voltage
DD
AGND–DGND
, V
–100
mV
V
Reference input voltage, V
, V
ref(RT A) ref(RT B) ref(RT C)
V
+2
V
CC
ref(RB)
0
Reference input voltage, V
, V
, V
V
–2
V
ref(RB A) ref(RB B) ref(RB C)
ref(RT)
Analog input voltage, V
0
2
V
V
I
ref(RT)
High-level input voltage, V
Low-level input voltage, V
V
IH
0.8
V
IL
High-level pulse duration, t
25
25
ns
ns
ns
°C
w(H)
w(L)
su1
Low-level pulse duration, t
Setup time for INIT input, t
5
Operating free-air temperature range, T
–20
75
A
‡
Within the electrical and operating characteristics table, when the term V
is used, all XDV
terminals are tied together, and when the term
DD
DD
V
CC
is used, all XAV
terminals are tied together.
CC
electrical characteristics at V
= 2.7 V to 5.25 V, V
= 5 V, V
= 2.5 V, V
= 0.5 V,
DD
CC
ref(RT)
ref(BB)
f
= 20 MHz, T = 25°C (unless otherwise noted)
(CLK)
A
PARAMETER
Clamp level accuracy
TEST CONDITIONS
MIN
TYP
±1
MAX
UNIT
LSB
Ω
R
C
Reference voltage resistor
Analog input capacitance
Measured between RT and RB
V = 1.5 V + 0.07 V
160
220
16
350
ref
i
pF
I
rms
†
V
V
= MAX ,
= 5V
V
= V
,
DD
DD
CC
IH
I
High-level input current
Low-level input current
5
5
IH
IL
µA
†
V
DD
V
CC
= MAX ,
V
IL
= 0,
I
= 5V
All DV
terminals = 2.7 V to 5.25 V,
DD
= –1 mA
V
High-level output voltage
Low-level output voltage
High-level output leakage current
Low-level output leakage current
Supply current
DV
–0.7 V
DD
OH
I
OH
All DV
V
terminals = 2.7 V to 5.25 V,
DD
= 2 mA
V
OL
0.8
16
16
75
I
OL
†
V
DD
V
CC
= MAX ,
= 5V
V
= V
,
DD
OH
OL
I
I
I
OH(lkg)
OL(lkg)
CC
µA
†
V
DD
V
CC
= MIN ,
= 5V
V
= 0,
f = 20 MSPS,
c
NTSC ramp wave input
50
mA
†
Conditions marked MIN or MAX are as stated in recommended operating conditions.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
operating characteristics at V
= 2.7 V to 5.25 V, V
= 5 V, V
= 2.5 V, V
= 0.5 V,
DD
CC
ref(RT)
ref(RB)
f
= 20 MHz, T = 25°C (unless otherwise noted)
(CLK)
A
PARAMETER
TEST CONDITIONS
= REFT – REFB = 2 V
ref
MIN
–18
–20
TYP
MAX
UNIT
E
E
Zero-scale error
Full-scale error
V
–43
0
–68
20
mV
mV
ZS
V
ref
= REFT – REFB = 2 V
FS
f
= 20 MHz,
V = 0.5 V to 2.5 V
I
±0.4 ±0.75
(CLK)
E
Linearity error
LSB
LSB
f
T
= 20 MHz,
= –20°C to 75°C
V = 0.5 V to 2.5 V
I
L
(CLK)
A
±0.4
±0.3
±1
f
f
= 20 MHz,
V = 0.5 V to 2.5 V
I
±0.5
(CLK)
E
D
Linearity error, differential
= 20 MHz,
= –20°C to 75°C
V = 0.5 V to 2.5 V
I
(CLK)
±0.3 ±0.75
T
A
f
Maximum conversion rate
Analog input bandwidth
Digital output delay time
Differential gain
V = 0.5 V – 2.5 V,
I
f = 1-kHz ramp waveform
20
MSPS
MHz
ns
c
I
BW
At – 1 dB
14
t
pd
C
= 10 pF
L
18
1%
0.7
30
4
30
‡
NTSC 40 IRE modulation wave, f = 14.3 MSPS
c
‡
Differential phase
NTSC 40 IRE modulation wave, f = 14.3 MSPS
c
deg
ps
Aperture jitter time
Sampling delay time
ns
‡
Institute of Radio Engineers
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
detailed description
clamp function
The clamp function is optimized for a YUV video signal and has two clamp modes. The first mode uses the
COMPOSITE SYNC signal as the input to the EXTCLP terminal to generate an internal clamp pulse and the
second mode uses an externally generated clamp pulse as the input to the EXTCLP terminal.
In the first mode, the device detects false pulses in the COMPOSITE SYNC signal by monitoring the rising and
falling edges of the COMPOSITE SYNC signal pulses. This monitoring prevents faulty operation caused by
disturbances and missing pulses of the COMPOSITE SYNC signal input on EXTCLP and external spike noise.
When fault pulses are detected, the device internally generates a train of clamp pulses at the proper positions
(1H) by an internal 910-counter for NTSC and a 1136-counter for PAL. The device checks clamp pulses for 1H
time and generates clamp pulses at correct positions when COMPOSITE SYNC pulses are in error in time.
The internal counter continually produces a horizontal sync period (1H) that is NTSC or PAL compatible as
selected by the condition of the NT/PAL terminal.
clamp voltages and selection
Table1showstheclampinglevelduringtheclampinterval. Table2showstheselectionoftheinternalorexternal
clamp pulse. With either NTSC or PAL, the internal clamp pulse is always used.
Table 1. Clamp Level (Internal Connection Level)
CHANNEL OF ADC
OUTPUT CODE
00010000
APPLICATION
ADC A • V
ADC B • V
ADC C • V
Y
I(A)
I(B)
I(C)
10000000
(U, V)
(U, V)
10000000
Table 2. Clamp Level (Internal Connection Level)
CONDITION
EXTCLP
FUNCTION (EACH ADC)
CLPEN
NT/PAL
Don’t Care
Don’t Care
L
INTERNAL CLAMP
Inactive
CLAMP PULSE
External clamp pulse
No clamping
L
L
Inactive
Active
Synchronous with NTSC
Synchronous with PAL
H
COMPOSITE SYNC input
H
Active
The clamp circuit is shown in Figure 6. The clamp voltage is stored on capacitor C2 during the back porch of
the horizontal blanking period.
During the clamp pulse the input to channel A is clamped to:
V (A) = (16/256) × (voltage difference from terminal RT A to RB A)
C
V (B) = (128/256) × (voltage difference from terminal RT B to RB B)
C
V (C) = (128/256) × (voltage difference from terminal RT C to RB C)
C
COMPOSITE SYNC time monitoring
WhenCLPENishigh, COMPOSITESYNCgeneratesaninternalclamppulseonthehorizontalblankinginterval
back porch. The TLC5733A has a timing window into which the horizontal sync tip must occur. There is a noise
time window for the falling edge and one for the rising edge (see Figure 1, Figure 2, and Table 3).
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
correct COMPOSITE SYNC timing
The Noise Gate 1 signal provides the timing window for the COMPOSITE SYNC falling edge. After an interval
A of 867 clocks for NTSC or 1075 for PAL from the last falling edge of COMPOSITE SYNC, Noise Gate 1 signal
goes high for 43 clocks for NTSC or 61 clocks for PAL (interval B). The falling edge of the input signal to the
EXTCLP terminal can occur at any time within this window to be a valid COMPOSITE SYNC falling edge.
The Noise Gate 2 signal provides the timing window for the COMPOSITE SYNC rising edge. On the falling edge
of the horizontal sync tip, the internal logic generates Noise Gate 2 as a low signal for 58 clocks (interval C) for
both NTSC and PAL and then returns to a high active state. At this time if the input to EXTCLP is still low, it is
considered a valid COMPOSITE SYNC signal.
normal clamp pulse generation
On the rising edge of COMPOSITE SYNC, the internal logic generates an internal delay (interval D) and then
generates the internal positive clamp pulse 54 clocks wide (interval F).
clamp operation with incorrect COMPOSITE SYNC timing
noise suppression
If the input to EXTCLP goes low prior to Noise Gate 1 going high (within 43 clocks for NTSC or 61 clocks for
PAL of the normal 1H timing for the falling edge of COMPOSITE SYNC) then that input is not considered a valid
COMPOSITE SYNC and is ignored.
If the input to EXTCLP is high when Noise Gate 2 goes to the high state, the input signal is considered noise
and is ignored.
Therefore, the correct signal must be high for a maximum of 43 clocks for NTSC or 61 clocks for PAL, before
the 1H timing, to be a valid sync signal. Also, the input to EXTCLP must be at least 58 clocks wide (interval C)
to be valid.
This function of monitoring the timing eliminates spurious noise spikes from falsely synchronizing the system.
timing error of COMPOSITE SYNC
The internal counter resets to zero on the first falling edge of COMPOSITE SYNC. After that time, if there is a
missing COMPOSITE SYNC signal, then the internal logic waits an interval of 76 clocks (interval E) for NTSC
or 93 for PAL from the counter zero count and then generates an internal clamp pulse 54 clocks wide
(interval F).
This function maintains the synchronization pattern when COMPOSITE SYNC is not present.
summary of device operation with COMPOSITE SYNC
This internal timing allows the TLC5733A to correctly position the clamp pulse when an external COMPOSITE
SYNC input:
•
•
•
•
Is delayed with respect to the horizontal sync period
Is early with respect to the horizontal sync period
Is nonexistent during the horizontal sync period
Has falling edge noise spikes within the horizontal sync period
The device operation is summarized as follows for these improper external clamp conditions:
•
•
Under all four conditions on EXTCLP, the internal clamp generation circuit generates a clamp pulse at
the proper time after the horizontal sync period as shown in Figure 1.
The TLC5733A internal clamp circuit generates an internal clamp pulse each 1H time for the entire time
interval that the COMPOSITE SYNC input is missing.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
1H
COMPOSITE
SYNC
B
A
Missing COMPOSITE SYNC,
therefore, Noise Gate is Not
Generated
Noise Gate 1
Noise Gate 2
C
F
E
F
Internal Clamp
Pulse
D
NTSC/PAL Counter Reset
NTSC/PAL Counter at
Max Count
Figure 1. COMPOSITE SYNC and Internal Clamp Timing
COMPOSITE
SYNC
B
Noise Gate 1
Noise Gate 2
Figure 2. Proper COMPOSITE SYNC Timing
Table 3. Sync and Clamp Timing for NTSC and PAL with CLK = 4 fsc
NTSC
PAL
fsc = 3.58 MHz
fsc = 4.43 MHz
TIME
INTERVAL
NO. OF
TIME
NO. OF
TIME
CLOCKS
(µs)
CLOCKS
(µs)
A
B
C
D
E
F
867
43
58
6
60.6
3
1075
61
58
6
60.7
3.5
4.05
0.42
5.3
3.27
0.34
5.25
4.74
76
54
93
84
3.77
using an external clamp pulse
When CLPEN is taken low, EXTCLP accepts an externally generated active-high clamp pulse. This pulse must
occurwithinthehorizontal-blankingintervalbackporch. CLPENlowinhibitstheinternalcountersandnointernal
clamp pulse is generated.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
output digital code (for each channel of ADC)
Table 4. Input Signal Versus Digital Output Code
DIGITAL OUTPUT CODE
INPUT SIGNAL
VOLTAGE
STEP
MSB
LSB
V
255
1
•
1
•
1
•
1
•
1
•
1
•
1
•
1
•
ref(RT)
•
•
•
•
•
•
•
•
128
127
•
•
•
•
•
•
•
•
•
1
0
•
0
1
•
0
1
•
0
1
•
0
1
•
0
1
•
0
1
•
0
1
•
•
•
•
•
•
•
•
•
•
V
0
0
0
0
0
0
0
0
0
ref(RB)
output data format
The TLC5733A can select three output data formats to various TV/VCR (video) data processing by the
combination of MODE0 and MODE1. The output is synchronous when INIT is taken high.
Table 5. Output Data Format Selection
CONDITION
MODE1 MODE0
OUTPUT DATA
OUTPUT DATA
RATIO OF Y:U:V
FORMAT
Format 1
Format 2
Format 3
Not used
L
L
4:1:1
4:4:4
4:2:2
N/A
L
H
H
H
L
H
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
output data format (continued)
t
t
w(H)
w(L)
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
t
su1
INIT
OE A
OE B
OE C
Analog
n+3
n+4
Input V
I(ANLG)
n+5
n+2
n+7
n
n+6
n+1
6 f
CLK
t
pd
INVALID
INVALID
A0
A1
A2
A3
A4
A5
A6
A7
Output Data A
t
pd
Output Data B
BD8–BD5
B08 B06
B07 B05
C08 C06
C07 C05
B04
B03
C04
C03
B02
B01
C02
C01
B48
B47
C48
C47
B46
B45
C46
C45
B44
B43
C44
C43
B42
B41
C42
C41
BD4–BD1:
Hi-Z
t
pd
Output Data C
CD8
CD7
CD6–CD1: Hi-Z
= Input signal sampling point
Figure 3. Format 1, 4:1:1
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
output data format (continued)
Table 6. Format 1
OUTPUT DATA
CHANNEL OF
BIT
CLK (see Note 1)
ADC
6
7
8
9
10
11
12
13
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
A08
A07
A06
A05
A04
A03
A02
A01
A18
A17
A16
A15
A14
A13
A12
A11
A28
A27
A26
A25
A24
A23
A22
A21
A38
A37
A36
A35
A34
A33
A32
A31
A48
A47
A46
A45
A44
A43
A42
A41
A58
A57
A56
A55
A54
A53
A52
A51
A68
A67
A66
A65
A64
A63
A62
A61
A78
A77
A76
A75
A74
A73
A72
A71
A
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
B08
B07
C08
C07
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B06
B05
C06
C05
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B04
B03
C04
C03
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B02
B01
C02
C01
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B48
B47
C48
C47
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B46
B45
C46
C45
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B44
B43
C44
C43
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B42
B41
C42
C41
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
H
L
L
L
L
L
L
H
H
L
L
L
L
L
L
H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
C
NOTES: 1. The value of the first sampling clock at A/D conversion is CLK 0.
2. A06 is an example of an entry in the table where A is the ADC channel, 0 is the sampling order, and
6 is the bit number.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
output data format (continued)
t
t
w(H)
w(L)
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
t
su1
INIT
OE A
OE B
OE C
Analog
n+3
n+4
Input V
I(ANLG)
n+5
n+2
n+7
n
n+6
n+1
6 f
CLK
t
pd
Output Data A
AD8–AD1
INVALID
INVALID
A0
A1
B1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
t
pd
Output Data B
BD8–BD1
B0
t
pd
Output Data C
CD8–CD1
C0
C1
C2
C3
C4
C5
C6
C7
INVALID
= Input signal sampling point
Figure 4. Format 2, 4:4:4
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
output data format (continued)
Table 7. Format 2
OUTPUT DATA
CHANNEL OF
BIT
CLK (see Note 1)
ADC
6
7
8
9
10
11
12
13
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
A08
A07
A06
A05
A04
A03
A02
A01
A18
A17
A16
A15
A14
A13
A12
A11
A28
A27
A26
A25
A24
A23
A22
A21
A38
A37
A36
A35
A34
A33
A32
A31
A48
A47
A46
A45
A44
A43
A42
A41
A58
A57
A56
A55
A54
A53
A52
A51
A68
A67
A66
A65
A64
A63
A62
A61
A78
A77
A76
A75
A74
A73
A72
A71
A
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
B08
B07
B06
B05
B04
B03
B02
B01
B18
B17
B16
B15
B14
B13
B12
B11
B28
B27
B26
B25
B24
B23
B22
B21
B38
B37
B36
B35
B34
B33
B32
B31
B48
B47
B46
B45
B44
B43
B42
B41
B58
B57
B56
B55
B54
B53
B52
B51
B68
B67
B66
B65
B64
B63
B62
B61
B78
B77
B76
B75
B74
B73
B72
B71
B
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
C08
C07
C06
C05
C04
C03
C02
C01
C18
C17
C16
C15
C14
C13
C12
C11
C28
C27
C26
C25
C24
C23
C22
C21
C38
C37
C36
C35
C34
C33
C32
C31
C48
C47
C46
C45
C44
C43
C42
C41
C58
C57
C56
C55
C54
C53
C52
C51
C68
C67
C66
C65
C64
C63
C62
C61
C78
C77
C76
C75
C74
C73
C72
C71
C
NOTES: 1. The value of the first sampling clock at A/D conversion is CLK 0.
2. A06 is an example of an entry in the table where A is the ADC channel, 0 is the sampling order, and
6 is the bit number.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
output data format (continued)
t
t
w(H)
w(L)
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
t
su1
INIT
OE A
OE B
OE C
Analog
n+3
n+4
Input V
I(ANLG)
n+5
n+2
n+7
n
n+6
n+1
6 f
CLK
t
pd
Output Data A
AD8–AD1
INVALID
INVALID
A0
A1
C0
A2
B2
A3
C2
A4
B4
A5
C4
A6
B6
t
pd
Output Data B
BD8–BD1
B0
t
pd
Output Data C
CD8
CD7
CD6 – CD1: Hi-Z
= Input signal sampling point
Figure 5. Format 3, 4:2:2
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
output data format (continued)
Table 8. Format 3
OUTPUT DATA
CHANNEL OF
BIT
CLK (see Note 1)
ADC
6
7
8
9
10
11
12
13
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
A08
A07
A06
A05
A04
A03
A02
A01
A18
A17
A16
A15
A14
A13
A12
A11
A28
A27
A26
A25
A24
A23
A22
A21
A38
A37
A36
A35
A34
A33
A32
A31
A48
A47
A46
A45
A44
A43
A42
A41
A58
A57
A56
A55
A54
A53
A52
A51
A68
A67
A66
A65
A64
A63
A62
A61
A78
A77
A76
A75
A74
A73
A72
A71
A
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
B08
B07
B06
B05
B04
B03
B02
B01
C08
C07
C06
C05
C04
C03
C02
C01
B28
B27
B26
B25
B24
B23
B22
B21
C28
C27
C26
C25
C24
C23
C22
C21
B48
B47
B46
B45
B44
B43
B42
B41
C48
C47
C46
C45
C44
C43
C42
C41
B68
B67
B66
B65
B64
B63
B62
B61
C68
C67
C66
C65
C64
C63
C62
C61
B
CD8
CD7
CD6
CD5
CD4
CD3
CD2
CD1
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
C
NOTES: 1. The value of the first sampling clock at A/D conversion is CLK 0.
2. A06 is an example of an entry in the table where A is the ADC channel, 0 is the sampling order, and
6 is the bit number.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
APPLICATION INFORMATION
Feed Back Clamp Block of HSYNC
CLK
V
ref
(Top)
C2
0.22 µF
A/D
Video Signal Input
AIN
(Composite or Component)
V
ref
(Bottom)
Digital
Feedback
_
+
Clamp Gate
R1
16 kΩ
P
Output
Q
C1
2200 pF
Preset Data
Magnitude
Comparator
FEEDBACK CLAMP AND CHARGE PUMP ACTIVITY
INPUT DATA
CONDITIONS
CHARGE PUMP
CONDITIONS
OUTPUT
P < Q
P = Q
P > Q
Active
H
Z
L
Charge
Hold
Hold
Active
Discharge
Figure 6. Feedback Clamp Circuit
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
APPLICATION INFORMATION
Channel–A
TLC5733A
16 kΩ
10 µF
2.2 kΩ
110 Ω
4.3 kΩ
10 µF
1.8 kΩ
PNP: 2SA733
NPN: 2SC1815
C2
63
V
IN
(A)
Analog
Signal Input
2V
I(PP)
1 kΩ
1V (
I PP)
CW
Gain Adjust
5.6 kΩ
75 Ω
5.6 kΩ
470 Ω
5.6 kΩ
1.8 kΩ
Buffer Amplifier
C2
60
59
CLPV(A)
TLC5733A
0.22 µF
R1
ADC
Channel–A
to
CLP OUT(A)
Buffer Amp
C1
R1
15 kΩ
2
Channel–C
OE(A)
C1
2200 pF
Channel–B
Channel–C
55
EXTCLP
56
57
CLK IN
CLK
CLPEN
58
3
INIT
NT/PAL
4
TEST
Figure 7. Interface Without Clamping
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
APPLICATION INFORMATION
Channel–A
TLC5733A
16 kΩ
10 µF
2.2 kΩ
110 Ω
4.3 kΩ
10 µF
1.8 kΩ
PNP: 2SA733
NPN: 2SC1815
C2
63
V
IN
(A)
Analog
Signal Input
2V (
I PP)
1 kΩ
1V (
I PP)
CW
Gain Adjust
5.6 kΩ
75 Ω
5.6 kΩ
470 Ω
1.8 kΩ
Buffer Amplifier
C2
60
59
CLPV(A)
TLC5733A
0.22 µF
R1
ADC
Channel–A
to
CLP OUT A
Buffer Amp
C1
R1
15 kΩ
2
Channel–C
OE(A)
C1
2200 pF
Channel–B
Channel–C
55
10 µF
EXTCLP
Composite SYNC
CLK IN
+
0 V
1 kΩ
–5 V
0 V
56
CLK
57
58
3
CLPEN
INIT
NT/PAL
TEST
4
Figure 8. Interface Connection Using Composite Sync Signal
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
APPLICATION INFORMATION
Channel–A
TLC5733A
16 kΩ
10 µF
2.2 kΩ
110 Ω
4.3 kΩ
10 µF
1.8 kΩ
PNP: 2SA733
NPN: 2SC1815
C2
63
V
IN
(A)
Analog
Signal Input
2V (
I PP)
1 kΩ
1V (
I PP)
CW
Gain Adjust
5.6 kΩ
75 Ω
5.6 kΩ
470 Ω
1.8 kΩ
Buffer Amplifier
C2
60
59
CLPV(A)
TLC5733A
0.22 µF
R1
ADC
Channel–A
to
CLP OUT A
Buffer Amp
C1
R1
15 kΩ
2
Channel–C
OE(A)
C1
2200 pF
Channel–B
Channel–C
55
D
Q
EXTCLP
Clamp Pulse IN
CLK IN
56
CLK
57
58
3
CLPEN
INIT
NT/PAL
TEST
4
Figure 9. Interface Using External Clamp Pulse With Synchronization
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
APPLICATION INFORMATION
AV
DD
+
_
ADC
Block
ADC
Block
ADC
Block
V (A)
RT
V (B)
RT
V (C)
RT
61
52
29
R
REF
V
RB
1
(A)
V
RB
48
(B)
V
RB
33
(C)
+
_
Figure 10. Adjustment Circuit For Top and Bottom Reference Voltages
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC5733A
20 MSPS 3-CHANNEL ANALOG-TO-DIGITAL CONVERTER
WITH HIGH-PRECISION CLAMP
SLAS104A – JULY 1995 – REVISED NOVEMBER 1996
MECHANICAL DATA
PM (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,50
M
0,08
0,17
33
48
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
0,25
12,20
SQ
0,05 MIN
0°–7°
11,80
1,45
1,35
0,75
0,45
Seating Plane
1,60 MAX
0,08
4040152/B 03/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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