TLC59116ITPWRQ1 [TI]
汽车类 16 通道 FM+ I2C 总线恒流 LED 灌流驱动器 | PW | 28 | -40 to 105;
| 型号： | TLC59116ITPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 16 通道 FM+ I2C 总线恒流 LED 灌流驱动器 | PW | 28 | -40 to 105 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总41页 (文件大小：672K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Sample &
Buy
Support &
Community
Product
Folder
Tools &
Software
Technical
Documents
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
TLC59116-Q1 16 通道 FM+ I2C 总线恒流 LED 灌电流驱动器
1
1 特性
•
16 个发光二极管 (LED) 驱动器（每个输出均可通
•
•
•
5.5V 耐压输入
过编程设定为关闭、开启、可编程的 LED 亮度或
者可编程的组合式调光和闪烁（各 LED 亮度混
合））
28 引脚薄型紧缩小尺寸封装 (TSSOP) (PW-28)
运行温度范围：–40°C 至 +105°C
•
•
16 条恒流输出通道
2 应用
256 色阶（8 位）线性可编程亮度范围，对应的
LED 输出从完全关闭（默认）到最大亮度（采用
97kHz 的脉宽调制 (PWM) 信号）
•
•
•
通用 LED 照明 应用
中控台按钮背光
仪表板指示灯背光
•
256 色阶组合式亮度控制支持通用调光 [采用
190Hz PWM 信号，从完全关闭到最大亮度（默
认）]
3 说明
TLC59116-Q1 是一款 I2C 总线控制的 16 通道 LED 驱
动器，它针对红色/绿色/蓝色/琥珀色 (RGBA) 混合和背
光应用进行了优化。每个 LED 输出都拥有自己的 8 位
分辨率（256 色阶）、固定频率、独立 PWM 控制器
（工作频率为 97kHz）和可调节占空比（0% 至
99.6%）。
•
•
•
256 色阶组合式闪烁，频率可在 24Hz 至 10.73s
范围内编程设定，占空比范围为 0% 至 99.6%
四个硬件地址引脚支持 14 个 TLC59116-Q1 器件
连接至同一条 I2C 总线
四个可通过软件编程设定的 I2C 总线地址（一个
LED 组合式调用地址和三个 LED 子调用地址）支
持以任意组合同时寻址多组器件
器件信息 (1)
•
•
•
•
软件复位功能（SWRST 调用）支持通过 I2C 总线
复位器件
多达 14 个可通过硬件调节的独立 I2C 总线地址，
这样便可对每个器件进行编程设定
部件号
封装
封装尺寸（标称值）
TLC59116-Q1
TSSOP (28)
9.70mm x 4.40mm
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
负载开路和过热检测模式，用于检测各个 LED 故
障
TLC59116-Q1 典型应用
可通过编程在收到应答命令或停止命令时更改输出
状态以逐字节更新输出或同时更新全部输出（默认
在收到停止命令时更改）
3.3 V
or
5 V
...
•
•
•
•
•
可通过外部电阻调节输出电流
恒定输出电流范围：5mA 至 120mA
最大输出电压：17V
TLC59116-Q1
SCL
SDA
SCL
SDA
VCC
OUT15
OUT14
OUT13
RESET
RESET
A0–A3
25MHz 内部振荡器，无需外部组件
1MHz 快速模式 Plus (FMT) 兼容 I2C 总线接
口，SDA 输出具有 30mA 高驱动能力，用于驱动
高容性总线
OUT1
OUT0
REXT
•
•
•
•
•
•
•
内部上电复位
GND
SCL 和 SDA 输入端装有噪声滤波器
上电时无毛刺脉冲
低电平有效复位
REXT
支持热插入
低待机电流
3.3V 或 5V 电源电压
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLDS223
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
目录
9.3 Feature Description................................................. 12
9.4 Device Functional Modes........................................ 15
9.5 Programming........................................................... 15
9.6 Register Maps......................................................... 22
10 Application and Implementation........................ 30
10.1 Application Information.......................................... 30
10.2 Typical Application ................................................ 31
11 Power Supply Recommendations ..................... 33
12 Layout................................................................... 33
12.1 Layout Guidelines ................................................. 33
12.2 Layout Example .................................................... 33
12.3 Thermal Considerations........................................ 34
13 器件和文档支持 ..................................................... 35
13.1 文档支持 ............................................................... 35
13.2 社区资源................................................................ 35
13.3 商标....................................................................... 35
13.4 静电放电警告......................................................... 35
13.5 Glossary................................................................ 35
14 机械、封装和可订购信息....................................... 35
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明 （续）.............................................................. 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions ...................... 5
7.4 Thermal Information.................................................. 5
7.5 Electrical Characteristics........................................... 6
7.6 Timing Requirements................................................ 7
7.7 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 12
9.1 Overview ................................................................. 12
9.2 Functional Block Diagram ....................................... 12
8
9
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (March 2016) to Revision A
Page
•
已将器件状态从产品预览更改为量产数据 .............................................................................................................................. 1
2
版权 © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
5 说明 （续）
独立 PWM 控制器允许将每个 LED 设置为特定的亮度值。附加的 8 位分辨率（256 色阶）组合式 PWM 控制器既
具有 190Hz 的固定频率，又拥有可调节频率（24Hz 至每隔 10.73 秒一次）和可调节占空比（0% 至 99.6%）。组
合式 PWM 控制器使用相同的值来调亮或调暗所有 LED。
每个 LED 输出均可设置为关闭、开启（无 PWM 控制）或其各自 PWM 控制器的值（独立 PWM 控制器的值和组
合式 PWM 控制器的值）。
TLC59116-Q1 的工作电源电压范围为 3V 至 5.5V，输出可耐受 17V 电压。LED 可直接连接至 TLC59116-Q1 器件
输出。
可通过软件编程的 LED 组合式和三个子调用 I2C 总线地址允许所有或定义的几组 TLC59116-Q1 器件响应同一 I2C
总线地址，以实现例如同时开启或关闭颜色相同的 LED 或者跑马灯效果，从而以最大限度减少 I2C 总线命令。
四个硬件地址引脚支持同一总线上连接 14 个器件。
软件复位 (SWRST) 调用允许主机通过 I2C 总线对 TLC59116-Q1 执行复位，该复位与上电复位 (POR) 一样会将寄
存器初始化为默认状态，从而将输出设置为高电平（LED 关闭）。这样一来，便可以轻松快速地将所有器件寄存器
重新配置为相同状态。
Copyright © 2016, Texas Instruments Incorporated
3
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
6 Pin Configuration and Functions
PW Package
28-Pin TSSOP
Top View
REXT
A0
1
2
28
VCC
27
SDA
A1
A2
3
4
5
6
26
25
24
23
SCL
RESET
GND
A3
OUT0
OUT15
OUT1
OUT2
7
8
22
21
OUT14
OUT13
OUT3
GND
9
20
19
18
17
OUT12
GND
10
11
12
OUT4
OUT5
OUT11
OUT10
OUT6
OUT7
13
14
16
15
OUT9
OUT8
Pin Functions
PIN
(1)
I/O
DESCRIPTION
NO.
1
NAME
REXT
A0
I
I
Input terminal used to connect an external resistor for setting up all output currents
Address input 0
2
3
A1
I
Address input 1
4
A2
I
Address input 2
5
A3
I
Address input 3
6
OUT0
OUT1
OUT2
OUT3
GND
O
O
O
O
—
O
O
O
O
O
O
O
O
—
O
O
O
O
—
I
Constant current output 0
Constant current output 1
Constant current output 2
Constant current output 3
Ground
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
GND
Constant current output 4
Constant current output 5
Constant current output 6
Constant current output 7
Constant current output 8
Constant current output 9
Constant current output 10
Constant current output 11
Ground
OUT12
OUT13
OUT14
OUT15
GND
Constant current output 12
Constant current output 13
Constant current output 14
Constant current output 15
Ground
RESET
SCL
Active-low reset input
Serial clock input
I
SDA
I/O
—
Serial data input/output
Power supply
VCC
(1) I/O = input and Output
4
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
(1)
MIN
0
MAX
7
UNIT
V
VCC Supply voltage
VI
Input voltage
–0.4
–0.5
VCC + 0.4
20
V
VO Output voltage
V
IO
Output current per channel
Junction temperature
120
mA
°C
°C
TJ
–40
–55
150
Tstg Storage temperature
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
±1500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
All unused inputs of the device must be held at VCC or GND to ensure proper device operation
MIN
MAX UNIT
VCC
VIH
VIL
Supply voltage
3
0.7 × VCC
0
5.5
VCC
V
V
V
V
High-level input voltage
Low-level input voltage
Supply voltage to output pins
SCL, SDA, RESET, A0, A1, A2, A3
SCL, SDA, RESET, A0, A1, A2, A3
OUT0 to OUT15
0.3 × VCC
17
VO
VCC = 3 V
20
IOL
Low-level output current sink
SDA
mA
VCC = 5 V
30
IO
Output current per channel
OUT0 to OUT15
5
120
mA
°C
TA
Operating free-air temperature
–40
105
7.4 Thermal Information
TLC59116-Q1
(1)
THERMAL METRIC
PW (TSSOP)
UNIT
28 PINS
78
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
18.8
36
ψJT
0.5
ψJB
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
35.5
n/a
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2016, Texas Instruments Incorporated
5
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
MAX UNIT
7.5 Electrical Characteristics
VCC = 3 V to 5.5 V, TA = –40°C to +105°C (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
SCL, SDA, A0,
A1, A2, A3,
RESET
Input / output leakage
current
II
VI = VCC or GND
±0.3
0.5
μA
Output leakage current
Power-on reset voltage
OUT0 to OUT15 VO = 17 V, TJ = 25°C
μA
VPOR
IOL
2.5
26
V
VCC = 3 V, VOL = 0.4 V
20
30
Low-level output current SDA
mA
mA
VCC = 5 V, VOL = 0.4 V
(2)
(2)
IO(1)
Output current 1
OUT0 to OUT15 VO = 0.6 V, Rext = 720 Ω, CG = 0.992
IO = 26 mA, VO = 0.6 V, Rext = 720 Ω,
Output current error
OUT0 to OUT15
TJ = 25°C
±10%
±6%
Output channel to
channel current error
IO = 26 mA, VO = 0.6 V, Rext = 720 Ω,
OUT0 to OUT15
TJ = 25°C
IO(2)
Output current 2
OUT0 to OUT15 VO = 0.8 V, Rext = 360 Ω, CG = 0.992
52
mA
IO = 52 mA, VO = 0.8 V, Rext = 360 Ω,
Output current error
OUT0 to OUT15
TJ = 25°C
±8%
±6%
Output channel to
channel current error
IO = 52 mA, VO = 0.8 V, Rext = 360 Ω,
OUT0 to OUT15
TJ = 25°C
VO = 1 V to 3 V, IO = 26 mA
OUT0 to OUT15
±0.1
±1
IOUT vs
VOUT
Output current vs output
voltage regulation
%/V
VO = 3 V to 5.5 V, IO = 26 mA to 120 mA
Threshold current 1 for
error detection
0.5 ×
IOUT,Th1
IOUT,Th2
IOUT,Th3
OUT0 to OUT15 IOUT,target = 26 mA
ITARGET%
Threshold current 2 for
error detection
0.5 ×
OUT0 to OUT15 IOUT,target = 52 mA
ITARGET%
Threshold current 3 for
error detection
0.5 ×
OUT0 to OUT15 IOUT,target = 104 mA
ITARGET
%
175
15
(3)
TSD
Overtemperature shutdown
Restart hysteresis
150
200
°C
°C
THYS
SCL, A0, A1,
Ci
Input capacitance
Input / output
VI = VCC or GND
A2, A3, RESET
5
8
pF
pF
Cio
SDA
VI = VCC or GND
capacitance
OUT0 to OUT15 = OFF,
Rext = Open
25
29
32
37
29
32
37
OUT0 to OUT15 = OFF,
Rext = 720 Ω
OUT0 to OUT15 = OFF,
Rext = 360 Ω
OUT0 to OUT15 = OFF,
Rext = 180 Ω
ICC
Supply current
VCC = 5.5 V
mA
OUT0 to OUT15 = ON,
Rext = 720 Ω
OUT0 to OUT15 = ON,
Rext = 360 Ω
OUT0 to OUT15 = ON,
Rext = 180 Ω
(1) All typical values are at TA = 25°C.
(2) CG is the Current Gain and is defined in Table 13.
(3) Specified by design
6
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
7.6 Timing Requirements
TA = –40°C to +105°C
I2C BUS
MIN
MAX
UNIT
kHz
μs
I2C INTERFACE
STANDARD MODE
FAST MODE
0
0
100
400
(1)
fSCL
SCL clock frequency
FAST MODE PLUS
STANDARD MODE
FAST MODE
0
1000
4.7
1.3
0.5
4
I2C Bus free time between Stop and Start
conditions
tBUF
FAST MODE PLUS
STANDARD MODE
FAST MODE
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT
tSU;DAT
tLOW
Hold time (repeated) Start condition
Set-up time for a repeated Start condition
Set-up time for Stop condition
Data hold time
0.6
0.26
4.7
0.6
0.26
4
μs
FAST MODE PLUS
STANDARD MODE
FAST MODE
μs
FAST MODE PLUS
STANDARD MODE
FAST MODE
0.6
0.26
0
μs
FAST MODE PLUS
STANDARD MODE
FAST MODE
0
ns
FAST MODE PLUS
STANDARD MODE
FAST MODE
0
0.3
0.1
0.05
0.3
0.1
0.05
250
100
50
3.45
0.9
(2)
Data valid acknowledge time
μs
FAST MODE PLUS
STANDARD MODE
FAST MODE
0.45
3.45
0.9
(3)
Data valid time
μs
FAST MODE PLUS
STANDARD MODE
FAST MODE
0.45
Data set-up time
ns
FAST MODE PLUS
STANDARD MODE
FAST MODE
4.7
1.3
0.5
4
Low period of SCL clock
High period of SCL clock
μs
FAST MODE PLUS
STANDARD MODE
FAST MODE
tHIGH
0.6
0.26
μs
FAST MODE PLUS
STANDARD MODE
FAST MODE
300
300
(4) (5)
(6)
tf
Fall time of both SDA and SCL signals
20+0.1Cb
ns
FAST MODE PLUS
STANDARD MODE
FAST MODE
120
1000
300
(6)
tr
Rise time of both SDA and SCL signals
20+0.1Cb
ns
FAST MODE PLUS
120
(1) The TLC59116-Q1 does not have a self timeout on the I2C Bus. The Master can issue a reset if needed.
(2) tVD;ACK = time for ACK signal from SCL low to SDA (out) low.
(3) tVD;DAT = minimum time for SDA data out to be valid following SCL low.
(4) A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of the SCL falling edge.
(5) The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time (tf) for the SDA output stage is specified
at 250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
(6) Cb = Total capacitance of one bus line in pF
Copyright © 2016, Texas Instruments Incorporated
7
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
Timing Requirements (continued)
TA = –40°C to +105°C
I2C BUS
MIN
MAX
UNIT
STANDARD MODE
FAST MODE
50
50
50
Pulse width of spikes that must be
suppressed by the input filter
tSP
ns
(7)
FAST MODE PLUS
RESET
STANDARD MODE
FAST MODE
10
10
10
0
tW
Reset pulse width
ns
ns
ns
FAST MODE PLUS
STANDARD MODE
FAST MODE
tREC
Reset recovery time
0
FAST MODE PLUS
STANDARD MODE
FAST MODE
0
400
400
400
(8) (9)
tRESET
Time to reset
FAST MODE PLUS
(7) Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
(8) Resetting the device while actively communicating on the bus may cause glitches or errant Stop conditions.
(9) Upon reset, the full delay will be the sum of tRESET and the RC time constant of the SDA bus.
8
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
7.7 Typical Characteristics
140
120
100
80
125
100
75
50
25
0
156 W
720 W
3750 W
60
40
20
0
0
500
1000
1500
2000
(W)
2500
3000
3500
4000
0
0.2
0.4
0.6
0.8
1
1.2
1.4 1.5
R
Output Voltage (V)
ext
D002
VCC = 5 V
CG = 0.992
Figure 1. IOUT,target vs Rext
Figure 2. Output Current vs Output Voltage across Output
Current
24
22
20
28
24
20
16
12
8
18
-40 èC
-40 èC
16
25 èC
25 èC
85 èC
4
85 èC
105 èC
105 èC
0
14
0
0.2
0.4
0.6
0.8
1
1.2
1.4 1.5
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25 5.5
Output Voltage (V)
Supply Voltage (V)
D003
D004
VCC = 5 V
CG = 0.992
REXT = 720 Ω
REXT = 720 Ω
All Channels ON
Figure 3. Output Current vs Output Voltage across Temp
Figure 4. ICC vs VCC across Temp
Copyright © 2016, Texas Instruments Incorporated
9
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
8 Parameter Measurement Information
Start
SCL
ACK or Read Cycle
SDA
30%
tRESET
50%
50%
RESET
tREC
tW
OUTn
tRESET
Figure 5. Reset Timing
SDA
SCL
tBUF
tHD;STA
tSP
tr
tf
tLOW
tSU;DAT
tHD;STA
tSU;STO
tHD;DAT
tSU;DAT
tHIGH
P
S
Sr
P
Figure 6. Definition of Timing
START
Condition
(S)
Bit 7
MSB
(A7)
Bit 6
(A6)
Bit 7
(D1)
Bit 8
(D0)
Acknowledge
(A)
STOP Condition
(P)
Protocol
t
t
SU;STA
HIGH
t
1/f
LOW
SCL
SCL
t
r
t
f
t
BUF
SDA
t
t
t
t
t
T
HD;STA
SU;DAT
HD;DAT
VD;DAT
VD;ACK
SU;STO
NOTE: Rise and fall times refer to VIL and VIH
.
Figure 7. I2C Bus Timing
10
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
Parameter Measurement Information (continued)
VCC
Open
GND
VCC
RL
VI
VO
Pulse
Generator
DUT
RT
CL
NOTE:
•
•
•
RL = Load resistance for SDA and SCL; should be >1 kΩ at 3-mA or lower current
CL = Load capacitance; includes jig and probe capacitance
RT = Termination resistance; should be equal to the output impedance (ZO) of the pulse generator
Figure 8. Test Circuit for Switching Characteristics
Copyright © 2016, Texas Instruments Incorporated
11
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
9 Detailed Description
9.1 Overview
The TLC59116-Q1 is an I2C Bus controlled 16-channel LED driver that is optimized for red/green/blue/amber
(RGBA) color mixing and backlight application. Each LED output has its own 8-bit resolution (256 steps) fixed-
frequency individual PWM controller that operates at 97-kHz, with a duty cycle that is adjustable from 0% to
99.6%. The individual PWM controller allows each LED to be set to a specific brightness value. An additional 8-
bit resolution (256 steps) group PWM controller has both a fixed frequency of 190-Hz and an adjustable
frequency between 24-Hz to once every 10.73 seconds, with a duty cycle that is adjustable from 0% to 99.6%.
The group PWM controller dims or blinks all LEDs with the same value.
9.2 Functional Block Diagram
A0 A1 A2 A3
REXT
OUT0 OUT1
OUT14 OUT15
SCL
SDA
I/O Regulator
I2C Bus Control
Input Filter
Output Driver and Error Detection
Power-On
Reset Control
RESET
LED State
Select Register
PWM Register X
Brightness Control
GRPFRQ
Register
24.3 kHz
97 kHz
GRPPWM
Register
25-MHz
Oscillator
190 kHz
0 = Permanently off
1 = Permanently on
VCC
GND
9.3 Feature Description
9.3.1 Open-Circuit Detection
The TLC59116-Q1 LED open-circuit detection compares the effective current level IOUT with the open load
detection threshold current IOUT,Th. If IOUT is below the threshold IOUT,Th the TLC59116-Q1 detects an open load
condition. This error status can be read out as an error flag through the registers EFLAG1 and EFLAG2.
For open-circuit error detection, a channel must be on and the PWM must be off. See Table 1.
12
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
Feature Description (continued)
Table 1. Open-Circuit Detection
CONDITION OF OUTPUT
CURRENT
STATE OF OUTPUT PORT
ERROR STATUS CODE
MEANING
Off
IOUT = 0 mA
0
Detection not possible
Open circuit
(1)
IOUT < IOUT,Th
0
On
(1)
I
OUT ≥ IOUT,Th
Channel n error status bit 1
Normal
(1) IOUT,Th = 0.5 × IOUT,target (typical)
9.3.2 Overtemperature Detection and Shutdown
The TLC59116-Q1 LED is equipped with a global overtemperature sensor and 16 individual channel-selective
overtemperature sensors.
•
When the global sensor reaches the trip temperature, all output channels are shut down, and the error status
is stored in the internal Error Status register of every channel. After shutdown, the channels automatically
restart after cooling down, if the control signal (output latch) remains on. The stored error status is not reset
after cooling down and can be read out as the error status code in registers EFLAG1 and EFLAG2.
•
When one of the channel-specific sensors reaches trip temperature, only the affected output channel is shut
down, and the error status is stored only in the internal Error Status register of the affected channel. After
shutdown, the channel automatically restarts after cooling down, if the control signal (output latch) remains
on. The stored error status is not reset after cooling down and can be read out as error status code in
registers EFLAG1 and EFLAG2.
For channel-specific overtemperature error detection, a channel must be on.
The error flags of open-circuit and overtemperature are ORed to set the EFLAG1 and EFLAG2 registers.
The error status code because of overtemperature is reset when the host writes 1 to bit 7 of the MODE2 register.
The host must write 0 to bit 7 of the MODE2 register to enable the overtemperature error flag. See Table 2.
(1)
Table 2. Overtemperature Detection
STATE OF OUTPUT PORT
CONDITION
Tj < Tj,trip global
ERROR STATUS CODE
MEANING
Normal
1
On
On → all channels Off
Tj > Tj,trip global
All error status bits = 0
1
Global overtemperature
Normal
Tj < Tj,trip channel n
Tj > Tj,trip channel n
On
On → Off
Channel n error status bit = 0
Channel n overtemperature
(1) The global shutdown threshold temperature is approximately 170°C.
9.3.3 Power-On Reset (POR)
When power is applied to VCC, an internal power-on reset holds the TLC59116-Q1 in a reset condition until VCC
reaches VPOR. At this point, the reset condition is released and the TLC59116-Q1 registers, and I2C Bus state
machine are initialized to their default states (all zeroes), causing all the channels to be deselected. Thereafter,
VCC must be lowered below 0.2 V to reset the device.
9.3.4 External Reset
A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TLC59116-Q1 registers
and I2C state machine are held in their default states until the RESET input is again high.
This input requires a pullup resistor to VCC if no active connection is used.
9.3.5 Software Reset
The Software Reset Call (SWRST Call) allows all the devices in the I2C Bus to be reset to the power-up state
value through a specific I2C Bus command.
The SWRST Call function is defined as the following:
1. A Start command is sent by the I2C Bus master.
Copyright © 2016, Texas Instruments Incorporated
13
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
2. The reserved SWRST I2C Bus address 1101 011 with the R/W bit set to 0 (write) is sent by the I2C Bus
master.
3. The TLC59116-Q1 device(s) acknowledge(s) after seeing the SWRST Call address 1101 0110 (D6h) only. If
the R/W bit is set to 1 (read), no acknowledge is returned to the I2C Bus master.
4. Once the SWRST Call address has been sent and acknowledged, the master sends two bytes with two
specific values (SWRST data byte 1 and byte 2):
(a) Byte1 = A5h: the TLC59116-Q1 acknowledges this value only. If byte 1 is not equal to A5h, the
TLC59116-Q1 does not acknowledge it.
(b) Byte 2 = 5Ah: the TLC59116-Q1 acknowledges this value only. If byte 2 is not equal to 5Ah, the
TLC59116-Q1 does not acknowledge it.
If more than two bytes of data are sent, the TLC59116-Q1 does not acknowledge any more.
5. Once the correct two bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly
acknowledged, the master sends a Stop command to end the SWRST Call. The TLC59116-Q1 then resets
to the default value (power-up value) and is ready to be addressed again within the specified bus free time
(tBUF).
The I2C Bus master may interpret a non-acknowledge from the TLC59116-Q1 (at any time) as a SWRST Call
Abort. The TLC59116-Q1 does not initiate a reset of its registers. This happens only when the format of the Start
Call sequence is not correct.
9.3.6 Individual Brightness Control With Group Dimming/Blinking
A 97-kHz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control the individual
brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be applied to the four
LED outputs):
•
A lower 190-Hz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) provides a global
brightness control.
•
A programmable frequency signal from 24-Hz to 1/10.73 s (8 bits, 256 steps) provides a global blinking
control. See Figure 9.
14
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
N × 40 ns
with N = 0 to 255
(PWM register)
M × 256 × 2 × 40 ns
with M = 0 to 255
(GRPPWM register)
256 × 40 ns = 10.24 µs
(97.6 kHz)
Group Dimming Signal
256 × 2 × 256 × 40 ns = 5.24 ms (190.7 Hz)
Resulting Brightness + Group Dimming Signal
NOTE:
•
•
•
Minimum pulse width for LEDn brightness control is 40 ns.
Minimum pulse width for group dimming is 20.48 μs.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal has two
pulses of the LED Brightness Control signal (pulse width = n × 40 ns, with n defined in the PWMx register).
•
This resulting Brightness + Group Dimming signal shows a resulting control signal with M = 4 (8 pulses).
Figure 9. Brightness and Group Dimming Signals
9.4 Device Functional Modes
9.4.1 Active
Active mode occurs when one or more of the output channels is enabled.
9.4.2 Standby
Standby mode occurs when all output channels are disabled. Standby mode may be entered via I2C command or
by pulling the RESET pin low.
9.5 Programming
9.5.1 Characteristics of the I2C Bus
The I2C Bus is for two-way two-line communication between different devices or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a
pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus
is not busy.
9.5.1.1 Bit Transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see
Figure 10).
Copyright © 2016, Texas Instruments Incorporated
15
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
Programming (continued)
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 10. Bit Transfer
9.5.1.2 Start and Stop Conditions
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the
clock is high is defined as the Start condition (S). A low-to-high transition of the data line while the clock is high is
defined as the Stop condition (P) (see Figure 11).
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 11. Start and Stop Conditions
9.5.1.3 Acknowledge
The number of data bytes transferred between the Start and the Stop conditions from transmitter to receiver is
not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a high level put on
the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. See
Figure 12.
A slave receiver that is addressed must generate an acknowledge after the reception of each byte. Also a master
must generate an acknowledge after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable low during the high period of the acknowledge related clock pulse; set-up time and
hold time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event, the transmitter must leave the data line high to enable
the master to generate a Stop condition. See Figure 13.
16
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
Programming (continued)
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
Master
1
2
8
9
S
Start
Clock Pulse for
Condition
Acknowledgment
Figure 12. Acknowledge/Not Acknowledge on I2C Bus
Slave Address
Control Register
S
1
1
0
A3 A2 A1 A0
0
A
X
X
X
D4 D3 D2 D1 D0
A
A
P
Start Condition
R/W
ACK From Slave
Auto-Increment Options
ACK From Slave Stop Condition
Auto-Increment Flag
ACK From Slave
Figure 13. Write to a Specific Register
Slave Address
Control Register
MODE1 Register
MODE2 Register
S
1
1
0
A3 A2 A1 A0
0
A
1
0
0
0
0
0
0
0
A
A
A
Start Condition
R/W
ACK From Slave
MODE1 Register Selection
Auto-Increment On All Registers (see Note A)
Auto-Increment On
ACK From Slave
ACK From Slave
SUBADR3 Register
ALLCALLADR Register
A
A
P
ACK From Slave
ACK From Slave Stop Condition
See Table 4 for register definitions.
Figure 14. Write to All Registers Using Auto-Increment
Copyright © 2016, Texas Instruments Incorporated
17
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
Programming (continued)
Slave Address
Control Register
PWM0 Register
PWM1 Register
S A6 A5 A4 A3 A2 A1 A0
0
A
1
0
1
0
0
0
1
0
A
A
A
Start Condition
R/W
ACK From Slave
PWM0 Register Selection
Auto-Increment On Brightness Registers Only
Auto-Increment On
ACK From Slave
ACK From Slave
PWM14 Register
PWM15 Register
PWM0 Register
PWMx Register
A
A
A
A
P
ACK From Slave
ACK From Slave
ACK From Slave
ACK From Slave
Stop Condition
Figure 15. Multiple Writes to Individual Brightness Registers Using Auto-Increment
Slave Address
Control Register
Slave Address
Data From MODE1 Register
A
S
A6 A5 A4 A3 A2 A1 A0
0
A
1
0
0
0
0
0
0
0
A
Sr A6 A5 A4 A3 A2 A1 A0
1
A
Start Condition
R/W
ACK From Slave
MODE1 Register Selection
Auto-Increment On All Registers
Auto-Increment On
ACK From Slave
R/W ACK From Slave
ACK From Master
Data From MODE2 Register
Data From PWM0 Register
Data From ALLCALLADR Register Data From MODE1 Register
A
A
A
A
ACK From Master
ACK From Master
ACK From Master
ACK From Master
Data From Last Read Byte
A
P
NACK From Master
Stop Condition
Figure 16. Read All Registers Auto-Increment
18
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
Programming (continued)
New LED All Call I2C Address
(see Note B)
Slave Address
Control Register
S A6 A5 A4 A3 A2 A1 A0
0
A
X
X
X
1
1
0
1
1
A
1
1
0
1
1
0
1
X
A
P
Sequence A
Start Condition
R/W
ACK From Slave
ALLCALLADR Register Selection
Auto-Increment Options
Auto-Increment Flag
ACK From Slave
ACK From Slave Stop Condition
The 16 LEDs are on at ACK (see Note C)
LEDOUT0 Register (LED3 to 0 Fully On)
LED All Call I2C Address
Control Register
1
1
X
1
0
0
S
1
0
1
0
1
0
A
X
X
0
1
0
0
A
1
0
1
1
0
1
A
P
Sequence B
Start Condition
R/W
ACK From the
Four Slaves
ACK From the Stop Condition
Four Slaves
LEDOUT0 Register Selection
ACK From Slave
A. In this example, several TLC59116-Q1 devices are used, and the same Sequence A is sent to each of them.
B. The ALLCALL bit in the MODE1 register is equal to 1 for this example.
C. The OCH bit in the MODE2 register is equal to 1 for this example.
Figure 17. LED All Call I2C Bus Address Programming and LED All Call Sequence
9.5.2 System Configuration
A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the
message is the master and the devices that are controlled by the master are the slaves (see Figure 18).
SDA
SCL
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter/
Receiver
I2C Bus
Multiplexer
Slave
Receiver
Master
Transmitter
Slave
Figure 18. System Configuration
9.5.3 Device Address
Following a Start condition, the bus master must output the address of the slave it is accessing.
9.5.4 Regular I2C Bus Slave Address
The I2C Bus slave address of the TLC59116-Q1 is shown in Figure 19. To conserve power, no internal pullup
resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. For
buffer management purposes, a set of sector information data should be stored.
Copyright © 2016, Texas Instruments Incorporated
19
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
Programming (continued)
Slave Address
1
1
0
A3 A2 A1 A0 R/W
Hardware
Selectable
Fixed
Figure 19. Slave Address
The last bit of the address byte defines the operation to be performed. When set to logic 1, a read operation is
selected. When set to logic 0, a write operation is selected.
9.5.5 LED All Call I2C Bus Address
•
•
•
Default power-up value (ALLCALLADR register): D0h or 1101 000
Programmable through I2C Bus (volatile programming)
At power-up, LED All Call I2C Bus address is enabled. TLC59116-Q1 sends an ACK when D0h (R/W = 0) or
D1h (R/W = 1) is sent by the master.
See LED All Call I2C Bus Address Register (ALLCALLADR) for more detail.
NOTE
The default LED All Call I2C Bus address (D0h or 1101 000) must not be used as a
regular I2C Bus slave address, since this address is enabled at power-up. All the
TLC59116-Q1 devices on the I2C Bus will acknowledge the address if it is sent by the I2C
Bus master.
20
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
Programming (continued)
9.5.6 LED Sub Call I2C Bus Address
•
•
Three different I2C Bus addresses can be used
Default power-up values:
–
–
–
SUBADR1 register: D2h or 1101 001
SUBADR2 register: D4h or 1101 010
SUBADR3 register: D8h or 1101 100
•
•
Programmable through I2C Bus (volatile programming)
At power-up, Sub Call I2C Bus address is disabled. TLC59116-Q1 does not send an ACK when D2h (R/W =
0) or D3h (R/W = 1) or D4h (R/W = 0) or D5h (R/W = 1) or D8h (R/W = 0) or D9h (R/W = 1) is sent by the
master.
See I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3) for more detail.
NOTE
The LED Sub Call I2C Bus addresses may be used as regular I2C Bus slave addresses if
their corresponding enable bits are set to 0 in the MODE1 Register.
9.5.7 Software Reset I2C Bus Address
The address shown in Figure 20 is used when a reset of the TLC59116-Q1 is performed by the master. The
software reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the TLC59116-Q1 does not
acknowledge the SWRST. See Software Reset for more detail.
1
1
0
1
0
1
1
R/W
Figure 20. Software Reset Address
NOTE
The Software Reset I2C Bus address is reserved address and cannot be use as regular
I2C Bus slave address or as an LED All Call or LED Sub Call address.
9.5.8 Control Register
Following the successful acknowledgment of the slave address, LED All Call address or LED Sub Call address,
the bus master sends a byte to the TLC59116-Q1, which is stored in the Control register. The lowest five bits are
used as a pointer to determine which register is accessed (D[4:0]). The highest three bits are used as auto-
increment flag and auto-increment options (AI[2:0]). See Figure 21.
Auto-Increment
Flag
Register Address
AI2 AI1 AI0 D4 D3 D2 D1 D0
Auto-Increment
Options
Figure 21. Control Register
When the auto-increment flag is set (AI2 = logic 1), the five low order bits of the Control register are automatically
incremented after a read or write. This allows the user to program the registers sequentially. Four different types
of auto-increment are possible, depending on AI1 and AI0 values as shown in Table 3.
Copyright © 2016, Texas Instruments Incorporated
21
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
Programming (continued)
Table 3. Auto-Increment Options
AI2
0
AI1
0
AI0
0
DESCRIPTION
No auto-increment
1
0
0
Auto-increment for all registers. D[4:0] roll over to 0 0000 after the last register (1 1011) is accessed.
Auto-increment for individual brightness registers only. D[4:0] roll over to 0 0010 after the last register
(1 0001) is accessed.
1
1
1
0
1
1
1
0
1
Auto-increment for global control registers only. D[4:0] roll over to 1 0010 after the last register (1 0011) is
accessed.
Auto-increment for individual and global control registers only. D[4:0] roll over to 0 0010 after the last
register (1 0011) is accessed.
NOTE
Other combinations are not shown in Table 3. (AI[2:0] = 001, 010, and 011) are reserved
and must not be used for proper device operation.
AI[2:0] = 000 is used when the same register must be accessed several times during a single I2C Bus
communication, for example, changing the brightness of a single LED. Data is overwritten each time the register
is accessed during a write operation.
AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming.
AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the
same I2C Bus communication, for example, changing a color setting to another color setting.
AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same
I2C Bus communication, for example, global brightness or blinking change.
AI[2:0] = 111 is used when individually and global changes must be performed during the same I2C Bus
communication, for example, changing color and global brightness at the same time.
Only the five least significant bits D[4:0] are affected by the AI[2:0] bits.
When the Control register is written, the register entry point determined by D[4:0] is the first register that will be
addressed (read or write operation), and can be anywhere between 0 0000 and 1 1011 (as defined in Table 4).
When AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register
increment stops and goes to the next one is determined by AI[2:0]. See Table 3 for rollover values. For example,
if the Control register = 1111 0100 (F4h), then the register addressing sequence will be (in hex):
14 → ... → 1B → 00 → ... → 13 → 02 → ... → 13 → 02 → ... as long as the master keeps sending or reading
data.
9.6 Register Maps
Table 4 describes the registers in the TLC59116-Q1.
Table 4. Register Descriptions
REGISTER
NUMBER
(HEX)
(1)
NAME
MODE1
ACCESS
DESCRIPTION
00
01
02
03
04
05
06
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Mode 1
MODE2
PWM0
PWM1
PWM2
PWM3
PWM4
Mode 2
Brightness control LED0
Brightness control LED1
Brightness control LED2
Brightness control LED3
Brightness control LED4
(1) R = read, W = write
22
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
Register Maps (continued)
Table 4. Register Descriptions (continued)
REGISTER
NUMBER
(HEX)
(1)
NAME
ACCESS
DESCRIPTION
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
PWM5
PWM6
PWM7
PWM8
PWM9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Brightness control LED5
Brightness control LED6
Brightness control LED7
Brightness control LED8
Brightness control LED9
Brightness control LED10
Brightness control LED11
Brightness control LED12
Brightness control LED13
Brightness control LED14
Brightness control LED15
Group duty cycle control
Group frequency
PWM10
PWM11
PWM12
PWM13
PWM14
PWM15
GRPPWM
GRPFREQ
LEDOUT0
LEDOUT1
LEDOUT2
LEDOUT3
SUBADR1
SUBADR2
SUBADR3
ALLCALLADR
IREF
LED output state 0
LED output state 1
LED output state 2
LED output state 3
I2C Bus subaddress 1
I2C Bus subaddress 2
I2C Bus subaddress 3
LED All Call I2C Bus address
IREF configuration
EFLAG1
EFLAG2
Error flags 1
R
Error flags 2
Copyright © 2016, Texas Instruments Incorporated
23
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
9.6.1 Mode Register 1 (MODE1)
Table 5 describes Mode Register 1.
Table 5. MODE1 – Mode Register 1 (Address 00h) Bit Description
(1)
BIT
SYMBOL
ACCESS
VALUE
DESCRIPTION
Register auto-increment disabled
(2)
0
7
AI2
R
1
Register auto-increment enabled
Auto-increment bit 1 = 0
Auto-increment bit 1 = 1
Auto-increment bit 0 = 0
Auto-increment bit 0 = 1
(2)
0
6
5
4
3
2
1
0
AI1
AI0
R
1
(2)
0
R
1
0
(3)
Normal mode
OSC
R/W
R/W
R/W
R/W
R/W
(2)
1
Oscillator off.
(2)
0
Device does not respond to I2C Bus subaddress 1.
Device responds to I2C Bus subaddress 1.
Device does not respond to I2C Bus subaddress 2.
Device responds to I2C Bus subaddress 2.
Device does not respond to I2 CBus subaddress 3.
Device responds to I2C Bus subaddress 3.
Device does not respond to LED All Call I2C Bus address.
Device responds to LED All Call I2C Bus address.
SUB1
SUB2
SUB3
ALLCALL
1
(2)
0
1
(2)
0
1
0
(2)
1
(1) R = read, W = write
(2) Default value
(3) Requires 500 μs maximum for the oscillator to be up and running once OSC bit has been set to logic 1. Timings on LED outputs are not
ensured if PWMx, GRPPWM, or GRPFREQ registers are accessed within the 500-μs window.
NOTE
The OSC bit (Bit 4) must be set to 0 before any outputs will turn on. Proper operation
requires this bit to be 0. Setting the bit to a 1 will turn all channels off.
9.6.2 Mode Register 2 (MODE2)
Table 6 describes Mode Register 2.
Table 6. MODE2 – Mode Register 2 (Address 01h) Bit Description
(1)
BIT
7
SYMBOL
ACCESS
VALUE
DESCRIPTION
(2)
0
Enable error status flag
Clear error status flag
Reserved
EFCLR
R/W
R
1
(2)
6
0
(2)
0
Group control = dimming
Group control = blinking
Reserved
5
DMBLNK
OCH
R/W
R
1
(2)
4
0
(2)
(3)
0
Outputs change on Stop command
Outputs change on ACK
Reserved
3
R/W
R
1
(2)
2:0
000
(1) R = read, W = write
(2) Default value
(3) Change of the outputs at the Stop command allows synchronizing outputs of more than one TLC59116-Q1. Applicable to registers from
02h (PWM0) to 17h (LEDOUT3) only.
24
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
9.6.3 Brightness Control Registers 0 to 15 (PWM0 to PWM15)
Table 7 describes Brightness Control Registers 0 to 15.
Table 7. PWM0 to PWM15 – Brightness Control Registers 0 to 15 (Address 02h to 11h) Bit Description
(1)
ADDRESS
02h
REGISTER
PWM0
BIT
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
SYMBOL
IDC0[7:0]
IDC1[7:0]
IDC2[7:0]
IDC3[7:0]
IDC4[7:0]
IDC5[7:0]
IDC6[7:0]
IDC7[7:0]
IDC8[7:0]
IDC9[7:0]
IDC10[7:0]
IDC11[7:0]
IDC12[7:0]
IDC13[7:0]
IDC14[7:0]
IDC15[7:0]
ACCESS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VALUE
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
DESCRIPTION
PWM0 individual duty cycle
PWM1 individual duty cycle
PWM2 individual duty cycle
PWM3 individual duty cycle
PWM4 individual duty cycle
PWM5 individual duty cycle
PWM6 individual duty cycle
PWM7 individual duty cycle
PWM8 individual duty cycle
PWM9 individual duty cycle
PWM10 individual duty cycle
PWM11 individual duty cycle
PWM12 individual duty cycle
PWM13 individual duty cycle
PWM14 individual duty cycle
PWM15 individual duty cycle
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
03h
PWM1
04h
PWM2
05h
PWM3
06h
PWM4
07h
PWM5
08h
PWM6
09h
PWM7
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
PWM8
PWM9
PWM10
PWM11
PWM12
PWM13
PWM14
PWM15
10h
11h
(1) R = read, W = write
(2) Default value
A 97-kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from
00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable
to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0, LEDOUT1, LEDOUT2 and LEDOUT3 registers).
Duty cycle = IDCn[7:0] / 256
(1)
9.6.4 Group Duty Cycle Control Register (GRPPWM)
Table 8 describes the Group Duty Cycle Control Register.
Table 8. GRPPWM – Group Brightness Control Register (Address 12h) Bit Description
(1)
ADDRESS
REGISTER
BIT
SYMBOL
ACCESS
VALUE
DESCRIPTION
GRPPWM register
(2)
12h
GRPPWM
7:0
GDC0[7:0]
R/W
1111 1111
(1) R = read, W = write
(2) Default value
When the DMBLNK bit (MODE2 register) is programmed with logic 0, a 190-Hz fixed-frequency signal is
superimposed with the 97-kHz individual brightness control signal. GRPPWM is then used as a global brightness
control, allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a Don't
care.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED
output off) to FFh (99.6% duty cycle = maximum brightness). This is applicable to LED outputs programmed with
LDRx = 11 (LEDOUT0, LEDOUT1, LEDOUT2 and LEDOUT3 registers).
When DMBLNK bit is programmed with logic 1, the GRPPWM and GRPFREQ registers define a global blinking
pattern, where GRPFREQ defines the blinking period (from 24-Hz to 10.73 s) and GRPPWM defines the duty
cycle (ON/OFF ratio in %).
Duty cycle = GDC0[7:0] / 256
(2)
Copyright © 2016, Texas Instruments Incorporated
25
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
9.6.5 Group Frequency Register (GRPFREQ)
Table 9 describes the Group Frequency Register.
Table 9. GRPFREQ – Group Frequency Register (Address 13h) Bit Description
(1)
ADDRESS
REGISTER
BIT
SYMBOL
ACCESS
VALUE
DESCRIPTION
GRPFREQ register
(2)
13h
GRPFREQ
7:0
GFRQ[7:0]
R/W
0000 0000
(1) R = read, W = write
(2) Default value
GRPFREQ is used to program the global blinking period when the DMBLNK bit (MODE2 register) is equal to 1.
Value in this register is a Don't care when DMBLNK = 0. This is applicable to LED output programmed with
LDRx = 11 (LEDOUT0, LEDOUT1, LEDOUT2 and LEDOUT3 registers).
The blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 s).
Global blinking period (seconds) = (GFRQ[7:0] + 1) / 24
9.6.6 LED Driver Output State Registers 0 to 3 (LEDOUT0 to LEDOUT3)
Table 10 describes LED Driver Output State Registers 0 to 3.
Table 10. LEDOUT0 to LEDOUT3 – LED Driver Output State Registers 0 to 3 (Address 14h to 17h)
Bit Description
(1)
ADDRESS
REGISTER
BIT
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
7:6
5:4
3:2
1:0
SYMBOL
LDR3[1:0]
LDR2[1:0]
LDR1[1:0]
LDR0[1:0]
LDR7[1:0]
LDR6[1:0]
LDR5[1:0]
LDR4[1:0]
LDR11[1:0]
LDR10[1:0]
LDR9[1:0]
LDR8[1:0]
LDR15[1:0]
LDR14[1:0]
LDR13[1:0]
LDR12[1:0]
ACCESS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VALUE
DESCRIPTION
LED3 output state control
(2)
00
(2)
00
LED2 output state control
LED1 output state control
LED0 output state control
LED7 output state control
LED6 output state control
LED5 output state control
LED4 output state control
LED11 output state control
LED10 output state control
LED9 output state control
LED8 output state control
LED15 output state control
LED14 output state control
LED13 output state control
LED12 output state control
14h
LEDOUT0
(2)
00
(2)
00
(2)
00
(2)
00
15h
16h
17h
LEDOUT1
LEDOUT2
LEDOUT3
(2)
00
(2)
00
(2)
00
(2)
00
(2)
00
(2)
00
(2)
00
(2)
00
(2)
00
(2)
00
(1) R = read, W = write
(2) Default value
LDRx = 00: LED driver x is off (default power-up state).
LDRx = 01: LED driver x is fully on (individual brightness and group dimming/blinking not controlled).
LDRx = 10: LED driver x is individual brightness can be controlled through its PWMx register.
LDRx = 11: LED driver x is individual brightness and group dimming/blinking can be controlled through its PWMx
register and the GRPPWM registers.
26
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
9.6.7 I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3)
Table 11 describes I2C Bus Subaddress Registers 1 to 3.
Table 11. SUBADR1 to SUBADR3 – I2C Bus Subaddress Registers 1 to 3 (Address 18h to 1Ah)
Bit Description
(1)
ADDRESS
REGISTER
BIT
7:1
0
SYMBOL
A1[7:1]
A1[0]
ACCESS
VALUE
DESCRIPTION
I2C Bus subaddress 1
(2)
(2)
(2)
R/W
R
1101 001
18h
SUBADR1
(2)
0
Reserved
I2C Bus subaddress 2
7:1
0
A2[7:1]
A2[0]
R/W
R
1101 010
19h
1Ah
SUBADR2
SUBADR3
(2)
0
Reserved
7:1
0
A3[7:1]
A3[0]
R/W
R
1101 100
I2C Bus subaddress 3
Reserved
(2)
0
(1) R = read, W = write
(2) Default value
Subaddresses are programmable through the I2C Bus. Default power-up values are D2h, D4h, D8h. The
TLC59116-Q1 does not acknowledge these addresses immediately after power-up (the corresponding SUBx bit
in MODE1 register is equal to 0).
Once subaddresses have been programmed to valid values, the SUBx bits (MODE1 register) must be set to 1 to
allows the device to acknowledge these addresses.
Only the 7 MSBs representing the I2C Bus subaddress are valid. The LSB in SUBADRx register is a read-only bit
(0).
When SUBx is set to 1, the corresponding I2C Bus subaddress can be used during either an I2C Bus read or
write sequence.
9.6.8 LED All Call I2C Bus Address Register (ALLCALLADR)
Table 12 describes the LED All Call I2C Bus Address Register.
Table 12. ALLCALLADR – LED All Call I2C Bus Address Register (Address 1Bh) Bit Description
(1)
ADDRESS
REGISTER
BIT
7:1
0
SYMBOL
AC[7:1]
AC[0]
ACCESS
R/W
VALUE
DESCRIPTION
All Call I2C Bus address
Reserved
(2)
1101 000
1Bh
ALLCALLADR
(2)
R
0
(1) R = read, W = write
(2) Default value
The LED All Call I2C Bus address allows all the TLC59116-Q1 devices in the bus to be programmed at the same
time (ALLCALL bit in register MODE1 must be equal to 1, which is the power-up default state). This address is
programmable through the I2C Bus and can be used during either an I2C Bus read or write sequence. The
register address can also be programmed as a Sub Call.
Only the seven MSBs representing the All Call I2C bus address are valid. The LSB in ALLCALLADR register is a
read-only bit (0).
If ALLCALL bit = 0, the device does not acknowledge the address programmed in register ALLCALLADR.
Copyright © 2016, Texas Instruments Incorporated
27
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
9.6.9 Output Gain Control Register (IREF)
Table 13 describes the Output Gain Control Register.
Table 13. IREF – Output Gain Control Register (Address 1Ch) Bit Description
(1)
ADDRESS
REGISTER
BIT
7
SYMBOL
CM
ACCESS
R/W
VALUE
DESCRIPTION
High/low current multiplier
Subcurrent
(2)
1
(2)
1Ch
IREF
6
HC
R/W
1
(2)
5:0
CC[5:0]
R/W
11 1111
Current multiplier
(1) R = read, W = write
(2) Default value
IREF determines the voltage gain (VG), which affects the voltage at the REXT terminal and indirectly the
reference current (Iref) flowing through the external resistor at terminal REXT. Bit 0 is the Current Multiplier (CM)
bit, which determines the ratio IOUT,target/Iref. Each combination of VG and CM sets a Current Gain (CG).
•
VG: the relationship between {HC,CC[0:5]} and the voltage gain is calculated as shown:
VG = (1 + HC) × (1 + D/64) / 4
D = CC0 × 25 + CC1 × 24 + CC2 × 23 + CC3 × 22 + CC4 × 21 + CC5 × 20
Where HC is 1 or 0, and D is the binary value of CC[0:5]. So, the VG could be regarded as a floating-point
number with 1-bit exponent HC and 6-bit mantissa CC[0:5]. {HC,CC[0:5]} divides the programmable voltage
gain (VG) into 128 steps and two sub-bands:
Low-voltage subband (HC = 0): VG = 1/4 to 127/256, linearly divided into 64 steps
High-voltage subband (HC = 1): VG = 1/2 to 127/128, linearly divided into 64 steps
CM: In addition to determining the ratio IOUT,target/Iref, CM limits the output current range.
High Current Multiplier (CM = 1): IOUT,target/Iref = 15, suitable for output current range IOUT = 10 mA to 120 mA.
Low Current Multiplier (CM = 0): IOUT,target/Iref = 5, suitable for output current range IOUT = 5 mA to 40 mA
CG: The total Current Gain is defined as:
•
•
VREXT = 1.26 V × VG
Iref = VREXT/Rext, if the external resistor (Rext) is connected to ground.
IOUT,target = Iref × 15 × 3CM – 1 = 1.26 V/Rext × VG × 15 × 3CM – 1 = (1.26 V/Rext × 15) × CG
CG = VG × 3CM – 1
Therefore, CG = (1/12) to (127/128), divided into 256 steps.
Examples
•
•
•
IREF Code {CM, HC, CC[0:5]} = {1,1,111111}
VG = 127/128 = 0.992 and CG = VG × 30 = VG = 0.992
IREF Code {CM, HC, CC[0:5]} = {1,1,000000}
VG = (1 + 1) × (1 + 0/64)/4 = 1/2 = 0.5, and CG = 0.5
IREF Code {CM, HC, CC[0:5]} = {0,0,000000}
VG = (1 + 0) × (1 + 0/64)/4 = 1/4, and CG = (1/4) × 3–1 = 1/12
After power-on, the default value of the Configuration Code {CM, HC, CC[0:5]} is {1,1,111111}. Therefore,
VG = CG = 0.992. The relationship between the Configuration Code and the Current Gain is shown in Figure 22.
28
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
1.00
0.75
0.50
0.25
0.00
CM = 1 (High Current Multiplier)
CM = 0 (Low Current Multiplier)
HC = 0 (Low
Voltage SubBand)
HC = 1 (High HC = 0 (Low
Voltage SubBand) Voltage SubBand)
HC = 1 (High
Voltage SubBand)
Configuration Code (CM, HC, CC[0:5]) in Binary Format
Figure 22. Current Gain vs Configuration Code
9.6.10 Error Flags Registers (EFLAG1, EFLAG2)
Table 14 describes Error Flags Registers 1 and 2.
Table 14. EFLAG1, EFLAG2 – Error Flags Registers (Address 1Dh and 1Eh) Bit Description
(1)
(2)
(3)
ADDRESS
REGISTER
BIT
0
SYMBOL
EFLAG1[0]
EFLAG1[1]
EFLAG1[2]
EFLAG1[3]
EFLAG1[4]
EFLAG1[5]
EFLAG1[6]
EFLAG1[7]
EFLAG1[0]
EFLAG1[1]
EFLAG1[2]
EFLAG1[3]
EFLAG1[4]
EFLAG1[5]
EFLAG1[6]
EFLAG1[7]
ACCESS
VALUE
DESCRIPTION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
Channel 9
Channel 10
Channel 11
Channel 12
Channel 13
Channel 14
Channel 15
1
2
3
1Dh
EFLAG1
R
4
5
6
7
0
1
2
3
1Eh
EFLAG2
R
4
5
6
7
(1) R = read, W = write
(2) Default value
(3) At power-up, in order to initialize the Error Flags registers, the host must write 1 to bit 7 of the MODE2 register and then write 0 to bit 7
of the MODE2 register.
Copyright © 2016, Texas Instruments Incorporated
29
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Constant Current Output
In LED display applications, TLC59116-Q1 provides nearly no current variations from channel to channel and
from device to device. While IOUT ≤ 52 mA, the maximum current skew between channels is less than ±6% and
less than ±10% between devices.
10.1.2 Adjusting Output Current
TLC59116-Q1 scales up the reference current (Iref) set by the external resistor (Rext) to sink the output current
(Iout) at each output port. Table 13 shows the Configuration Code and discusses bits CM, HC, and CC[5:0]. The
following formulas can be used to calculate the target output current IOUT,target in the saturation region:
VREXT = 1.26 V × VG
(3)
(4)
(5)
Iref = VREXT/Rext, if another end of the external resistor Rext is connected to ground
IOUT,target = Iref × 15 × 3CM – 1
Where Rext is the resistance of the external resistor connected to the REXT terminal, and VREXT is the voltage of
REXT, which is controlled by the programmable voltage gain (VG), which is defined by the Configuration Code.
The Current Multiplier bit (CM) sets the ratio IOUT,target/Iref to 15 or 5 (sets the exponent CM – 1 to either 0 or –1).
After power-on, the default value of VG is 127/128 = 0.992, and the default value of CM is 1, so that the ratio
IOUT,target/Iref = 15. Based on the default VG and CM:
VREXT = 1.26 V × 127/128 = 1.25 V
IOUT,target = (1.25 V/Rext) × 15
(6)
(7)
Therefore, the default current is approximately 20 mA at 931 Ω. The default relationship after power-on between
IOUT,target and Rext is shown in Figure 24.
shows the output voltage versus the output current with several different resistor values on REXT. This shows
the minimum voltage required at the device to have full VF across the LED. The VLED voltage must be higher
than the VF plus the VOL of the driver. If the VLED is too high, more power will be dissipated in the driver. If this
is the case, a resistor can be inserted in series with the LED to dissipate the excess power and reduce the
thermal conditions on the driver.
If a single driver is used with LEDs that have different VF values, resistors can also be used in series with the
LED to remove the excess power from the driver. In cases where not all outputs are being used, the unused
outputs can be left floating without issue.
30
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
10.2 Typical Application
The TLC59116-Q1 outputs can be wired in parallel to increase the current per LED string.
VLED
VCC
VCC
SDA
SCL
SDA
SCL
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
A0
A1
A2
A3
RESET
RESET
REXT
GND
Address: 00h
Figure 23. Parallel Channels
10.2.1 Design Requirements
Set the LED current to 50 mA while the IREF register is at the default value (CG = 0.992).
10.2.2 Detailed Design Procedure
The goal of this design is to set the LED current to 50 mA. Because two outputs are in parallel, the LED current
should actually be set to 25 mA. With the IREF register at the default value:
IOUT,target = ( 1.25 V / REXT ) × 15
(8)
Using this equation, the appropriate REXT is calculated to be 750 Ω.
Copyright © 2016, Texas Instruments Incorporated
31
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
Typical Application (continued)
10.2.3 Application Curve
140
120
100
80
60
40
20
0
0
500
1000
1500
2000
2500
3000
3500
4000
R
(W)
ext
Figure 24. IOUT,target vs Rext
32
Copyright © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
11 Power Supply Recommendations
TLC59116-Q1 is designed to operate from a VCC range of 3 V to 5.5 V.
12 Layout
12.1 Layout Guidelines
The I2C signals (SDA / SCL) should be kept away from potential noise sources.
The traces carrying power through the LEDs should be wide enough to the handle necessary current.
All LED current passes through the device and into the ground node. The connection between the device ground
and the circuit board ground must be a strong connection.
12.2 Layout Example
VIA to GND
REXT
A0
VCC
SDA
To µ/
To µ/
To µ/
A1
SCL
A2
RESET
GND
A3
OUT0
OUT1
OUT2
OUT3
GND
OUT4
OUT5
OUT6
OUT7
OUT15
OUT14
OUT13
OUT12
GND
OUT11
OUT10
OUT9
OUT8
Figure 25. PW-28 Layout Example
Copyright © 2016, Texas Instruments Incorporated
33
TLC59116-Q1
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
www.ti.com.cn
12.3 Thermal Considerations
The maximum IC junction temperature should be restricted to 150°C under normal operating conditions. To
calculate the maximum allowable dissipation, PD(max) for a given ambient temperature, use Equation 9 as a
guideline:
TJ(max) - TA
=
P
D(max)
θJA
where
•
•
•
•
PD(max) = maximum allowable power dissipation
TJ(max) = maximum allowable junction temperature (150°C for the TLC59116-Q1)
TA = ambient temperature of the device
ΘJA = junction to air thermal impedance.
(9)
See Thermal Information section. This parameter is highly dependent upon board layout.
Power dissipation in the device is determined by the LED current and the voltage at the OUTx pins. For example,
if the LED current is 50 mA continuous through each channel and the output voltage is 1 V on each channel,
then the total power dissipation is 50 mA × 1 V × 16 ch = 0.8 W.
34
版权 © 2016, Texas Instruments Incorporated
TLC59116-Q1
www.ti.com.cn
ZHCSEQ9A –MARCH 2016–REVISED MARCH 2016
13 器件和文档支持
13.1 文档支持
13.1.1 相关文档ꢀ
相关文档如下：
•
•
《TLC59116EVM-390 用户指南》，SLVU296
TLC59116FEVM-571，SLVU367
13.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对
本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2016, Texas Instruments Incorporated
35
重要声明
德州仪器(TI) 及其下属子公司有权根据 JESD46 最新标准, 对所提供的产品和服务进行更正、修改、增强、改进或其它更改， 并有权根据
JESD48 最新标准中止提供任何产品和服务。客户在下订单前应获取最新的相关信息, 并验证这些信息是否完整且是最新的。所有产品的销售
都遵循在订单确认时所提供的TI 销售条款与条件。
TI 保证其所销售的组件的性能符合产品销售时 TI 半导体产品销售条件与条款的适用规范。仅在 TI 保证的范围内，且 TI 认为 有必要时才会使
用测试或其它质量控制技术。除非适用法律做出了硬性规定，否则没有必要对每种组件的所有参数进行测试。
TI 对应用帮助或客户产品设计不承担任何义务。客户应对其使用 TI 组件的产品和应用自行负责。为尽量减小与客户产品和应 用相关的风险，
客户应提供充分的设计与操作安全措施。
TI 不对任何 TI 专利权、版权、屏蔽作品权或其它与使用了 TI 组件或服务的组合设备、机器或流程相关的 TI 知识产权中授予 的直接或隐含权
限作出任何保证或解释。TI 所发布的与第三方产品或服务有关的信息，不能构成从 TI 获得使用这些产品或服 务的许可、授权、或认可。使用
此类信息可能需要获得第三方的专利权或其它知识产权方面的许可，或是 TI 的专利权或其它 知识产权方面的许可。
对于 TI 的产品手册或数据表中 TI 信息的重要部分，仅在没有对内容进行任何篡改且带有相关授权、条件、限制和声明的情况 下才允许进行
复制。TI 对此类篡改过的文件不承担任何责任或义务。复制第三方的信息可能需要服从额外的限制条件。
在转售 TI 组件或服务时，如果对该组件或服务参数的陈述与 TI 标明的参数相比存在差异或虚假成分，则会失去相关 TI 组件 或服务的所有明
示或暗示授权，且这是不正当的、欺诈性商业行为。TI 对任何此类虚假陈述均不承担任何责任或义务。
客户认可并同意，尽管任何应用相关信息或支持仍可能由 TI 提供，但他们将独力负责满足与其产品及在其应用中使用 TI 产品 相关的所有法
律、法规和安全相关要求。客户声明并同意，他们具备制定与实施安全措施所需的全部专业技术和知识，可预见 故障的危险后果、监测故障
及其后果、降低有可能造成人身伤害的故障的发生机率并采取适当的补救措施。客户将全额赔偿因 在此类安全关键应用中使用任何 TI 组件而
对 TI 及其代理造成的任何损失。
在某些场合中，为了推进安全相关应用有可能对 TI 组件进行特别的促销。TI 的目标是利用此类组件帮助客户设计和创立其特 有的可满足适用
的功能安全性标准和要求的终端产品解决方案。尽管如此，此类组件仍然服从这些条款。
TI 组件未获得用于 FDA Class III（或类似的生命攸关医疗设备）的授权许可，除非各方授权官员已经达成了专门管控此类使 用的特别协议。
只有那些 TI 特别注明属于军用等级或“增强型塑料”的 TI 组件才是设计或专门用于军事/航空应用或环境的。购买者认可并同 意，对并非指定面
向军事或航空航天用途的 TI 组件进行军事或航空航天方面的应用，其风险由客户单独承担，并且由客户独 力负责满足与此类使用相关的所有
法律和法规要求。
TI 已明确指定符合 ISO/TS16949 要求的产品，这些产品主要用于汽车。在任何情况下，因使用非指定产品而无法达到 ISO/TS16949 要
求，TI不承担任何责任。
产品
应用
www.ti.com.cn/telecom
数字音频
www.ti.com.cn/audio
www.ti.com.cn/amplifiers
www.ti.com.cn/dataconverters
www.dlp.com
通信与电信
计算机及周边
消费电子
能源
放大器和线性器件
数据转换器
DLP® 产品
DSP - 数字信号处理器
时钟和计时器
接口
www.ti.com.cn/computer
www.ti.com/consumer-apps
www.ti.com/energy
www.ti.com.cn/dsp
工业应用
医疗电子
安防应用
汽车电子
视频和影像
www.ti.com.cn/industrial
www.ti.com.cn/medical
www.ti.com.cn/security
www.ti.com.cn/automotive
www.ti.com.cn/video
www.ti.com.cn/clockandtimers
www.ti.com.cn/interface
www.ti.com.cn/logic
逻辑
电源管理
www.ti.com.cn/power
www.ti.com.cn/microcontrollers
www.ti.com.cn/rfidsys
www.ti.com/omap
微控制器 (MCU)
RFID 系统
OMAP应用处理器
无线连通性
www.ti.com.cn/wirelessconnectivity
德州仪器在线技术支持社区
www.deyisupport.com
IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2016, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC59116ITPWRQ1
TLC59116ITPWTQ1
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
28
28
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
Y59116Q
Y59116Q
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
©2020 ICPDF网 联系我们和版权申明