TLC5942PWP_技术文档

TLC5942

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

16-Channel, 12-Bit PWM LED Driver with

7-Bit Dot Correction

1

FEATURES

•

Readable Error Information:

23

•

16 Channels, Constant Current Sink Output

–

LED Open Detection

•

50-mA Capability (Constant Current Sink)

Thermal Error Flag (TEF)

12-Bit (4096 Steps) Grayscale Control with

PWM

•

Noise Reduction:

–

4-Channel grouped delay to prevent inrush

current

•

7-Bit (128 Steps) Dot Correction with Sink

Current

Operating Temperature: –40°C to +85°C

•

LED Power-Supply Voltage up to 17 V

Constant Current Accuracy:

APPLICATIONS

•

Monochrome, Multicolor, Full-Color LED

Displays

–

Channel-to-Channel = ±1.5%

Device-to-Device = ±3%

•

LED Signboards

Display Backlighting

•

VCC = 3.0 V to 5.5 V

CMOS Level I/O

30-MHz Data Transfer Rate

30-MHz Grayscale Control Clock

DESCRIPTION

The TLC5942 is a 16-channel, constant current sink

driver. Each channel is individually adjustable with

4096 pulse-width modulated (PWM) steps and 128

constant current sink steps for dot correction. Dot

correction adjusts the brightness variations between

LEDs. Both grayscale control and dot correction are

accessible via separate, dedicated serial interface

ports. The maximum current value of all 16 channels

can be set by a single external resistor.

Dedicated Ports for Grayscale and Dot

Correction

•

Continuous Base LED Open Detection (LOD)

Thermal Shutdown (TSD):

–

Automatic shutdown at high temperature

conditions

–

Restart under normal temperature

VLED

¼

OUT0

OUT15

OUT0

OUT15

GSDATA

GSSIN

GSSOUT

GSSIN

GSSCLK

GSSOUT

GSSCLK

Controller

GSSCLK

for Grayscale

(Outside of

LED module)

XGSLAT

BLANK

TLC5942

IC1

TLC5942

ICn

XGSLAT

BLANK

DCSIN

DCSCLK

XDCLAT

IREF

XGSLAT

BLANK

DCSIN

DCSCLK

XDCLAT

IREF

ERROR

READ

DCSOUT

VCC

GND

VCC

GND

R_IREF

DCDATA

DCSCLK

XDCLAT

Controller for

Dot Correction

with

Correction

Data ROM

(Inside of

LED module)

Typical Application Circuit (Multiple Daisy-Chained TLC5942s)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

PowerPAD is a trademark of Texas Instruments, Inc.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TLC5942

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

DESCRIPTION, CONTINUED

The TLC5942 has two error detection circuits for LED open detection (LOD) and a thermal error flag (TEF). LOD

detects a broken or disconnected LED during the display period. TEF indicates an over-temperature condition;

when a TEF is set, all output drivers are turned off. When the TEF is cleared, all output drivers are restarted.

blank

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION⁽¹⁾

TRANSPORT MEDIA,

PRODUCT

PACKAGE-LEAD

ORDERING NUMBER

TLC5942PWPR

TLC5942PWP

QUANTITY

Tape and Reel, 2000

Tube, 50

TLC5942

HTSSOP-28 PowerPAD™

TLC5942RHBR

TLC5942RHBT

Tape and Reel, 3000

Tape and Reel, 250

TLC5942

5 mm × 5 mm QFN-32

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾⁽²⁾

Over operating free-air temperature range, unless otherwise noted.

PARAMETER

TLC5942

–0.3 to +6.0

60

UNIT

V

VCC

I_OUT

Supply voltage, VCC

Output current (dc): OUT0 to OUT15

mA

Input voltage range:

GSSIN, GSSCLK, XGSLAT, DCSIN, DCSCLK, XDCLAT, BLANK, IREF

V_IN

–0.3 to VCC + 0.3

V

GSSOUT, DCSOUT

OUT0 to OUT15

–0.3 to VCC + 0.3

Output voltage

range

V_OUT

–0.3 to +18

+150

T_J(max)

T_STG

Maximum operating junction temperature

Storage temperature range

°C

–55 to +150

2

Human body model (HBM)

Charged device model (CDM)

kV

V

ESD rating

500

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not supported.

(2) All voltage values are with respect to network ground terminal.

2

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

RECOMMENDED OPERATING CONDITIONS

At T_A= –40°C to +85°C, unless otherwise noted.

TLC5942

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

DC Characteristics: VCC = 3 V to 5.5 V

VCC

V_O

Supply voltage

3.0

5.5

V

Voltage applied to output

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Constant output sink current

Operating free-air temperature

OUT0 to OUT15

17

V_IH

V_IL

0.7 × VCC

VCC

V

GND

0.3 × VCC

V

I_OH

I_OL

I_OLC

T_A

GSSOUT, DCSOUT

OUT0 to OUT15

–1

1

mA

°C

50

–40

+85

Operating junction

temperature

T_J

+125

°C

AC Characteristics: VCC = 3 V to 5.5 V

f_{CLK (dcsclk)}

f_{CLK (gssclk)}

T_WH0/ T_WL0

T_WH1

Data shift clock frequency

DCSCLK

GSSCLK

30

MHz

Data shift/grayscale control

clock frequency

GSSCLK (see Figure 9),

DCSCLK (see Figure 10)

10

30

3

ns

Pulse duration

XGSLAT, BLANK (see Figure 9),

XDCLAT (see Figure 10)

GSSIN–GSSCLK ↑ (see Figure 9),

DCSIN–DCSCLK ↑ (see Figure 10)

T_SU0

BLANK ↓– GSSCLK ↑

T_SU1

10

(see Figure 9)

XGSLAT ↑ – GSSCLK↑

(see Figure 9),

XDCLAT ↑ – DCSCLK↑

(see Figure 10)

Setup time

T_SU2

100

ns

XGSLAT ↓ – GSSCLK↑

(see Figure 9 and Figure 11)

T_SU3

T_H0

15

3

ns

GSSIN–GSSCLK ↑ (see Figure 9),

DCSIN–DCSCLK ↑ (see Figure 10)

XGSLAT ↑ – GSSCLK↑

(see Figure 9),

XDCLAT ↑ – DCSCLK↑

(see Figure 10)

Hold time

T_H1

30

ns

DISSIPATION RATINGS

DERATING FACTOR

T_A< +25°C

T_A= +70°C

T_A= +85°C

PACKAGE

ABOVE T_A= +25°C

POWER RATING

HTSSOP-28 with

31.67 mW/°C

3958 mW

2533 mW

2058 mW

PowerPAD soldered⁽¹⁾

HTSSOP-28 with

16.21 mW/°C

27.86 mW/°C

2026 mW

3482 mW

1296 mW

2228 mW

1053 mW

1811 mW

PowerPAD not soldered⁽²⁾

QFN-32⁽³⁾

(1) With PowerPAD soldered onto copper area on printed circuit board (PCB); 2 oz. copper. For more information, see SLMA002 (available

for download at www.ti.com).

(2) With PowerPAD not soldered onto copper area on PCB.

(3) The package thermal impedance is calculated in accordance with JESD51-5.

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

ELECTRICAL CHARACTERISTICS

At VCC = 3.0 V to 5.5 V, and T_A= –40°C to +85°C. Typical values at VCC = 3.3 V and T_A= +25°C, unless otherwise noted.

TLC5942

PARAMETER

TEST CONDITIONS

I_OH= –1 mA at GSSOUT, DCSOUT

I_OL= 1 mA at GSSOUT, DCSOUT

MIN

VCC – 0.4

0

TYP

MAX

VCC

0.4

UNIT

V

V_OH

V_OL

High-level output voltage

Low-level output voltage

V

V_IN= VCC or GND at GSSIN, GSSCLK,

XGSLAT, DCSIN, DCSCLK, XDCLAT, BLANK

I_IN

Input current

–1

1

3

µA

No data transfer, all OUTn = OFF, DCn = 7Fh,

V_OUTn= 1 V, R_IREF= 10 kΩ

I_CC1

1

4

No data transfer, all OUTn = OFF, DCn = 7Fh,

V_OUTn= 1 V, R_IREF= 2 kΩ

I_CC2

8

Supply current

mA

Data transfer 30 MHz, all OUTn = ON,

DCn = 7Fh, V_OUTn= 1 V, R_IREF= 2 kΩ

I_CC3

14

27

49

30

50

55

0.1

±5

±8

±4

±3

Data transfer 30 MHz, all OUTn = ON,

DCn = 7Fh, V_OUTn= 1 V, R_IREF= 1 kΩ

I_CC4

All OUTn = ON, DCn = 7Fh, V_OUTn= 1 V,

V_OUTfix= 1 V, R_IREF= 1 kΩ

I_O(LC)

I_O(LKG)

ΔI_O(LC)

ΔI_O(LC1)

ΔI_O(LC2)

ΔI_O(LC3)

Constant output current

Leakage output current

43

mA

µA

All OUTn = OFF, DCn = 7Fh, V_OUTn= 17 V,

R_IREF= 1 kΩ

Constant current error

(channel-to-channel)⁽¹⁾

All OUTn = ON, DCn = 7Fh, V_OUTn= 1 V,

V_OUTfix= 1 V, R_IREF= 1 kΩ

±1.5

±3

%

Constant current error

(device-to-device)⁽²⁾

All OUTn = ON, DCn = 7Fh, V_OUTn= 1 V,

V_OUTfix= 1 V, R_IREF= 1 kΩ

%

All OUTn = ON, DCn = 7Fh, V_OUTn= 1 V,

V_OUTfix= 1 V, R_IREF= 1 kΩ, VCC = 3 V to 5.5 V

Line regulation⁽³⁾

Load regulation⁽⁴⁾

±1

%/V

All OUTn = ON, DCn = 7Fh,

V_OUTn= 1 V to 3 V, V_OUTfix= 1 V, R_IREF= 1 kΩ

±1

T_(TEF)

T_(HYS)

Thermal error flag threshold Junction temperature⁽⁵⁾

+150

+5

+162

+10

+175

+20

°C

Thermal error hysteresis

Junction temperature⁽⁵⁾

LED open detection

threshold

V_LOD

V_IREF

All OUTn = ON

0.2

0.3

0.4

V

Reference voltage output

R_IREF= 1 kΩ

1.16

1.20

1.24

(1) The deviation of each output from the average of OUT0–OUT15 constant current. Deviation is calculated by the formula:

I_OUTn

D (%) =

- 1 ´ 100

(I_OUT0+ I_OUT1+ ... + I_OUT15

)

16

.

(2) The deviation of the OUT0–OUT15 constant current average from the ideal constant current value.

(I_OUT0+ I_OUT1+ ... I_OUT14+ I_OUT15

)

- (Ideal Output Current)

16

D (%) =

´ 100

Ideal Output Current

Deviation is calculated by the following formula:

I_OUT(IDEAL)= 41 ´

1.20

R_IREF

Ideal current is calculated by the formula:

(I_OUTnat V_CC= 5.5 V) - (I_OUTnat V_CC= 3.0 V)

100

D (%/V) =

´

(I_OUTnat V_CC= 3.0 V)

5.5 V - 3 V

(3) Line regulation is calculated by this equation:

(I_OUTnat V_OUTn= 3 V) - (I_OUTnat V_OUTn= 1 V)

100

´

3 V - 1 V

(I_OUTnat V_OUTn= 1 V)

(4) Load regulation is calculated by the equation:

(5) Not tested; specified by design.

4

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

SWITCHING CHARACTERISTICS

At VCC = 3.0 V to 5.5 V, T_A= –40°C to +85°C, C_L= 15 pF, R_L= 82 Ω, R_IREF= 1 kΩ, and V_LED= 5.0 V. Typical values at

VCC = 3.3 V and T_A= +25°C, unless otherwise noted.

TLC5942

PARAMETER

Rise time

TEST CONDITIONS

GSSOUT (see Figure 9)

DCSOUT (see Figure 10)

MIN

TYP

MAX

16

UNIT

t_R0

t_R1

t_F0

t_F1

t_D0

ns

OUTn, DCn = 7Fh (see Figure 9)

10

30

GSSOUT (see Figure 9)

DCSOUTn (see Figure 10)

16

Fall time

ns

OUTn, DCn = 7Fh (see Figure 9)

10

30

GSSCLK ↑ – GSSOUT (see Figure 9)

DCSCLK ↑ – DCSOUT (see Figure 10)

25

ns

BLANK ↑ – OUT0 current sink off

(see Figure 9)

t_D1

20

18

42

66

90

40

GSSCLK ↑ – OUT0, 4, 8, 12

(see Figure 9)

t_D2

5

20

Propagation delay time

GSSCLK ↑ – OUT1, 5, 9, 13

(see Figure 9)

t_D3

73

GSSCLK ↑ – OUT2, 6, 10, 14

(see Figure 9)

t_D4

35

106

140

10

GSSCLK ↑ – OUT3, 7, 11, 15

(see Figure 9)

t_D5

50

t_OUTON– T_GSSCLK, GSn = 001h,

GSSCLK = 30 MHz (see Figure 9)

t_{ON_ERR}

Output on-time error

–20

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

FUNCTIONAL BLOCK DIAGRAM

VCC

33rd GSSCLK Signal After BLANK Goes Low

LED Open Detection Data Latch

(16 LOD)

VCC

16

LSB

MSB

GSSIN

Grayscale Shift Register

(12 Bits x 16 Channels)

GSSOUT

0

191

192

GSSCLK

XGSLAT

LSB

MSB

Grayscale Data Latch

(12 Bits x 16 Channels)

0

191

LSB

MSB

DCSIN

Dot Correction Shift Register

(7 Bits x 16 Channels)

DCSOUT

0

111

112

DCSCLK

XDCLAT

192

16

LSB

MSB

Dot Correction Data Latch

(7 Bits x 16 Channels)

0

111

112

12-Bit PWM Timing Control

16

12

Grayscale

Counter

Thermal

Detection

Output Switching Delay

(4-Channel Unit)

BLANK

16

Constant Current Driver with Dot Correction

(16 Channels)

Reference

Current

Control

IREF

GND

LED Open Detection

(LOD, 16 Channels)

GND

¼

OUT0

OUT1

OUT14 OUT15

6

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

DEVICE INFORMATION

PWP PACKAGE

(Top View)

RHB PACKAGE

(Top View)

GND

DCSCLK

DCSIN

GSSCLK

GSSIN

XGSLAT

OUT7

1

2

3

4

5

6

7

8

9

28 VCC

27 IREF

26 XDCLAT

25 DCSOUT

24 GSSOUT

23 BLANK

22 OUT15

21 OUT14

20 OUT13

19 OUT12

1

2

3

4

5

6

7

8

24 DCSOUT

23 GSSOUT

22 BLANK

GSSCLK

GSSIN

XGSLAT

OUT7

21 OUT15

Thermal

Pad

Thermal

Pad

OUT6

20 OUT14

OUT6

OUT5

19 OUT13

18 OUT12

17 OUT11

OUT5

OUT4 10

11

OUT4

OUT3

18

OUT11

OUT3

OUT2 12

OUT1 13

OUT0 14

17 OUT10

16 OUT9

15 OUT8

NC = No connection.

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

TERMINAL FUNCTIONS

TERMINAL

NAME

GSSIN

PWP

RHB

I/O

DESCRIPTION

5

2

I

Serial data input for grayscale.

Serial data shift clock for grayscale and reference clock for Grayscale PWM control. Data present

on the GSSIN pin are shifted into the Grayscale Shift Register with each rising edge of the

GSSCLK pin. Data are shifted into the LSB of the register with each rising edge. The MSB of the

register is shifted to the GSSOUT pin with each rising edge. If BLANK is low, then each rising

edge of GSSCLK increments the grayscale counter for PWM control.

GSSCLK

4

1

I

Data in the shift register are moved to the grayscale data latch with a low-to-high transition of this

pin.

XGSLAT

6

3

I

Serial data output for Grayscale/Status information data. This signal is connected to MSB of

Grayscale Shift Register.

GSSOUT

DCSIN

24

3

23

32

O

I

Serial data input for Dot Correction.

Serial data shift clock for dot correction. Data present on the DCSIN pin are shifted into the dot

correction shift register with each rising edge of the DCSCLK pin. Data are shifted into the LSB of

the register with each rising edge. The MSB of the register is shifted to the DCSOUT pin with

each rising edge.

DCSCLK

2

31

I

Data in the shift register are moved to the dot correction data latch with a low-to-high transition of

this pin.

XDCLAT

DCSOUT

26

25

24

I

Serial data output for dot correction. This signal is connected to the MSB of the Dot Correction

Shift Register.

O

Blank (all constant current outputs off). When BLANK is high, all constant current outputs (OUT0

through OUT15) are forced off, the Grayscale counter is reset to '0', and the Grayscale PWM

timing controller is initialized. When BLANK is low, all constant current outputs are controlled by

the Grayscale PWM timing controller.

BLANK

23

22

I

Constant current value setting. OUT0 through OUT15 sink constant current is set to desired

value by connecting an external resistor between IREF and GND.

IREF

27

26

I/O

OUT0

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

OUT9

OUT10

OUT11

OUT12

OUT13

OUT14

OUT15

VCC

14

13

12

11

10

9

11

10

9

O

—

Constant current output

Power-supply voltage

Power ground

8

7

6

8

5

7

4

15

16

17

18

19

20

21

22

28

1

14

15

16

17

18

19

20

21

27

30

GND

12, 13,

28, 29

NC

—

No internal connection

8

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

PARAMETER MEASUREMENT INFORMATION

PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

VCC

INPUT

GND

SOUT

GND

Figure 1. GSSIN, GSSCLK, XGSLAT, DCSIN, DCSCLK,

XDCLAT, BLANK

Figure 2. SOUT

OUTn

GND

Figure 3. OUT0 Through OUT15

TEST CIRCUITS

R_L

C_L

VCC

GND

VCC

GSSOUT/

DCSOUT

IREF

OUTn

VLED

VCC

(1)

C_L

R_IREF

GND

(1) C_Lincludes measurement probe and jig

capacitance.

Figure 4. Rise Time and Fall Time Test Circuit for OUTn

(1) C_Lincludes measurement probe and jig

capacitance.

Figure 5. Rise Time and Fall Time Test Circuit for

GSSOUT/DCSOUT

VCC

OUT0

OUTn

VCC

IREF

R_IREF

GND OUT15

VOUTn

VOUT_FIX

Figure 6. Test Circuit for OUTn

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

TIMING DIAGRAMS

T_WH0, T_WH1, T_WL0

VCC

GND

INPUT⁽¹⁾50%

T_WH

T_WL

T_SU0, T_SU1, T_SU2, T_SU3, T_H0, T_H1

VCC

CLOCK

50%

INPUT⁽¹⁾

GND

VCC

T_SU

T_H

DATA/CONTROL

50%

INPUT⁽¹⁾

GND

(1) Input pulse rise and fall time is 1 ns to 3 ns.

Figure 7. Input Timing

t_R0, t_R1, t_F0, t_F1, t_D0, t_D1, t_D2, t_D3, t_D4, t_D5

:

VCC

INPUT⁽¹⁾

50%

GND

t_D

V_OHor V_OUTn

H

90%

50%

10%

OUTPUT⁽²⁾

V_OLor V_OUTn

L

t_Ror t_F

(1) Input pulse rise and fall time is 1 ns to 3 ns.

(2) Input pulse high level is VCC and low level is GND.

Figure 8. Output Timing

10

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

GS0

0A

GS15 GS15 GS15

11B

10B 9B

GS15 GS15

8B

7B

GS0

3B

GS0

2B

GS0

1B

GS0

0B

GS15

11C

GS15 GS15

9C

GS15 GS15 GS15

8C 7C 6C

GS15

5C

GSSIN

10C

T_H0

T_SU0

T_WH0

T_GSSCLK

T_SU2

GSSCLK

1

2

3

4

5

189 190 191 192

T_H1T_WH1T_SU3

T_WL0

T_SU1

XGSLAT

BLANK

T_WH1

Shift Register Data are Transferred

to Data Latch

T_SU1

Latched Data

for Grayscale

(Internal)

Previous Data

Latest Data

t_D0

t_D1

GS15

11A

GS15 GS15 GS15 GS15

10A 9A 8A

7A

GS15

6A

GS0

3A

GS0

2A

GS0

1A

GS0

0A

GS15

11B

LOD

15

LOD

14

LOD

13

LOD

12

LOD

11

LOD

10

LOD

9

GSSOUT

t_R0/t_F0

SID Load Timing to

GS Data Shift Register

Turning off outputs with the BLANK signal (all GS data are greater than 006h):

(V_OUTnH)

OFF

OUT

(V_OUTnL)

0, 4, 8, 12 ON

t_D2

t_F1

OFF

OUT

1, 5, 9, 13

ON

t_D3

OFF

OUT

2, 6, 10, 14 ON

t_D4

OFF

OUT

3, 7, 11, 15

ON

t_D5

t_R1

Turning off outputs with GSCLK (all GS data are set to 001h):

OFF

OUT

0, 4, 8, 12 ON

t_D2

t_OUTON

OFF

OUT

1, 5, 9, 13

ON

t_D3

t_OUTON

OFF

OUT

2, 6, 10, 14 ON

t_D4

OFF

OUT

3, 7, 11, 15

ON

t_D5

t_{ON_ERR}= t_OUTON- T_GSSCLK

Figure 9. Grayscale Data Write Timing

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

DC0

0A

DC15 DC15

6B 5B

DC15 DC15 DC15

4B 2B

3B

DC0

3B

DC0

2B

DC0

1B

DC0

0B

DC15

6C

DC15 DC15

5C 4C

DC15 DC15 DC15

3C 2C 1C

DC15

0C

DCSIN

T_H0

T_SU0

T_WH0

T_SU2

DCSCLK

1

2

3

4

5

109 110 111 112

T_H1T_WH1

T_WL0

XDCLAT

Latched Data

for Dot Correction

(Internal)

Previous Data

Latest Data

t_D0

DC15

6A

DC15 DC15

5A

4A

DC15 DC15

3A

2A

DC15 DC0

3A

DC0

2A

DC0

1A

DC0

0A

DC15

6B

DC15 DC15

5B

4B

DC15 DC15

3B

2B

DC15 DC15

1B

0B

DC14

6B

DCSOUT

1A

t_R0/t_F0

Figure 10. Dot Correction Data Write Timing

The SCLK falling edge must be prior to the XGSLAT rising edge in case SID is read.

GS0

1

GS0

0

GS15 GS15

11A

10A

GS15 GS15

9A 8A

GS15

7A

GS14

9A

GS14 GS14 GS14

7A

8A 6A

GS14 GS14

5A

4A

GS14

3A

GS0

1A

GS0

0A

GSSIN

GSSCLK

XGSLAT

GSSOUT

191 192

1

2

3

4

5

13

14

15

16

17

18

19

20 190 191 192

T_SU2

T_H1T_WH1T_SU3

t_D0

GS15

11

LOD

15

LOD

14

LOD

13

LOD

12

LOD

3

LOD

2

LOD

1

LOD

0

GS14 GS14

5

GS0

1

GS0

0

GS15

11A

TEF

6

SID

16

SID

15

SID

14

SID

13

SID

4

SID

3

SID

2

SID

1

SID

0

SID are entered in the GS shift register at the first rising edge of GSSCLK after XGSLAT goes low.

The SID readout consists of the saved LOD result at the 33rd GSSCLK rising edge in the previous display period

and the TEF data at the rising edge of the first GSCLK after XGSLAT goes low.

Figure 11. Status Information Data Read Timing

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

TYPICAL CHARACTERISTICS

At VCC = 3.3 V and T_A= +25°C, unless otherwise noted.

REFERENCE RESISTOR vs

OUTPUT CURRENT

POWER DISSIPATION RATE

vs FREE-AIR TEMPERATURE

10000

4000

3000

2000

1000

0

9840

TLC5942PWP

PowerPAD Soldered

TLC5942RHB

4920

3280

TLC5942PWP

PowerPAD Not Soldered

2460

1968

1640

1406

1093

1230

40

984

50

1000

0

10

20

30

-40

-20

0

20

40

60

80

100

Output Current (mA)

Free-Air Temperature (°C)

Figure 12.

Figure 13.

OUTPUT CURRENT vs

OUTPUT VOLTAGE

OUTPUT CURRENT vs

OUTPUT VOLTAGE

60

55

54

53

52

51

50

49

48

47

46

45

I_O= 50 mA

DCn = 7Fh

T_A= +25°C

DCn = 7Fh

I_O= 50 mA

I_O= 40 mA

50

40

30

20

10

0

T_A= +85°C

I_O= 30 mA

I_O= 20 mA

I_O= 10 mA

T_A= -40°C

T_A= +25°C

I_O= 5 mA

2.5

0

0.5

1.0

1.5

2.0

3.0

0

0.5

1.0

1.5

2.0

2.5

3.0

Output Voltage (V)

Figure 14.

Figure 15.

ΔI_OLCvs

AMBIENT TEMPERATURE

ΔI_OLCvs

OUTPUT CURRENT

5

4

5

4

I_O= 50 mA

DCn = 7Fh

T_A= +25°C

DCn = 7Fh

3

2

1

0

-1

-2

-3

-4

-5

-1

-2

-3

-4

-5

VCC = 3.3 V

VCC = 5 V

VCC = 3.3 V

VCC = 5 V

40

-40

-20

0

20

40

60

80

100

0

10

20

30

50

Ambient Temperature (°C)

Output Current (mA)

Figure 16.

Figure 17.

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TYPICAL CHARACTERISTICS (continued)

At VCC = 3.3 V and T_A= +25°C, unless otherwise noted.

DOT CORRECTION LINEARITY

60

50

40

30

20

10

0

T_A= +25°C

I_OLCMax= 50 mA

50

I_OLCMax= 50 mA

40

30

20

I_OLCMax= 30 mA

T_A= -40°C

T_A= +25°C

T_A= +85°C

10

I_OLCMax= 5 mA

0

20

40

60

80

100

120

140

0

20

40

60

80

100

120

140

Dot Correction Data (dec)

Figure 18.

Figure 19.

CONSTANT CURRENT OUTPUT VOLTAGE WAVEFORM

CH1-GSCLK

(30 MHz)

CH1 (2 V/div)

CH2-OUT0

(GSData = 0x001h)

CH2 (2 V/div)

CH3 (2 V/div)

CH3-OUT15

(GSData = 0x001h)

I_OLCMax= 50 mA, DCn = 7Fh

T_A= +25°C,R_L= 82 W

C_L= 15 pF, VLED = 5 V

Time (25 ns/div)

Figure 20.

14

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DETAILED DESCRIPTION

Setting for the Maximum Constant Sink Current Value

On the TLC5942, the maximum constant current sink value for each channel, I_OLCMax, is determined by an

external resistor, R_IREF, placed between the IREF and GND pins. The R_IREFresistor value is calculated with

Equation 1:

V_IREF(V)

´ 41

R_IREF(kW) =

I_OLCMax(mA)

(1)

Where:

V_IREF= the internal reference voltage on the IREF pin (typically 1.20 V)

I_OLCMaxis the largest current for all outputs. Each output sinks the I_OLCMaxcurrent when it is turned on and its dot

correction is set to the maximum value of 7Fh (127d). The sink current for each output can be reduced by

lowering the respective output dot correction value.

R_IREFmust be between 984 Ω (typ) and 9.84 kΩ (typ) in order to keep I_OLCMaxbetween 5 mA and 50 mA. The

output may become unstable when I_OLCMaxis set lower than 5 mA. However, output currents lower than 5 mA

can be achieved by setting I_OLCMaxto 5 mA or higher, and then using dot correction to lower the output current.

Figure 12 in the Typical Characteristics and Table 1 show the characteristics of the constant sink current versus

external resistor, R_IREF

.

Table 1. Maximum Constant Current Output versus

External Resistor Value

I_OLCMax(mA, typical)

R_IREF(Ω)

984

50

45

40

35

30

25

20

15

10

5

1093

1230

1406

1640

1968

2460

3280

4920

9840

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Dot Correction (DC) Function

The TLC5942 is able to individually adjust the output current of each channel (OUT0 to OUT15). This function is

called dot correction (DC). The DC function allows users to individually adjust the brightness and color deviations

of LEDs connected to the outputs OUT0 to OUT15. Each respective channel output current can be adjusted in

128 steps from 0% to 100% of the maximum output current, I_OLCMax. The dot correction data are entered into the

TLC5942 via the serial interface.

Equation 2 determines the sink current for each output (OUTn):

DCn

127d

I_OUTn(mA) = I_OLCMax(mA) ´ (

)

(2)

Where:

I_OLCMax= the maximum channel current for each channel determined by R_IREF

DCn = the programmed dot correction value for OUTn (DCn = 0 to 127d)

When the IC is powered on, the data in the Dot Correction Shift Register and data latch are not set to any default

values. Therefore, DC data must be written to the DC latch before turning on the constant current output.

Table 2 summarizes the DC data versus current ratio and set current value.

Table 2. DC Data versus Current Ratio and Set Current Value

SET CURRENT

RATIO TO

MAX CURRENT (%)

OUTPUT CURRENT

(mA, typical)

AT I_OLCMax= 50 mA

OUTPUT CURRENT

(mA, typical)

AT I_OLCMax= 5 mA

DC DATA

(Binary)

DC DATA

(Decimal)

DC DATA

(Hex)

000 0000

000 0001

000 0010

... ...

0

1

00

01

0.0

0.8

0.0

0.4

0.00

0.04

0.08

... ...

4.92

4.96

5.00

2

02

1.6

0.8

... ...

125

126

127

... ...

7D

7E

7F

... ...

98.4

99.2

100.0

... ...

49.2

49.6

50.0

111 1101

111 1110

111 1111

16

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SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

Grayscale (GS) Function (PWM Operation)

The pulse width modulation (PWM) operation is controlled by a 12-bit grayscale counter that is clocked on each

rising edge of the grayscale reference clock, GSSCLK. The counter is reset to zero when the BLANK signal is

set high. The counter value is held at zero while BLANK is high, even if the GSSCLK input toggles high and low.

After the falling edge of BLANK, the counter increments with each rising edge of GSSCLK. Any constant current

sink output (OUT0 through OUT15) with a nonzero value in its corresponding grayscale latch starts to sink

current after the first rising edge of GSSCLK following a high-to-low transition of BLANK. The internal counter

keeps track of the number of GSSCLK pulses. Each output channel stays on as long as the internal counter is

equal to or less than the respective output GSSCLK. Each channel turns off at the rising edge of GSSCLK when

the grayscale counter value is larger than the grayscale latch value.

For example, an output that has a grayscale latch value of '1' turns on at the first rising edge of GSSCLK after

BLANK goes low. It turns off at the second rising edge of GSSCLK. Figure 21 shows the PWM timing diagram.

BLANK

2049

2048 2050

4095

4094 4096

1

2

3

4

¼

GSSCLK

OFF

GSSCLK counter starts to count GSSCLK

after BLANK goes low.

(V_OUTnH)

OUTn

Drivers do not turn on when grayscale data are zero.

ON

(GSDATA = 0d)

T = GSSCLK ´ 1

(V_OUTnH)

OFF

OUTn

ON

(V_OUTnL)

(V_OUTnH)

(GSDATA = 1d)

T = GSSCLK ´ 2

T = GSSCLK ´ 3

OFF

OUTn

ON

(V_OUTnL)

(V_OUTnH)

(V_OUTnL)

(GSDATA = 2d)

OFF

OUTn

ON

(GSDATA = 3d)

(V_OUTnH)

T = GSSCLK ´ 2047

T = GSSCLK ´ 2048

T = GSSCLK ´ 2049

OFF

OUTn

ON

(V_OUTnL)

(V_OUTnH)

(GSDATA = 2047d)

OFF

OUTn

ON

(V_OUTnL)

(V_OUTnH)

(GSDATA = 2048d)

OFF

OUTn

ON

(V_OUTnL)

(GSDATA = 2049d)

(V_OUTnH)

T = GSSCLK ´ 4093

T = GSSCLK ´ 4094

OFF

OUTn

ON

(V_OUTnL)

(V_OUTnH)

(GSDATA = 4093d)

OFF

OUTn

ON

(V_OUTnL)

(V_OUTnH)

(V_OUTnL)

(GSDATA = 4094d)

T = GSSCLK ´ 4095

OFF

OUTn

ON

(GSDATA = 4095d)

OUTn does not turn on again until

BLANK goes high to reset the grayscale clock

and then goes low to enable all OUTn.

OUTn turns on at first rising edge of GSSCLK

after BLANK goes low except when grayscale data are zero.

Figure 21. PWM Operation Timing

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When the IC is powered on, the data in the Grayscale Shift Register and latch are not set to any default value.

Therefore, Grayscale data must be written to the Grayscale latch before turning the constant current output on.

Additionally, BLANK should be high when the device turns on, to prevent the outputs from turning on before the

proper grayscale and dot correction values can be written. All constant current outputs are always off when

BLANK is high. Equation 3 determines each output (OUTn) on time (t_OUTON):

t_OUTON(ns) = T_GSSCLK(ns) ´ GSn

(3)

Where:

T_GSSCLK= the period of GSSCLK

GSn = the programmed grayscale value for OUTn (GSn = 0 to 4095d)

If there are any unconnected output LED lamps (including connection failures or short-circuits), the grayscale

data corresponding to the unconnected output should be set to '0' before turning on the LEDs. Otherwise, the

supply current (I_VCC) increases while the LEDs are on. If GS data changes during a GS period because XLAT

goes high, and latches new GS data, the internal data latch registers are immediately updated. This action can

cause the outputs to turn on or off unexpectedly. For proper operation, GS data should only be latched into the

IC at the end of a GS period when BLANK is high. Table 3 summarizes the GS data versus OUTn on duty and

on time.

Table 3. GS Data versus OUTn On Duty and OUTn On Time

GS DATA

(Binary)

GS DATA

(Decimal)

GS DATA

(Hex)

OUTn

ON DUTY (%)

OUTn ON TIME (ns, typical)

AT 30 MHz GSSCLK

0000 0000 0000

0000 0000 0001

0000 0000 0010

0000 0000 0011

... ...

0

000

001

002

003

... ...

7FF

800

801

... ...

FFD

FFE

FFF

0.00

0.02

0

1

33

2

0.05

67

3

0.07

100

... ...

2047

2048

2049

... ...

4093

4094

4095

... ...

0111 1111 1111

1000 0000 0000

1000 0000 0001

... ...

49.99

50.01

50.04

... ...

68263

68267

68300

... ...

1111 1111 1101

1111 1111 1110

1111 1111 1111

99.95

99.98

100.00

136433

135467

136500

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Grayscale Shift Register and Data Latch

The Grayscale (GS) Shift Registers and data latches are each 192 bits in length, and are used to set the PWM

timing for each constant current driver. See Table 3 for the ON time duty of each GS data bit. Figure 22 shows

the shift register and latch configuration. Refer to Figure 9 for the timing diagram for writing data into the GS shift

register and latch. The driver on time is set by the data in the GS data latch. GS data present on the GSSIN pin

are clocked into the GS Shift Register with each rising edge of the GSSCLK pin. Data are shifted in MSB first.

Data are latched from the shift register into the GS data latch with a rising edge on the XGSLAT pin.

When the IC is powered on, the data in Grayscale Shift Register and data latch are not set to any default value.

Therefore, grayscale data must be written to the GS latch before turning on the constant current output. Also,

BLANK should be high when powered on because the constant current may also turn on. All constant current

outputs are off when BLANK is high.

The Status Information Data (SID) byte is overwritten on the most significant 17 bits of the Grayscale Shift

Register at the rising edge of the first GSSCLK after XGSLAT goes low.

Grayscale Shift Register (12 Bits ´ 16 Channels)

GS Data for OUT15

MSB

191

GS Data for OUT14

¼

GS Data for OUT1

GS Data for OUT0

LSB

0

180

179

175

7

6

GSSIN

OUT15-Bit11

(LOD-OUT15)

OUT15-Bit0 OUT14-Bit11

(LOD-OUT4) (LOD-OUT3)

OUT14-Bit7

(TEF)

¼

OUT1-Bit0

OUT0-Bit11

OUT0-Bit0

GSSOUT

GSSCLK

SID Data are Overwritten Between Bits 191 and 175

¼

GS Data for OUT15

GS Data for OUT14

¼

GS Data for OUT1

GS Data for OUT0

MSB

191

LSB

0

180

179

12

11

¼

OUT15-Bit11

OUT15-Bit0 OUT14-Bit11

OUT14-Bit7

OUT1-Bit0

OUT0-Bit11

OUT0-Bit0

XGSLAT

Grayscale Data Latch (12 Bits ´ 16 Channels)

192 Bits

To PWM Timing Control Block

Figure 22. Grayscale Shift Register and Data Latch Configuration

Dot Correction Shift Register and Data Latch

The Dot Correction (DC) Shift Registers and latches are each 112 bits in length and are used to individually

adjust the constant current values for each constant current driver. Each channel can be adjusted from 0% to

100% of the maximum LED current with 7-bit resolution. Table 2 describes the percentage of the maximum

current for each dot correction data. See Figure 23 for the Dot Correction Shift Register and data latch

configuration. Figure 10 illustrates the timing chart for writing data into the DC Shift Registers and latches. Each

channel LED current is dot-corrected by the percentage corresponding to the data in its DC data latch. DC data

present on the DCSIN pin are clocked into the DC Shift Register with each rising edge of the DCSCLK pin. Data

are shifted in MSB first. The data are latched from the shift register into the DC data latch with a rising edge on

the XDCLAT pin.

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Dot Correction Shift Register (7 Bits ´ 16 Channels)

DC Data for OUT15

MSB

DC Data for OUT14

¼

DC Data for OUT1

DC Data for OUT0

LSB

0

111

105

104

7

6

DCSIN

DCSCLK

¼

OUT15-Bit6

OUT15-Bit0 OUT14-Bit6

OUT1-Bit0

OUT0-Bit6

OUT0-Bit0

DCSOUT

¼

DC Data for OUT15

MSB

DC Data for OUT14

¼

DC Data for OUT1

DC Data for OUT0

LSB

0

111

105

104

7

6

¼

OUT15-Bit6

OUT15-Bit0 OUT14-Bit6

OUT1-Bit0

OUT0-Bit6

OUT0-Bit0

XDCLAT

Dot Correction Data Latch (7 Bits ´ 16 Channels)

112 Bits

To Constant Current Driver Block

Figure 23. Dot Correction Shift Register and Latch Configuration

When the IC is powered on, the data in the Dot Correction Shift Register and data latch are not set to a specific

default value. Therefore, dot correction data must be written to the DC latch before turning on the constant

current output.

Status Information Data (SID)

Status information data (SID) are 17-bit, read-only data. Both the LED open detection (LOD) error and the

thermal error flag (TEF) are shifted out of the GSSOUT pin with each rising edge of the grayscale clock,

GSSCLK. The 16 LOD bits for each channel and the TEF bit are written into the 17 most significant bits of the

Grayscale Shift Register at the rising edge of the first GSSCLK after XGSLAT goes low. As a result, the previous

data in the 17 most significant bits are lost at the same time. No data are loaded into the other 175 bits.

Figure 24 shows the bit assignments. Figure 11 illustrates the read timing for the status information data.

Status Information Data (SID) Configuration

LOD Data of OUT15 to OUT0 (16 Bits)

TEF (1 Bit)

MSB

16

LSB

0

¼

15

2

1

OUT15

LOD Data

OUT14

LOD Data

OUT1

LOD Data

OUT0

LOD Data

¼

TEF Data

The 16 LOD bits for each channel and the TEF bit overwrite

the most significant 17 bits of the grayscale shift register at the

rising edge of the first GSSCLK after XGSLAT goes low.

¼

GS Data for OUT15

MSB

GS Data for OUT14

179

¼

GS Data for OUT1

GS Data for OUT0

LSB

0

191

180

175

12

11

GSSIN

OUT15-Bit11

(LOD-OUT15)

OUT15-Bit0 OUT14-Bit11

(LOD-OUT4) (LOD-OUT3)

OUT14-Bit7

(TEF)

¼

OUT1-Bit0 OUT0-Bit11

OUT0-Bit0

GSSOUT

GSSCLK

Grayscale Shift Register (12 Bits ´ 16 Channels)

Figure 24. Status Information Data Configuration

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The LOD data are updated at the rising edge of the 33rd GSSCLK pulse after BLANK goes low; the LOD data

are retained until the next 33rd GSSCLK. LOD data are only checked for outputs that are turned on during the

rising edge of the 33rd GSSCLK pulse. A '1' in an LOD bit indicates an open LED condition for the corresponding

channel. A '0' indicates normal operation. It is possible for LOD data to show a '0' even if the LED is open when

the grayscale data are less than 20h (32d). Therefore, the GS data must be set to 21h (33d) or higher to get

updated LOD data beyond 20h (32d).

The TEF bit indicates that the IC temperature is too high. The flag also indicates that the IC has turned off all

drivers to avoid damage by overheating the device. A '1' in the TEF bit means that the IC temperature has

exceeded the detect temperature threshold (T_TEF) and the driver is turned off. A '0' in the TEF bit indicates

normal operating temperature conditions. The IC automatically turns the drivers back on when the IC

temperature decreases to less than T_TEF-THYS. When the IC is powered on, LOD data do not show correct values.

Therefore, LOD data must be read from the 33rd GSSCLK pulse input after BLANK goes low. Table 4 shows a

truth table for both LOD and TEF.

Table 4. LOD and TEF Truth Table

CONDITION

SID DATA

LED OPEN DETECTION (LODn)

LED is connected (V_OUTn> V_IOD

LED is open or shorted to GND (V_OUTn≤ V_IOD

THERMAL ERROR FLAG (TEF)

0

1

)

Device temperature is low (temp ≤ T_TEF–THYS)

)

Device temperature is high (temp > T_TEF)

Continuous Base LED Open Detection

The LED Open Detection (LOD) circuit checks the voltage of each active (that is, on) constant current sink output

(OUT0 through OUT15) at the rising edge of the 33rd GSSCLK after the falling edge of BLANK to detect open

and short LEDs to GND. The channels corresponding to the LOD bit in the Status Information Data register (SID)

are set to a '1' if the voltage of the OUTn pin is less than the LED open detection threshold (V_LOD= 0.3 V_TYP).

This status information can be read from the GSSOUT pin. No special test sequence is required for LED open

detection.

The LOD function automatically checks for open and short LEDs to GND during each grayscale PWM cycle. The

SID information of the LOD is latched into the LED Open Detection data latch and does not change until the

rising edge of the 33rd GSSCLK pulse following the next falling edge of BLANK. To eliminate false detection of

open LEDs, the LED driver design must ensure that the TLC5942 output voltage is greater than V_LODwhen the

outputs are on. The GS data must be 21h (33d) or more to get the LOD result.

BLANK

4086 4088 4090 4093 4094 4096

4085 4087 4089 4091 4093 4095

¼

3

1

2

4

28 29 30 31 32 33 34 35 36 37 38 39

GSSCLK

OUTn

If the OUTn voltage (V_OUT) is less than VLOD (0.3 V, typ) at the rising edge of the 33rd

GSSCLK after the falling edge of BLANK, the LOD sets the SID bit corresponding

to the output channel in which LED is open or shorted to GND equal to ‘1’.

OUTn OFF

OUTn ON

GND

V_OUTn

This LED Open Detection (LOD) data are

kept until the next 33rd rising edge of

GSSCLK after BLANK goes low.

Internal SID

Old LED Open Detection Data

New LED Open Detection Data

Register Value

Figure 25. LED Open Detection (LOD) Timing

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Thermal Shutdown and Thermal Error Flag

The Thermal Shutdown (TSD) function turns off all of the constant current outputs on the IC when the junction

temperature (T_J) exceeds the threshold (T_TEF= +162°C, typ) and sets the thermal error flag (TEF) to '1'. All

outputs are latched off when TEF is set to '1' and remain off until the next grayscale cycle after the junction

temperature drops below (T_(TEF)– T_(HYS)). TEF is set to '0' once the junction temperature drops below (T_(TEF)

T_(HYS)), but the outputs do not turn on until the first GSSCLK after BLANK goes low while TEF is set to '0'.

–

BLANK

4094 4096

1

2

3

4

4093 4095

1

2

3

GSSCLK

IC Junction

T

< T

(TEF)

(Normal Temperature)

T

³ T

(TEF)

T

< T

(TEF)

- T

(HYS)

(Normal Temperature)

T ³ T

J (TEF)

J

Temperature (T_J)

(High Temp)

'1'

(High Temp)

'1'

TEF

'0'

(Internal)

OFF

ON

OUTn

If T_J³ T_(TEF)at this time,

then OUTn is not turned on.

Figure 26. TEF/TSD Timing

Noise Reduction

Large surge currents may flow through the IC and the board on which the device is mounted if all 16 LED

channels turn on simultaneously at the start of each grayscale cycle. These large current surges could introduce

detrimental noise and electromagnetic interference (EMI) into other circuits. The TLC5942 turns on the LED

channels in a series delay, to provide a current soft-start feature. The output current sinks are grouped into four

groups of four channels each. The first group is OUT0, 4, 8, 12; the second group is OUT1, 5, 9, 13; the third

group is OUT2, 6, 10, 14; and the fourth group is OUT3, 7, 11, 15. Each group turns on sequentially with a small

delay between groups; see Figure 9. Both turn-on and turn-off are delayed.

POWER DISSIPATION CALCULATION

The device power dissipation must be below the power dissipation rate of the device package illustrated in

Figure 13 to ensure correct operation. Equation 4 calculates the power dissipation of the device:

DCn

P_D= (V_CC´ I_CC) + V_OUT´ I_MAX´ N ´

´ d_PWM

127d

(4)

Where:

V_CC= device supply voltage

I_CC= device supply current

V_OUT= OUTn voltage when driving LED current

I_MAX= LED current adjusted by R_(IREF)resistor

DCn = maximum dot correction value for OUTn (decimal)

N = number of OUTn driving LED at the same time

d_PWM= duty ratio defined by BLANK pin or GS PWM value

22

Submit Documentation Feedback

Product Folder Link(s): TLC5942

TLC5942

www.ti.com

SBVS096B–OCTOBER 2007–REVISED OCTOBER 2007

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (October 2007) to Revision B ............................................................................................... Page

•

Changed Figure 11. ............................................................................................................................................................. 12

Changes from Original (October 2007) to Revision A .................................................................................................... Page

Changed release date for QFN package............................................................................................................................... 2

•

Submit Documentation Feedback

23

Product Folder Link(s): TLC5942

PACKAGE OPTION ADDENDUM

www.ti.com

1-Nov-2007

PACKAGING INFORMATION

Orderable Device

TLC5942PWP

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTSSOP

PWP

28

32

50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

TLC5942PWPR

TLC5942RHBR

TLC5942RHBT

HTSSOP

QFN

PWP

RHB

2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

QFN

250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Oct-2007

TAPE AND REEL BOX INFORMATION

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

(mm)

16

TLC5942PWPR

TLC5942RHBR

TLC5942RHBT

PWP

RHB

28

32

SITE 60

SITE 41

6.9

5.3

10.2

5.3

1.8

1.5

12

8

16

12

Q1

Q2

330

12

180

12

5.3

8

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Oct-2007

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

TLC5942PWPR

TLC5942RHBR

TLC5942RHBT

PWP

RHB

28

32

SITE 60

SITE 41

346.0

190.0

346.0

212.7

33.0

29.0

31.75

Pack Materials-Page 2

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TLC5942PWP
厂家：	TEXAS INSTRUMENTS
描述：	16-Channel, 12-Bit PWM LED Driver with 7-Bit Dot Correction 16通道， 12位PWM LED驱动器， 7位点校正显示驱动器驱动程序和接口接口集成电路光电二极管 PC
文件：	总33页 (文件大小：1086K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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