TLC5943RHBT [TI]
16-Channel, 16-Bit PWM LED Driver with 7-Bit Global Brightness Control; 16通道, 16位PWM LED驱动器, 7位全局亮度控制型号: | TLC5943RHBT |
厂家: | TEXAS INSTRUMENTS |
描述: | 16-Channel, 16-Bit PWM LED Driver with 7-Bit Global Brightness Control |
文件: | 总34页 (文件大小:758K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLC5943
www.ti.com
SBVS101–DECEMBER 2007
16-Channel, 16-Bit PWM LED Driver with
7-Bit Global Brightness Control
1
FEATURES
•
Readable Error Information:
23
•
16 Channels, Constant Current Sink Output
–
–
LED Open Detection (LOD)
Thermal Error Flag (TEF)
•
•
50-mA Capability (Constant Current Sink)
16-Bit (65,536 Steps) Grayscale Control with
Enhanced Spectrum (ES) PWM
•
•
Noise Reduction:
–
4-channel grouped delay to prevent inrush
current
•
7-Bit (128 Steps) Global Brightness Control for
All Channels with Sink Current
Operating Temperature: –40°C to +85°C
•
•
•
LED Power-Supply Voltage up to 17 V
VCC = 3.0 V to 5.5 V
APPLICATIONS
•
Monochrome, Multicolor, Full-Color LED
Displays
Constant Current Accuracy:
–
–
Channel-to-Channel = ±1.5%
Device-to-Device = ±3%
•
•
LED Signboards
Display Backlighting
•
•
•
•
•
•
CMOS Level I/O
30-MHz Data Transfer Rate
33-MHz Grayscale Control Clock
Auto Display Repeat
DESCRIPTION
The TLC5943 is a 16-channel, constant current sink
driver. Each channel is individually adjustable with
65,536 enhanced spectrum pulse-width modulated
(PWM) steps controlled by grayscale (GS) data. All
output drivers are adjustable with 128 constant sink
current steps at same value controlled by brightness
control (BC) data. Both GS data and BC data are
writable via a serial interface port. The maximum
current value of all 16 channels can be set by a
single external resistor.
Auto Data Refresh
Continuous Base LED Open Detection (LOD):
–
Detect LED opening and LED short to GND
during display
•
Thermal Shutdown (TSD):
–
Automatic shutdown at high temperature
conditions
–
Restart under normal temperature
VLED
VLED
VLED
VLED
¼
¼
¼
¼
¼
¼
¼
¼
OUT0
OUT15
SOUT
XERR
OUT0
SIN
OUT15
SOUT
XERR
DATA
SIN
SCLK
SCLK
SCLK
BCSEL
BCSEL
BCSEL
XLAT
XLAT
VCC VCC
VCC
XLAT
BLANK
BLANK
BLANK
GSCLK
IREF
VCC
VCC
Controller
GSCLK
GSCLK
FLAGS
XTEST
XTEST
IREF
READ
TLC5943
TLC5943
XERR
READ
RIREF
RIREF
GND
GND
IC1
ICn
5
XTEST pin must be connected to VCC or GND.
Typical Application Circuit (Multiple Daisy-Chained TLC5943s)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TLC5943
www.ti.com
SBVS101–DECEMBER 2007
DESCRIPTION, CONTINUED
The TLC5943 has two error detection circuits for LED open detection (LOD) and a thermal error flag (TEF). LOD
detects a broken or disconnected LED and shorted LED to GND during the display period. TEF indicates an
over-temperature condition; when a TEF is set, all output drivers are turned off. When the TEF is cleared, all
output drivers are restarted.
blank
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION(1)
TRANSPORT MEDIA,
PRODUCT
PACKAGE-LEAD
ORDERING NUMBER
TLC5943PWPR
TLC5943PWP
QUANTITY
Tape and Reel, 2000
Tube, 50
TLC5943
HTSSOP-28 PowerPAD™
TLC5943RHBR
TLC5943RHBT
Tape and Reel, 3000
Tape and Reel, 250
TLC5943
5 mm × 5 mm QFN-32
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS(1)(2)
Over operating free-air temperature range, unless otherwise noted.
PARAMETER
TLC5943
–0.3 to +6.0
60
UNIT
V
VCC
IOUT
Supply voltage, VCC
Output current (dc): OUT0 to OUT15
mA
Input voltage range:
SIN, SCLK, XLAT, BLANK, GSCLK, BCSEL, IREF
VIN
–0.3 to VCC + 0.3
V
SOUT, XERR
Output voltage range
–0.3 to VCC + 0.3
V
V
VOUT
OUT0 to OUT15
–0.3 to +18
+150
TJ(max)
TSTG
Maximum operating junction temperature
Storage temperature range
°C
°C
kV
V
–55 to +150
2
Human body model (HBM)
Charged device model (CDM)
ESD rating
500
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) All voltage values are with respect to network ground terminal.
2
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TLC5943
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SBVS101–DECEMBER 2007
RECOMMENDED OPERATING CONDITIONS
At TA= –40°C to +85°C, unless otherwise noted.
TLC5943
NOM
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC
VO
Supply voltage
3.0
5.5
V
V
Voltage applied to output
High-level input voltage
Low-level input voltage
High-level output current
OUT0 to OUT15
17
VIH
VIL
0.7 × VCC
VCC
V
GND
0.3 × VCC
V
IOH
SOUT
SOUT
–1
1
mA
mA
mA
mA
°C
IOL
Low-level output current
XERR
5
IOLC
TA
Constant output sink current
Operating free-air temperature
OUT0 to OUT15
50
+85
–40
–40
Operating junction
temperature
TJ
+125
°C
AC Characteristics: VCC = 3 V to 5.5 V
fCLK (sclk)
Data shift clock frequency
SCLK
30
33
MHz
MHz
Grayscale control clock
frequency
fCLK (gsclk)
GSCLK
TWH0 / TWL0
TWH1
TSU0
TSU1
TSU2
TSU3
TSU4
TSU5
TSU6
TH0
SCLK, GSCLK
XLAT, BLANK
SIN–SCLK↑
10
30
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pulse duration
Setup time
XLAT↑–SCLK↑
BLANK↓–GSCLK↑
BCSEL–SCLK↑
BCSEL–XLAT↑
XLAT↓–SCLK↑
XLAT↑–BLANK↓
SIN–SCLK↑
100
10
10
30
15
20
3
TH1
XLAT↑–SCLK↑
BCSEL–SCLK↓
BCSEL–XLAT↑
30
10
100
Hold time
TH2
TH3
DISSIPATION RATINGS
OPERATING FACTOR
TA < +25°C
TA = +70°C
TA = +85°C
PACKAGE
ABOVE TA = +25°C
POWER RATING
POWER RATING
POWER RATING
HTSSOP-28 with
31.67 mW/°C
3958 mW
2533 mW
2058 mW
PowerPAD soldered(1)
HTSSOP-28 with
16.21 mW/°C
27.86 mW/°C
2026 mW
3482 mW
1296 mW
2228 mW
1053 mW
1811 mW
PowerPAD not soldered(2)
QFN-32(3)
(1) With PowerPAD soldered onto copper area on printed circuit board (PCB); 2 oz. copper. For more information, see SLMA002 (available
for download at www.ti.com).
(2) With PowerPAD not soldered onto copper area on PCB.
(3) The package thermal impedance is calculated in accordance with JESD51-5.
Copyright © 2007, Texas Instruments Incorporated
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SBVS101–DECEMBER 2007
ELECTRICAL CHARACTERISTICS
At VCC = 3.0 V to 5.5 V, and TA = –40°C to +85°C. Typical values at VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5943
PARAMETER
TEST CONDITIONS
IOH = –1 mA at SOUT
MIN
VCC – 0.4
0
TYP
MAX
VCC
0.4
UNIT
VOH
VOL
High-level output voltage
V
V
V
IOL = 1 mA at SOUT
IOL = 5 mA at XERR
Low-level output voltage
Input current
0.4
VIN = VCC or GND at SIN, SCLK, GSCLK, XLAT,
BLANK, BCSEL
IIN
–1
1
3
8
µA
mA
mA
SIN/SCLK/GSCLK/XLAT/BCSEL = low, BLANK = high,
GSn = FFFFh, BCn = 7Fh, VOUTn = 1 V, RIREF = 10 kΩ
ICC1
ICC2
1
4
SIN/SCLK/GSCLK/XLAT/BCSEL = low, BLANK = high,
GSn = FFFFh, BCn = 7Fh, VOUTn = 1 V, RIREF = 2 kΩ
SCLK/GSCLK = 30 MHz, SIN = 15MHz,
XLAT/BCSEL/BLANK = low,
Supply current (VCC
)
ICC3
14
30
mA
GSn = FFFFh, BCn = 7Fh, Auto Repeat on,
VOUTn = 1 V, RIREF = 2 kΩ(1)
SCLK/GSCLK = 30 MHz, SIN = 15MHz,
XLAT/BCSEL/BLANK = low,
ICC4
27
49
50
55
mA
mA
GSn = FFFFh, BCn = 7Fh, Auto Repeat on,
VOUTn = 1 V, RIREF = 1 kΩ(1)
All OUTn = ON, BCn = 7Fh, VOUTn = 1 V,
VOUTfix = 1 V, RIREF = 1 kΩ
IO(LC)
Constant output current
43
BLANK = high, RIREF = 1 kΩ, VOUTn = 17 V,
At OUT0 to OUT15
IO(LKG1)
IO(LKG2)
ΔIO(LC)
Leakage output current
Leakage output current
0.1
1
µA
µA
%
No error condition, VXERR = 5.5 V, at XERR
Constant current error
(pin-to-pin)(1)
All OUTn = ON, BCn = 7Fh, VOUTn = 1 V,
VOUTfix = 1 V, RIREF = 1 kΩ, at OUT0 to OUT15
±1.5
±3
±4
Constant current error
(device-to-device)(2)
All OUTn = ON, BCn = 7Fh, VOUTn = 1 V,
VOUTfix = 1 V, RIREF = 1 kΩ
ΔIO(LC1)
ΔIO(LC2)
ΔIO(LC3)
±9
±4
±3
%
All OUTn = ON, BCn = 7Fh, VOUTn = 1 V,
VOUTfix = 1 V, RIREF = 1 kΩ, at OUT0 to OUT15
Line regulation(3)
Load regulation(4)
±1
%/V
%/V
All OUTn = ON, DCn = 7Fh, VOUTn = 1 V to 3 V,
VOUTfix = 1 V, RIREF = 1 kΩ, at OUT0 to OUT15
±1
T(TEF)
T(HYS)
VLOD
Thermal error flag threshold
Thermal error hysteresis
LED open detection threshold
Reference voltage output
Junction temperature(5)
Junction temperature(5)
All OUTn = ON
+150
+5
+162
+10
0.3
+175
+20
0.4
°C
°C
V
0.2
VIREF
RIREF = 1 kΩ
1.16
1.20
1.24
V
(1) The deviation of each output from the average of OUT0–OUT15 constant current. Deviation is calculated by the formula:
IOUTn
D (%) =
- 1 ´ 100
(IOUT0 + IOUT1 + ... + IOUT15
)
16
.
(2) The deviation of the OUT0–OUT15 constant current average from the ideal constant current value.
Deviation is calculated by the following formula:
(IOUT0 + IOUT1 + ... IOUT14 + IOUT15
)
- (Ideal Output Current)
16
D (%) =
´ 100
Ideal Output Current
Ideal current is calculated by the formula:
1.20
IOUT(IDEAL) = 41 ´
RIREF
(3) Line regulation is calculated by this equation:
(IOUTn at VCC = 5.5 V) - (IOUTn at VCC = 3.0 V)
D (%/V) =
100
´
(IOUTn at VCC = 3.0 V)
5.5 V - 3 V
(4) Load regulation is calculated by the equation:
(IOUTn at VOUTn = 3 V) - (IOUTn at VOUTn = 1 V)
100
3 V - 1 V
D (%/V) =
´
(IOUTn at VOUTn = 1 V)
(5) Not tested. Specified by design.
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Copyright © 2007, Texas Instruments Incorporated
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TLC5943
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SBVS101–DECEMBER 2007
SWITCHING CHARACTERISTICS
At VCC = 3.0 V to 5.5 V, TA = –40°C to +85°C, CL = 15 pF, RL = 82 Ω, RIREF = 1 kΩ, and VLED = 5.0 V. Typical values at
VCC = 3.3 V and TA = +25°C, unless otherwise noted.
TLC5943
PARAMETER
Rise time
TEST CONDITIONS
MIN
TYP
MAX UNIT
tR0
tR1
tF0
tF1
tF2
tD0
tD1
tD2
tD3
tD4
tD5
SOUT
16
ns
30
OUTn, BC = 7Fh
10
SOUT
16
ns
30
Fall time
OUTn, BC = 7Fh
10
XERR, CL = 100 pF, RL = 1 kΩ, VXERR = 5 V
SCLK↑ to SOUT
100
25
ns
ns
ns
ns
ns
ns
ns
ns
BLANK↑ to OUT0 sink current off
GSCLK↑ to OUT0/4/8/12
GSCLK↑ to OUT1/5/9/13
GSCLK↑ to OUT2/6/10/14
GSCLK↑ to OUT3/7/11/15
GSn = 0001h, GSCLK = 33 MHz
20
18
42
66
90
40
5
20
40
Propagation delay time
73
35
106
140
10
50
tON_ERR Output on-time error(1)
–20
(1) Output on-time error is calculated by the following formula: TON_ERR (ns) = tOUTON – TGSCLK. tOUTON is the actual on-time of the constant
current driver. TGSCLK is the period of GSCLK.
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TLC5943
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SBVS101–DECEMBER 2007
FUNCTIONAL BLOCK DIAGRAM
VCC
16
LED Open Detection Data Latch
(16 LOD)
gsclk33
VCC
16
LSB
MSB
SIN
Grayscale Shift Register
(16 Bits x 16 Channels)
SOUT
0
255
SCLK
256
LSB
MSB
First Grayscale Data Latch
(16 Bits x 16 Channels)
0
255
256
LSB
MSB
Second Grayscale Data Latch
(16 Bits x 16 Channels)
BCSEL
0
255
LSB
MSB
Brightness Control (7 Bits) / Auto
Repeat Enable (1 Bit) Shift Register
0
LSB
7
MSB
8
XLAT
256
First Brightness Control (7 Bits) / Auto
Repeat Enable (1 Bit) Data Latch
xlatbuf
0
LSB
7
7
MSB
Second Brightness Control (7 Bits)
Data Latch
0
1
6
GS Counter/
Auto Repeat/
Refresh
GSCLK
BLANK
XERR
16-Bit ES PWM Timing Control
16
16
XERR
Control
7
Output Switching Delay
(4-Channel Unit)
blankbuf
16
Constant Current Driver with 7-Bit
(128 Steps) Global Current Control
Reference
Current
Control
IREF
16
XTEST
GND
LED Open Detection
(LOD, 16 Channels)
Thermal
Detection
GND
¼
OUT0
OUT1
OUT14 OUT15
6
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SBVS101–DECEMBER 2007
DEVICE INFORMATION
PWP PACKAGE
(Top View)
RHB PACKAGE
(Top View)
GND
BLANK
XLAT
1
2
3
4
5
6
7
8
9
28 VCC
27 IREF
26 XTEST
25 GSCLK
24 SOUT
23 XERR
22 OUT15
21 OUT14
20 OUT13
19 OUT12
18 OUT11
17 OUT10
16 OUT9
15 OUT8
SCLK
SIN
OUT10
15 OUT9
OUT8
14
XTEST
IREF
25
26
16
BCSEL
OUT0
OUT1
OUT2
VCC 27
28
29
30
13 NC
12 NC
11 OUT7
NC
NC
Thermal
Pad
Thermal
Pad
GND
OUT3 10
OUT4 11
OUT5 12
OUT6 13
OUT7 14
OUT6
10
BLANK 31
32
OUT5
XLAT
9
NC = No internal connection.
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SBVS101–DECEMBER 2007
TERMINAL FUNCTIONS
TERMINAL
NAME
SIN
PWP
RHB
I/O
DESCRIPTION
Serial data input for grayscale and brightness control data. Schmitt buffer input.
5
2
I
Serial data shift clock for GS shift register and BC shift register. Schmitt buffer input. The shift
register is selected by BCSEL. Data present on the SIN pin are shifted into the shift register
selected by BCSEL with the rising edge of the SCLK pin. Data in the selected shift register are
shifted to the MSB side by 1-bit synchronizing to the rising edge of SCLK. The MSB data of the
selected register appears on SOUT.
SCLK
4
1
I
Data in the Grayscale and Brightness shift register are moved to the respective first data latch
with a low-to-high transition of this pin.
XLAT
3
6
32
3
I
I
I
Shift register and data latch select. Schmitt buffer input. When BCSEL is low, Grayscale shift
register and first data latch are selected. When BCSEL is high, Brightness Control shift register
and first data latch are selected. BCSEL should not be changed while SCLK is high.
BCSEL
GSCLK
Reference clock for Grayscale PWM control. Schmitt buffer input. If BLANK is low, then each
rising edge of GSCLK increments the grayscale counter for PWM control.
25
24
Blank (all constant current outputs off). Schmitt buffer input. When BLANK is high, all constant
current outputs (OUT0 through OUT15) are forced off, the Grayscale counter is reset to '0', and
the Grayscale PWM timing controller is initialized. When BLANK is low, all constant current
outputs are controlled by the Grayscale PWM timing controller.
BLANK
2
31
I
Constant current value setting. OUT0 through OUT15 sink constant current is set to desired
value by connecting an external resistor between IREF and GND.
IREF
27
24
26
23
I/O
O
Serial data output. This output is connected to Grayscale/Status Information shift register or
Brightness Control shift register. The connected register is selected by BCSEL.
SOUT
XERR
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
VCC
23
7
22
4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
I
Error output. Open-drain output. XERR goes low when LOD or TEF is detected.
Constant current output.
8
5
Constant current output
9
6
Constant current output
10
11
12
13
14
15
16
17
18
19
20
21
22
28
1
7
Constant current output
8
Constant current output
9
Constant current output
10
11
14
15
16
17
18
19
20
21
27
30
25
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Constant current output
Power-supply voltage
GND
Power ground
XTEST
26
Factory test pin. XTEST must be connected to VCC or GND.
12, 13,
28, 29
NC
—
—
No internal connection
8
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SBVS101–DECEMBER 2007
PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
INPUT
SOUT
GND
GND
Figure 1. SIN, SCLK, XLAT, BCSEL, BLANK, GSCLK
Figure 2. SOUT
OUTn
XERR
GND
GND
Figure 3. XERR
Figure 4. OUT0 Through OUT15
TEST CIRCUITS
RL
CL
VCC
GND
VCC
VCC
IREF
OUTn
SOUT
VLED
VCC
(1)
(1)
CL
RIREF
GND
(1) CL includes measurement probe and jig
capacitance.
Figure 5. Rise Time and Fall Time Test Circuit for OUTn
(1) CL includes measurement probe and jig
capacitance.
Figure 6. Rise Time and Fall Time Test Circuit for SOUT
VCC
OUT0
OUTn
VCC
RL
VCC
VCC
IREF
XERR
VXERR
(1)
CL
RIREF
GND OUT15
GND
VOUTn
VOUTFIX
Figure 8. Constant Current Test Circuit for OUTn
(1) CL includes measurement probe and jig
capacitance.
Figure 7. Rise Time and Fall Time Test Circuit for XERR
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SBVS101–DECEMBER 2007
TIMING DIAGRAMS
TWH0, TWH1, TWL0
VCC
GND
INPUT(1) 50%
TWH
TWL
TSU0, TSU1, TSU2, TSU3, TSU4, TSU5, TSU6, TH0, TH1, TH2, TH3
VCC
CLOCK
50%
INPUT(1)
GND
VCC
TSU
TH
DATA/CONTROL
50%
INPUT(1)
GND
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 9. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5
:
VCC
INPUT(1)
50%
GND
tD
VOH or VOUTn
H
90%
50%
10%
OUTPUT(2)
VOL or VOUTn
L
tR or tF
(1) Input pulse rise and fall time is 1 ns to 3 ns.
(2) Input pulse high level is VCC and low level is GND.
Figure 10. Output Timing
10
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SBVS101–DECEMBER 2007
BCSEL
TSU4
TH3
TSU3
GS0
0A
GS15 GS15 GS15
13B
GS15 GS15
12B
11B
GS0
3B
GS0
2B
GS0
1B
GS0
0B
SIN
15B
14B
TH0
TSU0
TWH0
TH1
TSU1
SCLK
1
2
3
4
5
253 254 255 256
TH2
TWL0
TWH0
GSCLK
65,53465,535 65,536 65,537 65,538
TWL0
TGSCLK
TWH1
XLAT
TSU6
TWH1
BLANK
TSU2
Latched Data
for Grayscale
(Internal)
Previous Data
Latest Data
tD0
GS15
15A
GS15 GS15 GS15 GS15
12A
GS15
10A
GS0
3A
GS0
2A
GS0
1A
GS0
0A
GS15
15B
LOD
15
LOD
14
LOD
13
LOD
12
LOD
11
LOD
10
LOD
9
SOUT
14A
13A
11A
tR0/tF0
tD1
Turning off outputs with the BLANK signal (all GS data are greater than 0300h):
(VOUTnH)
OFF
(VOUTnL)
OUT
0, 4, 8, 12 ON
tD2
OFF
OUT
1, 5, 9, 13
ON
If GS data = FFFFh (65535d)
tF1
tD3
tR1
OFF
OUT
2, 6, 10, 14 ON
tD4
OFF
OUT
3, 7, 11, 15
ON
tD5
Turning off outputs with GSCLK (all GS data are set to 0001h):
OFF
OUT
0, 4, 8, 12 ON
tD2
tOUTON
OFF
OUT
1, 5, 9, 13
ON
tD3
tD4
tD5
tOUTON
OFF
OUT
2, 6, 10, 14 ON
tOUTON
OFF
OUT
3, 7, 11, 15
ON
tOUTON
tON_ERR = tOUTON - TGSCLK
Figure 11. Grayscale Data Write and Constant Current Output Timing
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SBVS101–DECEMBER 2007
BCSEL
TSU4
TH3
TSU3
BC
7B
BC
6B
BC
5B
BC
4B
BC
3B
BC
2B
BC
1B
BC
0B
BC
7C
BC
6C
BC
5C
BC
4C
BC
3C
BC
2C
BC
1C
BC
0C
N/A
SIN
TH0
TSU0
TH2
TWH0
TSU1
SCLK
1
2
3
4
5
6
TWL0
7
8
1
2
3
4
5
6
7
8
TH1
TWH1
XLAT
Latched Data
for Brightness Control
(Internal)
Previous Data
New BC Data
tD0
BC
7A
BC
6A
BC
5A
BC
4A
BC
3A
BC
2A
BC
1A
BC
0A
BC
7B
BC
6B
BC
5B
BC
4B
BC
3B
BC
2B
BC
1B
BC
0B
BC
7C
SOUT
tR0/tF0
Figure 12. Brightness Control Data Write Timing
Low ('L') level
BCSEL
The SCLK falling edge must be prior to the XLAT rising edge in case SID is read.
GS0
1A
GS0
0A
GS15 GS15
15B
14B
GS15 GS15
13B 12B
GS15
11B
GS15
2B
GS15 GS15 GS14
0B
1B 15B
GS14 GS14
14B
13B
GS14
12B
GS0
1B
GS0
0B
SIN
SCLK
XLAT
SOUT
255 256
1
2
3
4
5
13
14
15
16
17
18
19
20 254 255 256
TSU1
TH1 TWH1 TSU5
tD0
GS0
0
GS15
15A
LOD
15
LOD
14
LOD
13
LOD
12
LOD
3
LOD
2
LOD
1
LOD
0
GS14 GS14
13A
GS0
1A
GS0
0A
GS15
15B
TEF
14A
256
255
254
253
244
243
242
241
239
238
2
1
SID are entered in the GS shift register at the first rising edge of SCLK after XLAT goes low.
The SID readout consists of the saved LOD result at the 33rd GSCLK rising edge in the previous display period
and the TEF data after the previous TEF data readout.
Figure 13. Status Information Data Read Timing
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SBVS101–DECEMBER 2007
TYPICAL CHARACTERISTICS
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
REFERENCE RESISTOR vs
OUTPUT CURRENT
POWER DISSIPATION RATE
vs FREE-AIR TEMPERATURE
10000
4000
3000
2000
1000
0
9840
TLC5943PWP
PowerPAD Soldered
TLC5943RHB
4920
3280
TLC5943PWP
PowerPAD Not Soldered
2460
1968
1640
1406
1093
1230
40
984
50
1000
0
10
20
30
-40
-20
0
20
40
60
80
100
Output Current (mA)
Free-Air Temperature (°C)
Figure 14.
Figure 15.
OUTPUT CURRENT vs
OUTPUT VOLTAGE
OUTPUT CURRENT vs
OUTPUT VOLTAGE
60
55
54
53
52
51
50
49
48
47
46
45
TA = +25°C
BC = 7Fh
IO = 50 mA
BC = 7Fh
IO = 50 mA
IO = 40 mA
50
40
30
20
10
0
TA = +85°C
IO = 30 mA
IO = 20 mA
IO = 10 mA
TA = -40°C
TA = +25°C
IO = 5 mA
2.5
0
0.5
1.0
1.5
2.0
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
Output Voltage (V)
Output Voltage (V)
Figure 16.
Figure 17.
ΔIOLC vs
AMBIENT TEMPERATURE
ΔIOLC vs
OUTPUT CURRENT
5
4
5
4
IO = 50 mA
BC = 7Fh
TA = +25°C
BC = 7Fh
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
-40
-20
0
20
40
60
80
100
0
10
20
30
40
50
Ambient Temperature (°C)
Output Current (mA)
Figure 18.
Figure 19.
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TYPICAL CHARACTERISTICS (continued)
At VCC = 3.3 V and TA = +25°C, unless otherwise noted.
BRIGHTNESS CONTROL LINEARITY
BRIGHTNESS CONTROL LINEARITY
60
60
50
40
30
20
10
0
TA = +25°C
IOLCMax = 50 mA
50
IOLCMax = 50 mA
40
30
20
IOLCMax = 30 mA
TA = -40°C
TA = +25°C
TA = +85°C
10
IOLCMax = 5 mA
0
0
20
40
60
80
100
120
140
0
20
40
60
80
100
120
140
Brightness Control Data (dec)
Brightness Control Data (dec)
Figure 20.
Figure 21.
CONSTANT CURRENT OUTPUT
VOLTAGE WAVEFORM
CH1-GSCLK
(30 MHz)
CH1 (2 V/div)
CH2 (2 V/div)
CH2-OUT0
(GSData = 0x001h)
CH3-OUT15
(GSData = 0x001h)
CH3 (2 V/div)
IOLCMax = 50 mA, BC = 7Fh
TA = +25°C,RL = 82 W
CL = 15 pF, VLED = 5 V
Time (25 ns/div)
Figure 22.
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SBVS101–DECEMBER 2007
DETAILED DESCRIPTION
Setting for the Maximum Constant Sink Current Value
On the TLC5943, the maximum constant current sink value for each channel, IOLCMax, is determined by an
external resistor, RIREF, placed between the IREF and GND pins. The RIREF resistor value is calculated with
Equation 1:
VIREF (V)
´ 41
RIREF (kW) =
IOLCMax (mA)
(1)
Where:
•
VIREF = the internal reference voltage on the IREF pin (typically 1.20 V)
IOLCMax is the largest current for all outputs. Each output sinks the IOLCMax current when it is turned on and the
brightness control data are set to the maximum value of 7Fh (127d). The sink current for each output can be
reduced by lowering the brightness control data.
RIREF must be between 984 Ω (typ) and 9.84 kΩ (typ) in order to keep IOLCMax between 5 mA and 50 mA. The
output may become unstable when IOLCMax is set lower than 5 mA. However, output currents lower than 5 mA
can be achieved by setting IOLCMax to 5 mA or higher, and then using brightness control to lower the output
current.
Figure 14 in the Typical Characteristics and Table 1 show the characteristics of the constant sink current versus
the external resistor, RIREF
.
Table 1. Maximum Constant Current Output versus
External Resistor Value
IOLCMax (mA, Typical)
RIREF (Ω)
984
50
45
40
35
30
25
20
15
10
5
1093
1230
1406
1640
1968
2460
3280
4920
9840
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SBVS101–DECEMBER 2007
Brightness Control (BC) Function
The TLC5943 is able to adjust the output current of all channels (OUT0 to OUT15). This function is called
brightness control (BC). The BC function allows users to adjust the global brightness of LEDs connected to the
outputs OUT0 to OUT15. All channel output currents can be adjusted in 128 steps from 0% to 100% of the
maximum output current, IOLCMax. The brightness control data are entered into the TLC5943 via the serial
interface.
Equation 2 determines the sink current for each output (OUTn):
BCn
IOUTn (mA) = IOLCMax (mA) ´ (
)
127d
(2)
Where:
•
•
IOLCMax = the maximum channel current for each channel determined by RIREF
BCn = the programmed brightness control value for OUTn (BCn = 0 to 127d)
When the IC is powered on, the data in the Brightness Control Shift Register and data latch 1 and 2 are not set
to any default values. Therefore, BC data must be written to the BC latch 1 and 2 before turning on the constant
current output.
Table 2 summarizes the BC data versus current ratio and set current value.
Table 2. BC Data versus Current Ratio and Set Current Value
SET CURRENT
RATIO TO
MAX CURRENT (%)
OUTPUT CURRENT
(mA, Typical)
AT IOLCMax = 50 mA
OUTPUT CURRENT
(mA, Typical)
AT IOLCMax = 5 mA
BC DATA
(Binary)
BC DATA
(Decimal)
BC DATA
(Hex)
000 0000
000 0001
000 0010
... ...
0
1
00
01
0.0
0.8
0.0
0.4
0.00
0.04
0.08
... ...
4.92
4.96
5.00
2
02
1.6
0.8
... ...
125
126
127
... ...
7D
7E
7F
... ...
98.4
99.2
100.0
... ...
49.2
49.6
50.0
111 1101
111 1110
111 1111
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SBVS101–DECEMBER 2007
Grayscale (GS) Function (Enhanced Spectrum PWM Operation)
The TLC5943 has an enhanced spectrum pulse-width modulation (ES PWM) function. In this PWM control, the
total display period is divided to 128 display segments. Total display period means the timing from the first
grayscale clock (GSCLK) input to the 65,536th grayscale clock input after BLANK goes low. Each display period
has 512 grayscale as a maximum. The driver (OUTn) on time changes depending on the 16-bit grayscale data.
Refer to Table 3 for sequence information and Figure 23 for timing information.
Table 3. ES PWM Drive Turn-On Time Length
GS DATA (Dec)
GS DATA (Hex)
0000h
OUTn DRIVER OPERATION
0
1
2
3
4
5
6
No turn on
0001h
Turns on during 1GSCLK period in first display period
0002h
Turns on during 1GSCLK period in first and 65th display periods
Turns on during 1GSCLK period in first, 65th, and 33rd display periods
Turns on during 1GSCLK period in first, 65th, 33rd, and 97th display periods
Turns on during 1GSCLK period in first, 65th, 33rd, 97th, and 17th display periods
0003h
0004h
0005h
0006h
Turns on during 1GSCLK period in first, 65th, 33rd, 97th, 17th, and 81st display
periods
---
---
The number of display periods in which OUTn turns on during 1GSCLK is
increased by GS data increasing in the following order.
The display period order in which OUTn turns on :
1>65>33>97>17>81>49>113>9>73>41>105>25>89>57>121>5>69>37>101>21>
85>53>117>13>77>45>109>29>93>61>125>3>67>35>99>19>83>51>115>11>
75>43>107>27>91>59>123>7>71>39>103>23>87>55>119>15>79>47>111>31>
95>63>127>2>66>34>98>18>82>50>114>10>74>42>106>26>90>58>122>6>70>
38>102>22>86>54>118>14>78>46>110>30>94>62>126>4>68>36>100>20>84>
52>116>12>76>44>108>28>92>60>124>8>72>40>104>24>88>56>120>16>80>
48>112>32>96>64>128.
127
007Fh
Turns on during 1GSCLK period in first through 127th display period. No turn on in
128th display period only.
128
129
0080h
0081h
Turns on during 1GSCLK period in all (1 through 128th) display periods.
Turns on during 2GSCLK periods in first display period and 1GSCLK period in
other display periods.
---
---
The number of display periods in which OUTn turns on during 2GSCLKs increases
by GS data as when GS is 130 through 254.
255
00FFh
Turns on during 2GSCLKs period in 1 through 127th display period and turns on
1GSCLK period in 128th display period only.
256
257
0100h
0101h
Turns on during 2GSCLK periods in all (1 through 128th) display periods.
Turns on during 3GSCLK periods in first display period and 2GSCLK periods in
other display periods.
---
---
Display period in which OUTn turn-on time increases by GS data, increasing as
does above operation
65478
FEFFh
Turns on during 511 GSCLK period in 1 through 127th display period and turns on
510 GSCLK period in 128th display period only.
65279
65280
FF00h
FF01h
Turns on during 511 GSCLK period in all (1 through 128th) display periods.
Turns on during 512 GSCLK period in first display period + 511 GSCLK period in
second through 128th display period.
---
---
Display period in which OUTn turn-on time increases by GS data, increasing as
does above operation
65534
65535
FFFEh
FFFFh
Turns on during 512 GSCLK period in first through 63rd and 65th through 127th
display period, and turns on 511 GSCLK period in 64th and 128th display periods.
Turns on during 512 GSCLK period in first through 127th display periods, and turns
on 511 GSCLK period in 128th display period only.
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Constant Current Driver ON/OFF Tming in ES-PWM
BLANK
512 514
511 513
16,383 16,385 16,387 32,767 32,769 32,771
32,766 32,768 32,770
49,151 49,153 49,155 65,024 65,026
49,150 49,152 49,154
65,535
65,534 65,536
1
2
3
16,382 16,384 16,386
65,023 65,025
GSCLK
OFF
2nd
Period
32nd 33rd
64th 65th
96th 97th
127th
¼
¼
¼
¼
1st Period
128th Period
1st Period
Voltage level = High ('H')
Period Period
Period Period
Period Period
Period
OUTn
Voltage level = Low ('L’)
ON
(GSDATA = 000h)
T = GSCLK ´ 1d
OFF
OUTn
ON
(GSDATA = 001h)
If Auto Repeat
is enabled
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
OFF
OUTn
ON
(GSDATA = 002h)
T = GSCLK ´ 1d
T = GSCLK ´ 1d
OFF
OUTn
ON
(GSDATA = 003h)
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
OFF
OUTn
ON
(GSDATA = 004h)
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
OFF
OUTn
ON
(GSDATA = 0041h)
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK
´ 1d
OFF
OUTn
ON
(GSDATA = 0080h)
T = GSCLK
´ 2d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK ´ 1d
T = GSCLK
´ 1d
OFF
OUTn
ON
(GSDATA = 0081h)
T = GSCLK
´ 2d
T = GSCLK
´ 2d
T = GSCLK
´ 1d
OFF
OUTn
ON
(GSDATA = 0082h)
T = GSCLK ´ 511d
T = GSCLK ´ 511d
T = GSCLK ´ 512d
in 2nd through 128th Periods
OFF
OUTn
ON
T = GSCLK ´ 511d
(GSDATA = FFC0h)
in 2nd through 128th Periods
OFF
OUTn
ON
(GSDATA = FFC1h)
T = GSCLK ´ 512d in 2nd through 63rd and 65th through 127th Periods;
T = GSCLK ´ 511d in 64th Period
T = GSCLK ´ 512d
T = GSCLK ´ 512d
T = GSCLK ´ 511d
T = GSCLK ´ 511d
OFF
OUTn
ON
(GSDATA = FFFEh)
T = GSCLK ´ 512d in 2nd through 127th Periods
OFF
OUTn
ON
(GSDATA = FFFFh)
Figure 23. PWM Operation Timing
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When the IC powers on, the data in the Grayscale Shift Register and latch 1/2 are not set to any default value.
Therefore, grayscale data must be written to the Grayscale latch before turning on the constant current output.
Additionally, BLANK should be high when the device turns on, to prevent the outputs from turning on before the
proper grayscale and brightness control values can be written. All constant current outputs are always off when
BLANK is high. Equation 3 determines each output (OUTn) total on time (tOUTON):
tOUTON (ns) = TGSCLK (ns) ´ GSn
(3)
Where:
•
•
TGSCLK = the period of GSCLK
GSn = the programmed grayscale value for OUTn (GSn = 0 to 65,535d)
Table 4 summarizes the GS data versus OUTn on duty and on time.
Table 4. GS Data versus OUTn Total On Duty
GS DATA (Decimal)
GS DATA (Hex)
ON-TIME DUTY (%)
0
GS DATA (Decimal)
32768
32769
32770
32771
---
GS DATA (Hex)
8000
8001
8002
8003
---
ON-TIME DUTY (%)
50.001
50.002
50.004
50.005
---
0
0
1
1
0.002
0.003
0.005
---
2
2
3
3
---
---
8191
8192
8193
---
1FFF
2000
2001
---
12.499
12.5
40959
40960
40961
---
9FFF
A000
A001
---
62.499
62.501
62.502
---
12.502
---
16381
16382
16383
16384
16385
16386
16387
---
3FFD
3FFE
3FFF
4000
4001
4002
4003
---
24.996
24.997
24.999
25
49149
49150
49151
49152
49153
49154
49155
---
BFFD
C000
C001
C002
C003
C004
C005
---
74.997
74.998
75
75.001
75.003
75.004
75.006
---
25.002
25.003
25.005
---
24575
24576
24577
---
5FFF
6000
6001
37.499
37.501
37.502
---
57343
57344
57345
---
DFFF
E000
E001
87.5
87.501
87.503
---
32765
32766
32767
7FFD
7FFE
7FFF
49.996
49.998
49.999
65533
65534
65535
FFFD
FFFE
FFFF
99.997
99.998
100
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SBVS101–DECEMBER 2007
Auto Display Repeat Function
This function can repeat the total display period without a BLANK signal as long as GSCLK is input as Figure 24
shows. This function can be switched on or off by the data of bit 7 in the first latch of the Brightness Control.
When bit 7 is '1', Auto Repeat is enabled and the entire display period repeats without a BLANK signal. When bit
7 is '0', Auto Repeat is disabled and the entire display period executes only one time after the falling edge of
BLANK.
BLANK
65,534 65,536
65,533 65,535
65,534 65,536
65,533 65,535
65,534 65,536
¼
¼
¼
1
2
3
4
5
1
2
3
4
5
1
2
3 6
4 5
7
8
9
10
1
2
65,535 1
2
GSCLK
Bit 7 = ‘1’
(Auto Repeat On)
Bit 7 = ‘0’
(Auto Repeat Off)
Brightness
1st Latch
Bit 7
1st of 128
display period
2nd of 128
display period
3rd of 128
display period
1st of 128
display period
OUTn is not
turned on until
next BLANK
falling edge
Display period repeated
by Auto Refresh function
OUTn is forced off
when BLANK goes high
OFF
OUTn
(GSData = FFFFh)
ON
Figure 24. Auto Repeat Display Function Timing
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Auto Data Refresh Function
This function allows users to input Grayscale (GS) data or Brightness Control (BC) data any time without
synchronizing the input to the BLANK signal. If GS data or BC data are input during a display period, the input
data are held in the first latch for each data register. Data are then transferred to the second latch when the
65,536th GSCLK occurs. The second latch data are used for the next display period. Figure 25 through
Figure 27 show the timing.
However, when the high level signal of BLANK occurs before the 65,536th GSCLK, then the first latch data
upload to the second latch immediately. Also, when the XLAT rising edge inputs while BLANK is at a high level,
then the selected shift register data are transferred to the first and second latch at the same time. Bit 7 data of
BC update immediately whenever the data are written into the first latch.
GS0
4A
GS0
3A
GS0
2A
GS0
1B
GS0
0A
BC
7A
BC
6A
BC
5A
BC
4A
BC
3A
BC
2A
BC
1A
BC
0A
GS15 GS15 GS15 GS15
15B 14B 13B 12B
SIN
SCLK
BCSEL
XLAT
251 252 253 254 255 256
1
2
3
4
5
6
7
8
1
2
3
4
Low level ('L') = Grayscale Register is selected
High level ('H') = Brightness Register is selected
65,536
65,535
1
2
3
4
5
6
7
8
GSCLK
BLANK
Low level ('L')
GS Shift Register
(Internal)
Latest Grayscale Data
Latest Grayscale Data
Previous Grayscale Data
GSData
1st Latch (Internal)
Previous Grayscale Data
GSData
2nd Latch (Internal)
Latest Grayscale Data
BC Shift Register
(Internal)
Previous Brightness Data
Latest Brightness Data
Latest Brightness Data
BCData
1st Latch (Internal)
Previous Brightness Data
BCData
2nd Latch (Internal)
Previous Brightness Data (Bit 0-Bit 6)
PWM/Brightness Controlled by Previous Data
Latest Brightness Data (Bit 0-Bit 6)
OFF
OUTn
ON
PWM/Brightness Controlled by Latest Data
GS0
4
GS0
3
GS0
2
GS0
1
GS0
0
GS15
15A
BC
7
BC
6
BC
5
BC
4
BC
3
BC
2
BC
1
BC
0
BC
7A
GS15
15A
GS15 GS15 GS15 GS15
14A 13A 12A 11A
SOUT
If there is no BLANK input when Auto Repeat is enabled.
Figure 25. Auto Refresh Data Function Timing 1
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GS0
SIN
4A
GS0
3A
GS0
2A
GS0
1B
GS0
0A
BC
7A
BC
6A
BC
5A
BC
4A
BC
3A
BC
2A
BC
1A
BC
0A
GS15 GS15 GS15 GS15
15B 14B 13B 12B
SCLK
251 252 253 254 255 256
1
2
3
4
5
6
7
8
1
2
3
4
Low level ('L') = Grayscale Register is selected
High level ('H') = Brightness Register is selected
BCSEL
XLAT
1
2
3
4
5
6
7
8
GSCLK
BLANK
Low level ('L')
GS Shift Register
(Internal)
Latest Grayscale Data
Latest Grayscale Data
Previous Grayscale Data
GSData
1st Latch (Internal)
Previous Grayscale Data
GSData
2nd Latch (Internal)
Latest Grayscale Data
Latest Brightness Data
Latest Brightness Data
BC Shift Register
(Internal)
Previous Brightness Data
BCData
1st Latch (Internal)
Previous Brightness Data
BCData
2nd Latch (Internal)
Previous Brightness Data (Bit 0-Bit 6)
PWM/Brightness Controlled by Previous Data
Latest Brightness Data (Bit 0-Bit 6)
OFF
OUTn
ON
PWM/Brightness Controlled by Latest Data
GS0
4
GS0
3
GS0
2
GS0
1
GS0
0
GS15
15A
BC
7
BC
6
BC
5
BC
4
BC
3
BC
2
BC
1
BC
0
BC
7A
GS15
15A
GS15 GS15 GS15 GS15
14A 13A 12A 11A
SOUT
When the BLANK input occurs after XLAT.
Figure 26. Auto Refresh Data Function Timing 2
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GS0
4A
GS0
3A
GS0
2A
GS0
1B
GS0
0A
BC
7A
BC
6A
BC
5A
BC
4A
BC
3A
BC
2A
BC
1A
BC
0A
GS15 GS15 GS15 GS15
13B
SIN
15B
14B
12B
SCLK
BCSEL
XLAT
251 252 253 254 255
256
1
2
3
4
5
6
7
8
1
2
3
4
Low level ('L') = Grayscale Register is selected
High level ('H') = Brightness Register is selected
1
2
3
4
5
6
7
8
GSCLK
BLANK
Low level ('L')
GS Shift Register
(Internal)
Latest Grayscale Data
Previous Grayscale Data
Previous Grayscale Data
GSData
1st Latch (Internal)
Latest Grayscale Data
Latest Grayscale Data
Latest Brightness Data
Latest Brightness Data
GSData
2nd Latch (Internal)
BC Shift Register
(Internal)
Previous Brightness Data
BCData
1st Latch (Internal)
Previous Brightness Data
BCData
2nd Latch (Internal)
Previous Brightness Data (Bit 0-Bit 6)
Latest Brightness Data (Bit 0-Bit 6)
OFF
OUTn
ON
PWM/Brightness Controlled by Previous Data
PWM/Brightness Controlled by Latest Data
GS0
4
GS0
3
GS0
2
GS0
1
GS0
0
GS15
15A
BC
7
BC
6
BC
5
BC
4
BC
3
BC
2
BC
1
BC BC GS15
7A 15A
BC
7A
GS15 GS15 GS15 GS15 GS15
15A 14A 13A 12A 11A
SOUT
0
When the BLANK input occurs with XLAT.
Figure 27. Auto Refresh Data Function Timing 3
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Grayscale (GS) Shift Register and Data Latch
The Grayscale (GS) Shift Register and data latch 1 and 2 are each 256 bits in length, and set the PWM timing
for each constant current driver. See Table 4 for the ON time duty of each GS data bit. Figure 28 shows the shift
register and latch configuration. Refer to Figure 11 for the timing diagram for writing data into the GS shift
register and latch.
The driver on time is controlled by the data in the GS second data latch. GS data can be set into the latch by the
rising edge of XLAT with BCSEL = low after writing data into the GS shift register with SIN and GSCLK with
BCSEL = low. A BCSEL level change occurs during SCLK = low, and after 100 ns from the rising edge of XLAT.
When the device powers up, the data in the GS shift register and latches are not set to any default value.
Therefore, GS data must be written to the GS latch before turning on the constant current output. Also, BLANK
should be at a high level when powering on the device, because the constant current may be turned on as well.
All constant current output is off when BLANK is at a high level.
GS Data for OUT15
MSB
GS Data for OUT0
LSB
SIN with
255
240
239
16
15
0
BCSEL = low
GS Data
for Bit 15
of OUT15
GS Data
for Bit 0
GS Data
for Bit 15
of OUT14
GS Data
for Bit 0
of OUT1
GS Data
for Bit 15
of OUT0
GS Data
for Bit 0
of OUT0
¼
¼
¼
of OUT15
SCLK with
BCSEL = low
Grayscale Shift Register (16 Bits x 16 Channels)
¼
¼
¼
GS Data for OUT15
MSB
GS Data for OUT14
¼
GS Data for OUT1
GS Data for OUT0
LSB
255
240
239
16
15
0
GS Data
for Bit 15
of OUT15
GS Data
for Bit 0
GS Data
for Bit 15
of OUT14
GS Data
for Bit 0
of OUT1
GS Data
for Bit 15
of OUT0
GS Data
for Bit 0
of OUT0
XLAT with
¼
¼
¼
BCSEL = low
of OUT15
Grayscale Data Latch 1 (16 Bits x 16 Channels)
¼
¼
¼
GS Data for OUT15
MSB
GS Data for OUT14
¼
GS Data for OUT1
GS Data for OUT0
LSB
255
240
239
16
15
0
65,536th GSCLK
when Auto Repeat is
enabled or Blank
with BCSEL = low
GS Data
for Bit 15
of OUT15
GS Data
for Bit 0
GS Data
for Bit 15
of OUT14
GS Data
for Bit 0
of OUT1
GS Data
for Bit 15
of OUT0
GS Data
for Bit 0
of OUT0
¼
¼
¼
of OUT15
Grayscale Data Latch 2 (16 Bits x 16 Channels)
256 Bits
To PWM Timing Control Block
Figure 28. Grayscale Shift Register and Data Latch Configuration
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Brightness Control (BC) Shift Register and Data Latch
The Brightness Control (BC) data shift register and the first latch are each 8 bits long; the second latch is 7 bits
long. The lower 7 bits in the latch are used to adjust the constant current value for all channels of the constant
current driver. The MSB of the first latch is used for the auto repeat mode setting. Table 5 shows the ratio of
setting the current value against the maximum current value for each BC data point. Figure 29 shows the shift
register and latch configuration for BC data. Figure 12 shows the timing for writing data.
The driver constant current value is controlled by the data in the second BC data latch. BC data can be set into
the latch at the rising edge of XLAT with BCSEL = high after writing the data into the BC Shift Register by SIN
and SCLK with BCSEL = high. A BCSEL level change occurs during SCLK = low and after 100 ns from the rising
edge of XLAT. When powered up, the data in the BC Shift Register and latches are not set to any default value.
Therefore, brightness data must be written to the BC latch before turning on the constant current output.
Table 5. BC Data vs Current Ratio
BC Data (Dec)
BC Data (Lower 7 Bits; Hex)
Ratio of Setting Current Value Against MAX Value (%)
0
1
0
1
0
0.8
1.6
2.4
---
2
2
3
3
---
125
126
127
---
7D
7E
7F
98.4
99.2
100
MSB
7
LSB
0
Shift
Data
SIN with
BCSEL = high
6
5
4
3
2
1
Auto-Repeat
1 = Repeat
BC Data
for Bit 6
BC Data
for Bit 5
BC Data
for Bit 4
BC Data
for Bit 3
BC Data
for Bit 2
BC Data
for Bit 1
BC Data
for Bit 0
SOUT
SCLK with
BCSEL = high
Shift
Clock
Brightness/Auto Repeat Control Shift Register (8 Bits)
MSB
7
LSB
0
6
5
4
3
2
1
Latch
Signal
XLAT rising edge with
BCSEL = high
Auto-Repeat
1 = Repeat
BC Data
for Bit 6
BC Data
for Bit 5
BC Data
for Bit 4
BC Data
for Bit 3
BC Data
for Bit 2
BC Data
for Bit 1
BC Data
for Bit 0
Brightness/Auto Repeat Control Data Latch 1 (8 Bits)
MSB
6
LSB
0
5
4
3
2
1
Latch
Signal
65,536th GSCLK when
Auto Repeat is enabled
or BLANK with BCSEL = high
BC Data
for Bit 6
BC Data
for Bit 5
BC Data
for Bit 4
BC Data
for Bit 3
BC Data
for Bit 2
BC Data
for Bit 1
BC Data
for Bit 0
Brightness Control Data Latch 2 (7 Bits)
1 Bit
7 Bits
To PWM Control Block
To Constant Current Driver
Figure 29. Brightness Control Shift Register and Latch Configuration
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Status Information Data (SID)
Status information data (SID) are 17-bit, read-only data. Both the LED open detection (LOD) error and the
thermal error flag (TEF) are shifted out onto the SOUT pin with each rising edge of the shift clock, SCLK. The 16
LOD bits for each channel and the TEF bit are written into the 17 most significant bits of the Grayscale Shift
Register at the rising edge of the first SCLK after XLAT goes low. As a result, the previous data in the 17 most
significant bits are lost at the same time. No data are loaded into the other 175 bits. Figure 30 shows the bit
assignments. Figure 13 illustrates the read timing for the status information data.
Status Information Data (SID) Configuration
LOD Data of OUT15 to OUT0
TEF (1 Bit)
MSB
16
LSB
0
¼
15
2
1
OUT15
LOD Data
OUT14
LOD Data
OUT1
LOD Data
OUT0
LOD Data
¼
TEF Data
The 16 LOD bits for each channel and the TEF bit overwrite
the most significant 17 bits of the Grayscale Shift Register at the
rising edge of the first SCLK after XLAT goes low.
¼
GS Data for OUT15
GS Data for OUT14-OUT1
GS Data for OUT0
MSB
255
LSB
0
254
241
240
239
16
15
SIN
OUT15-Bit15 OUT15-Bit1
(LOD-OUT15) (LOD-OUT14)
OUT15-Bit1 OUT15-Bit0 OUT14-Bit15
(TEF)
¼
¼
¼
OUT1-Bit0 OUT0-Bit15
OUT0-Bit0
SOUT
(LOD-OUT1) (LOD-OUT0)
SCLK
(BCSEL = low)
Grayscale Shift Register (16 Bits ´ 16 Channels)
Figure 30. Status Information Data Configuration
The LOD data update at the rising edge of the 33rd GSCLK pulse after BLANK goes low; the LOD data are
retained until the next 33rd GSCLK. LOD data are only checked for outputs that are turned on during the rising
edge of the 33rd GSCLK pulse. A '1' in an LOD bit indicates an open LED or short LED to GND condition for the
corresponding channel. A '0' indicates normal operation. LOD shows a '0' even if the LED is open or shorted to
GND when the grayscale data are less than 1000h (4096d). Therefore, grayscale data must be greater than
1001h (4097d) to correctly receive LOD data.
The TEF bit indicates that the IC temperature is too high. The flag also indicates that the IC has turned off all
drivers to avoid damage by overheating the device. A '1' in the TEF bit means that the IC temperature has
exceeded the detect temperature threshold (T(TEF)) and the driver is turned off. A '0' in the TEF bit indicates
normal operating temperature conditions. The IC automatically turns the drivers back on when the IC
temperature decreases to less than T(TEF) –T(HYS). When the IC powers on, LOD data do not show correct values.
Therefore, LOD data must be read from the 33rd GSCLK pulse input after BLANK goes low. Table 6 shows a
truth table for both LOD and TEF.
Table 6. LOD and TEF Truth Table
CONDITION
SID DATA
LED OPEN DETECTION (LODn)
LED is connected (VOUTn > VLOD
LED is open or shorted to GND (VOUTn ≤ VLOD
THERMAL ERROR FLAG (TEF)
0
1
)
Device temperature is low (temp ≤ T(TEF) –T(HYS))
)
Device temperature is high (temp > T(TEF))
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Noise Reduction
Large surge currents may flow through the IC and the printed circuit board (PCB) on which the device is mounted
if all 16 LED channels turn on simultaneously at the start of each grayscale cycle. These large current surges
could introduce detrimental noise and electromagnetic interference (EMI) into other circuits. The TLC5943 turns
on the LED channels in a series delay to provide a circuit soft-start feature. The output current sinks are grouped
into four groups of four channels each. The first group is OUT0,4,8,12; the second group is OUT1,5,9,13; the
third group is OUT2,6,10,14; and the fourth group is OUT3,7,11,15. Each group is turns on sequentially with a
small delay between groups; see Figure 11. Both turn-on and turn-off are delayed.
Continuous Base LED Open Detection
When the 33rd GSCLK goes high in the first display period after a BLANK falling edge, the LED open detection
(LOD) circuit checks the voltage of each constant current output (OUT0 through OUT15 = OUTn) that is turned
on to detect open LEDs and short LEDs to GND. Then, if the voltage of OUTn is less than the LED open
detection threshold (VLOD = 0.3 VTYP), it sets '1' as the error flag to the LOD error bit that corresponds with the
error channel in the Status Information Data (SID) register. Also, the XERR pin level moves from Hi-Z at the
same time. As a result, GS data should be over 1001h (4097d) to get the LOD result. The OUTn channel that
has the detected LOD error is forced off to avoid an increase in the VCC supply current. OUTn turns on at the first
GSCLK after a BLANK falling edge again. LOD data are kept until the next 33rd rising edge of GSCLK in the first
display period after a BLANK falling edge. LOD is always '0' when grayscale data are less than 1001h (4097d).
XERR is forced to a Hi-Z state while BLANK is high. When powered up, LOD data are not set to any default
value. Therefore, SID data must be used after OUTn turns on with over 1001h GS data. Figure 31 shows the
LED Open Detection timing.
BLANK
65,534 65,536
65,533 65,535
1
2
3
4
30 31 32 33 34 35
1
2
3
30 31 32 33 34 35
GSCLK
1st GSCLK Period
OUTn is turned off by Auto Off
function if LOD error is detected
OFF
OUTn
(Data = FFFFh)
ON
VOUTn
If no LOD error is detected
GND
If the OUTn voltage (VOUT) is less than VLOD (0.3 V, typ) at the rising edge of the 33rd
GSCLK after the falling edge of BLANK, the LOD sets the SID bit corresponding
to the output channel in which LED is open or shorted to GND equal to ‘1.
SID Register Value
(Internal)
Old LED open detection data
New LED open detection data
This LED Open Detection (LOD) data are
kept until the next 33rd rising edge of
GSCLK after BLANK goes low.
If no LOD error is detected
'Hi-Z’
Depends on LOD data
Depends on previous
XERR
Low
('L')
If LOD error is detected
LOD data
Figure 31. LED Open Detection (LOD) Timing
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Auto Output Off
If the active OUTn channel is not connected to an LED or if LED is shorted to GND, then VCC consumption
current increases. In order to avoid this event, the device has an auto output off function. This function turns off
channel OUTn with a detected LED opening or LED shorting to GND at the 33rd GSCLK after BLANK goes low
automatically. VCC current can be saved by this function. OUTn is controlled normally again after BLANK goes
low. Figure 32 illustrates the auto output off function.
VCC
Dissipation
Current
BLANK
65,534 65,536
65,533 65,535
1
2
3
4
30 31 32 33 34 35
1
2
3
30 31 32 33 34 35
GSCLK
OFF
If LOD error is detected
Voltage of
OUTn
ON
VOUTn
If no LOD error is detected
GND
SID Register Value
(Internal)
Old LED open detection data
New LED open detection data
Remain 'On' (if no
Remain 'On'
LOD error detected)
(if no LOD error detected)
'ON'
'ON'
ON Signal of OUTn
(Internal)
'OFF'
'OFF'
(GS data = FFFFh)
Turn 'Off' (OUTn is turned off
by Auto Off function if LOD error
is detected)
Turn 'Off' (OUTn is turned off
by Auto Off function if LOD error
is detected)
Figure 32. Auto Output Off Function
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Thermal Shutdown and Thermal Error Flag
The Thermal Shutdown (TSD) function turns off all of the constant current outputs on the IC immediately when
the junction temperature (TJ) exceeds the threshold (T(TEF) = +162°C, typ) and sets the thermal error flag (TEF)
to '1'. The XERR pin goes low at the same time. The XERR pin level and the TEF level are kept until the first
SCLK falling edge after an XLAT falling edge of grayscale data. Then if TJ is still greater than T(TEF), TEF
continues at '1' while XERR remains low. If TJ becomes less than T(TEF) –T(HYS), TEF is set to '0' and XERR
becomes Hi-Z. XERR is not forced to a Hi-Z state while BLANK is high. Therefore, the error type TEF or LOD
can be distinguished from the BLANK signal control. OUTn is turned on at the first GSCLK after the BLANK
falling edge if TJ becomes less than T(TEF) – T(HYS) at the BLANK rising edge.
When the IC powers on, TEF may be set and all output is forced off. Therefore, an XLAT pulse and a BLANK
rising edge should be input once to turn on the output. Figure 33 illustrates the TEF/TSD/XERR timing sequence.
BLANK
XLAT
SCLK
65,534 65,536
1
T
2
3 4
65,533 65,535
1 2 3
GSCLK
IC Junction
< T
(TEF)
T
< T
- T
(HYS)
J
J (TEF)
T
³ T
(TEF)
T ³ T
J (TEF)
J
Temperature (TJ)
'1'
TEF
'0'
'0'
(Internal)
'Hi-Z’
Low
('L')
XERR
OUTn
OFF
OFF
ON
Figure 33. TEF/TSD/XERR timing
POWER DISSIPATION CALCULATION
The device power dissipation must be below the power dissipation rate of the device package (illustrated in
Figure 15) to ensure correct operation. Equation 4 calculates the power dissipation of the device:
BCn
PD = (VCC ´ ICC) + VOUT ´ IMAX ´ N ´
´ dPWM
127d
(4)
Where:
•
•
•
•
•
•
•
VCC = device supply voltage
ICC = device supply current
VOUT = OUTn voltage when driving LED current
IMAX = LED current adjusted by R(IREF) resistor
BCn = maximum BC value for OUTn
N = number of OUTn driving LED at the same time
dPWM = duty ratio defined by BLANK pin or GS PWM value
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Dec-2007
PACKAGING INFORMATION
Orderable Device
TLC5943PWP
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
HTSSOP
PWP
28
50 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TLC5943PWPR
HTSSOP
PWP
28
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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Addendum-Page 1
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
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