TLC5955RTQT [TI]
具有点校正、亮度控制和开路/短路检测功能的 48 通道、16 位 PWM LED 驱动器 | RTQ | 56 | -40 to 85;
| 型号： | TLC5955RTQT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有点校正、亮度控制和开路/短路检测功能的 48 通道、16 位 PWM LED 驱动器 | RTQ | 56 | -40 to 85 驱动 驱动器 |
| 文件： | 总54页 (文件大小：1890K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLC5955
ZHCSC51 –MARCH 2014
TLC5955 48 通道，16 位，脉宽调制 (PWM) 发光二极管 (LED) 驱动器，
具有 DC，BC，LED 开路-短路检测和内部电流设置功能
1 特性
3 说明
1
•
•
48 个恒定灌电流输出通道
支持最大 MC，DC 和 BC 数据的灌电流能力：
TLC5955 是一款 48 通道，恒定灌电流驱动器。 每个
通道具有一个独立可调节，脉宽调制 (PWM)，灰度
(GS) 亮度控制，此控制有 65,536 步长和 128 步长的
恒定电流点校正 (DC)。 DC 可调节通道间的亮度偏
差。 所有通道具有一个 128 步长的全局亮度控制
(BC)。 BC 调节 R，G，B 色彩组之间的亮度偏差。 8
步长最大电流控制 (MC) 为每个色彩组的所有通道选择
最大输出电流范围。 可通过一个串行接口端口来访问
GS，DC，BC 和 MC 数据。
–
–
23.9mA (VCC ≤ 3.6V，MC = 5)
31.9mA (VCC > 3.6V, MC = 7)
•
•
灰度 (GS) 控制：
–
支持增强型频谱或传统 PWM 的 16 位（65536
个步长）
最大电流 (MC) 控制：
–
–
电流范围为 3mA 至 30mA 的 3 位（8 个步长）
针对每个色彩组的 3 MC 设置
TLC5955 具有两个错误标志：LED 开路检测 (LOD) 和
LED 短路检测 (LSD)。 可使用一个串行接口端口来读
取错误检测结果。
•
•
点校正 (DC) 控制：
–
范围在 26.2% 至 100% 之间的 7 位（128 个步
长）
全局亮度控制 (BC)：
器件信息
订货编号
封装
封装尺寸
–
–
10% 至 100% 范围内的 7 位（128 个步长）
针对每个色彩组的 3 BC 设置
带散热片薄型小外形
尺寸封装 (HTSSOP) 14.0mm x 6.1mm
TLC5955DCA
•
•
•
LED 电源电压：高达 10V
VCC：3.0V 至 5.5V
恒定电流精度：
(56)
四方扁平无引线
8.0mm x 8.0mm
(QFN) (56)
TLC5955RTQ
–
–
通道到通道：±2%（典型值），±5%（最大值）
器件到器件：±2%（典型值），±4%（最大值）
•
•
•
•
•
•
•
•
•
•
数据传输速率：25MHz
灰度控制时钟：33MHz
自动重复显示功能
应用电路
显示定时复位
VLED
自动数据刷新（只适用于 GS 和 DC）
LED 开路检测 (LOD)
+
x48
LED 短路检测 (LSD)
欠压闭锁 (UVLO) 设定缺省数据
延迟开关以防止涌入电流
工作温度范围：-40°C 至 +85°C
GND
OUTR0
OUTB15
SOUT
Input Serial Data
Shift Clock
Output Serial Data
SIN
VCC
SCLK
LAT
VCC
TLC5955
Data Latch
2 应用范围
GS Clock
GSCLK
GND
GND
•
•
•
LED 视频显示屏
可变消息标志 (VMS)
照明
GND
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBVS237
TLC5955
ZHCSC51 –MARCH 2014
www.ti.com.cn
目录
8.1 Overview ................................................................. 15
8.2 Functional Block Diagram ....................................... 16
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 28
Applications and Implementation ...................... 38
9.1 Application Information............................................ 38
9.2 Typical Application .................................................. 38
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Terminal Configurations and Functions.............. 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ..................................... 6
6.2 Handling Ratings....................................................... 6
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 8
6.6 Switching Characteristics.......................................... 9
6.7 Typical Characteristics............................................ 10
Parameter Measurement Information ................ 12
9
10 Power Supply Recommendations ..................... 41
11 Layout................................................................... 41
11.1 Layout Guidelines ................................................. 41
11.2 Layout Example .................................................... 42
12 器件和文档支持 ..................................................... 43
12.1 器件支持................................................................ 43
12.2 文档支持................................................................ 43
12.3 Trademarks........................................................... 43
12.4 Electrostatic Discharge Caution............................ 43
12.5 Glossary................................................................ 43
13 机械封装和可订购信息 .......................................... 43
7
8
7.1 Terminal-Equivalent Input and Output Schematic
Diagrams.................................................................. 12
7.2 Test Circuits ............................................................ 12
7.3 Timing Diagrams..................................................... 13
Detailed Description ............................................ 15
4 修订历史记录
日期
修订版本
注释
2014 年 3 月
*
最初发布。
2
Copyright © 2014, Texas Instruments Incorporated
TLC5955
www.ti.com.cn
ZHCSC51 –MARCH 2014
5 Terminal Configurations and Functions
DCA Package
HTSSOP-56
(Top View)
SIN
SCLK
1
2
3
4
5
6
7
8
9
56 GND
55 GSCLK
54 VCC
LAT
OUTB4
OUTR4
OUTG4
OUTB0
OUTR0
OUTG0
53 OUTB8
52 OUTR8
51 OUTG8
50 OUTB12
49 OUTR12
48 OUTG12
47 OUTB9
46 OUTR9
45 OUTG9
44 OUTB13
43 OUTR13
42 OUTG13
41 OUTB14
40 OUTR14
39 OUTG14
38 OUTB10
37 OUTR10
36 OUTG10
35 OUTB15
34 OUTR15
33 OUTG15
32 OUTB11
31 OUTR11
30 OUTG11
29 GND
OUTB5 10
OUTR5 11
OUTG5 12
OUTB1 13
OUTR1 14
OUTG1 15
OUTB2 16
OUTR2 17
OUTG2 18
OUTB6 19
OUTR6 20
OUTG6 21
OUTB3 22
OUTR3 23
OUTG3 24
OUTB7 25
OUTR7 26
OUTG7 27
SOUT 28
Thermal Pad
(Solder Side)
Copyright © 2014, Texas Instruments Incorporated
3
TLC5955
ZHCSC51 –MARCH 2014
www.ti.com.cn
RTQ Package
QFN-56
(Top View)
OUTB0
OUTG4
OUTR4
OUTB4
LAT
OUTB3
OUTR3
OUTG3
OUTB7
OUTR7
OUTG7
SOUT
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
3
4
5
SCLK
6
SIN
7
Thermal Pad
(Solder Side)
GND
GND
8
GSCLK
VCC
OUTG11
OUTR11
OUTB11
OUTG15
OUTR15
OUTB15
9
10
11
12
13
14
OUTB8
OUTR8
OUTG8
OUTB12
4
Copyright © 2014, Texas Instruments Incorporated
TLC5955
www.ti.com.cn
ZHCSC51 –MARCH 2014
Terminal Functions
TERMINAL
DCA NUMBER
29, 56
NAME
RTQ NUMBER
I/O
DESCRIPTION
GND
8, 35
—
Power ground
Reference clock for the grayscale (GS) pulse width modulation (PWM) control for all outputs.
Each GSCLK rising edge increments the grayscale counter for PWM control. When the LAT
signal is input for a GS data write with the timing reset mode enabled, all constant-current
outputs (OUTX0-OUTX15, where X = R, G, or B) are forced off, the grayscale counter is
reset to 0, and the grayscale PWM timing controller is initialized.
GSCLK
LAT
55
3
34
38
I
I
The LAT rising edge either latches the data from the common shift register into the GS data
latch when the MSB of the common shift register is 0 or latches the data into the control
data latch when the MSB of the common shift register is 1. When the display timing reset bit
(TMGRST) in the control data latch is 1, the grayscale counter initialized at the LAT signal is
input for a grayscale data write. Dot correction (DC) data in the control data latch are copied
to DC data latch at the same time.
4, 7, 10, 13, 16, 19, 1, 4, 11, 14, 17, 20,
Constant-current outputs for the blue color group.
Multiple outputs can be configured in parallel to increase the constant-current capability.
Different voltages can be applied to each output.
OUTB0 to
OUTB15
22, 25, 32, 35, 38,
41, 44, 47, 50, 53
23, 26, 29, 32, 39,
42, 45, 48, 51, 54
O
O
O
6, 9, 12, 15, 18, 21,
24, 27, 30, 33, 36,
39, 42, 45, 48, 51
3, 6, 9, 12, 15, 18,
21, 24, 27, 30, 41,
44, 47, 50, 53, 56
Constant-current outputs for the green color group.
Multiple outputs can be configured in parallel to increase the constant-current capability.
Different voltages can be applied to each output.
OUTG0 to
OUTG15
5, 8, 11, 14, 17, 20, 2, 5, 10, 13, 16, 19,
Constant-current outputs for the red color group.
Multiple outputs can be configured in parallel to increase the constant-current capability.
Different voltages can be applied to each output.
OUTR0 to
OUTR15
23, 26, 31, 34, 37,
40, 43, 46, 49, 52
22, 25, 28, 31, 40,
43, 46, 49, 52, 55
Serial data shift clock.
Data present on SIN are shifted to the LSB of the common shift register with the SCLK
rising edge. Data in the shift register are shifted toward the MSB at each SCLK rising edge.
The MSB data of the common shift register appears on SOUT.
SCLK
SIN
2
1
37
36
I
I
Serial data input for the 769-bit common shift register.
This bit is the serial data output of the 769-bit common shift register.
LED open detection (LOD) and LED short detection (LSD) can be read out with SOUT in the
form of status information data (SID) after the LAT falling edge is input for a GS data write.
SOUT is connected to the MSB of the 769-bit common shift register. Data are clocked out at
the SCLK rising edge.
SOUT
28
54
7
O
VCC
33
—
—
Power-supply voltage
The thermal pad is not connected to GND internally.
The thermal pad must be connected to GND via the PCB.
Thermal pad
Copyright © 2014, Texas Instruments Incorporated
5
TLC5955
ZHCSC51 –MARCH 2014
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)
Over operating free-air temperature range, unless otherwise noted.
MIN
–0.3
–0.3
–0.3
MAX
UNIT
VCC
VIN
Supply
+6.0
VCC + 0.3
VCC + 0.3
V
V
V
Input range
SIN, SCLK, LAT, GSCLK
SOUT
Voltage(2)
VOUT
Output range
OUTR0 to OUTR15, OUTG0 to
OUTG15, OUTB0 to OUTB15
–0.3
+11
V
TJ (max)
Maximum operating junction temperature
+150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to device ground terminal.
6.2 Handling Ratings
MIN
MAX
+150
4000
2000
UNIT
°C
V
TSTG
Storage temperature range
–55
Human body model (HBM) ESD stress voltage(2)
Charged device model (CDM) ESD stress voltage(3)
(1)
VESD
V
(1) Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
(2) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 4000-V HBM allows
safe manufacturing with a standard ESD control process.
(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 2000-V CDM allows safe
manufacturing with a standard ESD control process.
6
Copyright © 2014, Texas Instruments Incorporated
TLC5955
www.ti.com.cn
ZHCSC51 –MARCH 2014
6.3 Recommended Operating Conditions
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
DC CHARACTERISTICS
VCC
VO
Supply voltage
3.0
5.5
10
V
V
Voltage applied to output
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
OUTX0 to OUTX15(1)
VIH
VIL
IOH
IOL
SIN, SCLK, LAT, GSCLK
SIN, SCLK, LAT, GSCLK
SOUT
0.7 × VCC
GND
VCC
V
0.3 × VCC
–2
V
mA
mA
mA
mA
SOUT
2
OUTX0 to OUTX15(1), 3 V ≤ VCC ≤ 3.6 V
OUTX0 to OUTX15(1), 3.6 V < VCC ≤ 5.5 V
23.9
31.9
IOLC
Constant output sink current
Operating free-air temperature
range
TA
TJ
–40
–40
+85
°C
°C
Operating junction temperature
range
+125
AC CHARACTERISTICS
fCLK (SCLK)
Data shift clock frequency
SCLK
25
33
MHz
MHz
ns
fCLK (GSCLK) Grayscale control clock frequency
GSCLK
tWH0
tWL0
SCLK
10
10
10
10
30
5
SCLK
ns
tWH1
tWL1
tWH2
tSU0
Pulse duration
GSCLK
ns
GSCLK
ns
LAT
ns
SIN to SCLK↑
ns
LAT↓ to SCLK↑ (auto data refresh is
tSU1
tSU2
tSU3
30
50
70
ns
ns
ns
disabled(2)
)
Setup time
Hold time
LAT↑ for GS data written to GSCLK↑ when
display time reset mode is disabled
LAT↑ for GS data written to GSCLK↑ when
display time reset mode is enabled
tH0
tH1
(1) X = R, G, or B.
SCLK↑ to SIN
2
5
ns
ns
SCLK↑ to LAT↑
(2) When auto data refresh is enabled, the first SCLK rising edge after the LAT signal input must be input after the first GSCLK is input.
6.4 Thermal Information
DCA (HTSSOP)
RTQ (QFN)
THERMAL METRIC(1)
UNIT
56 TERMINALS 56 TERMINALS
θJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
32.2
16.8
16.1
0.8
27.9
14.9
6.5
θJCtop
θJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
16.0
0.9
6.4
θJCbot
2.0
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2014, Texas Instruments Incorporated
7
TLC5955
ZHCSC51 –MARCH 2014
www.ti.com.cn
6.5 Electrical Characteristics
At TA = –40°C to +85°C and VCC = 3 V to 5.5 V, unless otherwise noted. Typical values at TA = +25°C and VCC = 3.3 V.
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
High-level output voltage
(SOUT)
VOH
VOL
IIN
IOH = –2 mA
VCC – 0.4
VCC
V
Low-level output voltage
(SOUT)
IOL = 2 mA
0.4
1
V
Input current
(SIN, SCLK, LAT, GSCLK)
VIN = VCC or GND
–1
μA
SIN, SCLK, and LAT = GND, all OUTXn = off,
GSCLK = GND, GSXn = 0000h, DCXn and BCX = 7Fh,
VOUTXn = 0.8 V, MCX = 0 (3.2-mA target)(1)(2)
ICC0
ICC1
ICC2
15
16
18
20
22
26
mA
mA
mA
SIN, SCLK, and LAT = GND, all OUTXn = off,
GSCLK = GND, GSXn = 0000h, DCXn and BCX = 7Fh,
VOUTXn = 0.8 V, MCX = 4 (19.1-mA target)
Supply current (VCC
)
SIN, SCLK, and LAT = GND, auto display repeat
enabled, GSCLK = 33 MHz, GSXn = FFFFh, DCXn and
BCX = 7Fh, VOUTXn = 0.8 V, MCX = 4 (19.1-mA target)
VCC = 5.0 V, SIN, SCLK, and LAT = GND, auto display
repeat enabled, GSCLK = 33 MHz, GSXn = FFFFh,
DCXn and BCX = 7Fh, VOUTXn = 0.8 V, MCX = 7
(31.9-mA target)
ICC3
20
29
mA
All OUTXn = on, DCXn and BCX = 7Fh,
VOUTXn = VOUTfix = 0.8 V, MCX = 4
IOLC0
IOLC1
17.4
29.1
19.1
31.9
20.8
34.7
mA
mA
Constant output sink current
(OUTX0 to OUTX15)
VCC = 5.0 V, all OUTXn = on, DCXn and BCX = 7Fh,
VOUTXn = VOUTfix = 0.8 V, MCX = 7
IOLKG0
IOLKG1
IOLKG2
TJ = +25°C
0.1
0.2
0.8
μA
μA
μA
All OUTn = off,
VOUTXn = VOUTfix = 10 V,
MCX = 7
Output leakage current
(OUTX0 to OUTX15)
TJ = +85°C
TJ = +125°C
0.3
Constant-current error
(channel-to-channel, OUTX0 to
OUTX15)(3)
All OUTXn = on, DCXn and BCX = 7Fh,
VOUTXn = VOUTfix = 0.8 V, MCX = 4
ΔIOLC0
ΔIOLC1
ΔIOLC2
±2%
±5%
±4%
±1
Constant-current error
(device-to-device, OUTX0 to
OUTX15)(4)
All OUTXn = on, DCXn and BCX = 7Fh,
VOUTXn = VOUTfix = 0.8 V, MCX = 4
±2%
±0.1
VCC = 3.0 V to 5.5 V, all OUTXn = on,
DCXn and BCX = 7Fh, VOUTXn = VOUTfix = 0.8 V,
MCX = 4
Line regulation
%/V
(OUTx0 to OUTx15)(5)
(1) X = R, G, or B. For example, MCX = MCR, MCG, and MCG.
(2) n = 0 to 15.
(3) The deviation of each output from the OUTX0 to OUTX15 constant-current average of the same color group. Deviation is calculated by
the formula:
IOLCXn
- 1
(IOLCX0 + IOLCX1 + ... + IOLCX14 + IOLCX15
)
D (%) =
´ 100
16
where X = R, G, or B; n = 0 to 15.
(4) Deviation of the OUTX0 to OUTX15 constant-current average from the ideal constant-current value.
Deviation is calculated by the formula:
(IOLCX0 + IOLCX1 + ... IOLCX14 + IOLCX15
)
- (Ideal Output Current)
D (%) =
´ 100
16
Ideal Output Current
where X = R, G, or B; n = 0 to 15.
Ideal current is the target current when MC is 4.
(5) Line regulation is calculated by the formula:
(IOLCXn at VCC = 5.5 V) - (IOLCXn at VCC = 3.0 V)
100
D (%/V) =
´
(IOLCXn at VCC = 3.0 V)
5.5 V - 3.0 V
where X = R, G, or B; n = 0 to 15.
8
Copyright © 2014, Texas Instruments Incorporated
TLC5955
www.ti.com.cn
ZHCSC51 –MARCH 2014
Electrical Characteristics (continued)
At TA = –40°C to +85°C and VCC = 3 V to 5.5 V, unless otherwise noted. Typical values at TA = +25°C and VCC = 3.3 V.
PARAMETER
CONDITION
MIN
TYP
±0.1
0.30
MAX
UNIT
Load regulation
All OUTXn = on, DCXn and BCX = 7Fh,
VOUTXn = 0.8 V to 3.0 V, VOUTfix = 0.8 V, MCX = 4
ΔIOLC3
±1
%/V
(OUTx0 to OUTx15)(6)
VLOD
VLSD0
VLSD1
LED open-detection threshold
All OUTXn = on
0.25
0.35
V
V
V
All OUTXn = on, LSDVLT = 0
All OUTXn = on, LSDVLT = 1
0.65 × VCC 0.70 × VCC 0.75 × VCC
0.85 × VCC 0.90 × VCC 0.95 × VCC
LED short-detection threshold
(6) Load regulation is calculated by the equation:
(IOLCXn at VOUTXn = 3 V) - (IOLCXn at VOUTXn = 0.8 V)
D (%/V) =
100
´
IOLCXn at VOUTXn = 0.8 V
3 V - 0.8 V
where X = R, G, or B; n = 0 to 15.
6.6 Switching Characteristics
At TA = –40°C to +85°C, VCC = 3 V to 5.5 V, CL = 15 pF, RL = 120 Ω, MCX = 7, and VLED = 4.5 V, unless otherwise noted.
Typical values at TA = +25°C and VCC = 3.3 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
3
MAX
UNIT
ns
tR0
tR1
tF0
tF1
tD0
SOUT
5
Rise time
OUTXn, VCC = 3.6 V, DCXn, and BCX = 7Fh, TA = +25°C(1)
30
3
ns
SOUT
5
ns
Fall time
OUTXn, VCC = 3.6 V, DCXn, and BCX = 7Fh, TA = +25°C
SCLK↑ to SOUT↑↓
40
20
ns
30
ns
GSCLK↑ to OUTX4 and
OUTX11 on or off
tD1
40
43
46
49
52
55
58
61
ns
ns
ns
ns
ns
ns
ns
ns
ns
GSCLK↑ to OUTX0 and
OUTX15 on or off
tD2
GSCLK↑ to OUTX5 and
OUTX10 on or off
tD3
GSCLK↑ to OUTX1 and
OUTX14 on or off
tD4
Propagation delay
VCC = 3.6 V, GSCLK = 33 MHz, DCXn
and BCX = 7Fh, TA = +25°C
GSCLK↑ to OUTX2 and
OUTX13 on or off
tD5
GSCLK↑ to OUTX6 and
OUTX9 on or off
tD6
GSCLK↑ to OUTX3 and
OUTX12 on or off
tD7
GSCLK↑ to OUTX7 and
OUTX8 on or off
tD8
tOUTON – tGSCLK, VCC = 3.6 V to 5.5 V, GSXn = 0001h,
GSCLK = 33 MHz, DCXn and BCX = 7Fh
tON_ERR
Output on-time error(2)
–20
20
(1) X = R, G, or B; n = 0 to 15.
(2) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR = tOUT_ON – tGSCLK. tOUTON is the actual on-time of the constant-
current driver. tGSCLK is the GSCLK period.
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6.7 Typical Characteristics
At TA = +25°C and VCC = 5.0 V, unless otherwise noted.
40
40
35
30
25
20
15
10
5
MC = 0
MC = 1
MC = 2
MC = 3
MC = 4
MC = 5
MC = 6
MC = 7
DC = 0h
DC = 10h
DC = 20h
DC = 30h
DC = 40h
DC = 50h
DC = 60h
DC = 70h
DC = 7Fh
35
30
25
20
15
10
5
0
0
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
Output Voltage (V)
2
2.5
3
Output Voltage (V)
C001
C002
BCX = DCXn = 7Fh
BCX = DCXn = 7Fh
Figure 1. Output Current vs Output Voltage
(MCX Changing)
Figure 2. Output Current vs Output Voltage
(DCXn Changing)
35
34
33
32
31
30
29
40
35
30
25
20
15
10
5
BC = 0h
BC = 10h
BC = 20h
BC = 30h
BC = 40h
BC = 50h
BC = 60h
BC = 70h
BC = 7Fh
T=±40C
A
TA = 25C
TA = 85C
0
0
0.2
0.4
0.6
0.8
1
0
0.5
1
1.5
2
2.5
3
Output Voltage (V)
Output Voltage (V)
C004
C003
BCX = DCXn = 7Fh
BCX = DCXn = 7Fh
Figure 4. Output Current vs Output Voltage (Temperature
Changing)
Figure 3. Output Current vs Output Voltage
(BCX Changing)
5
4
5
4
3
3
2
2
1
1
0
0
±1
±2
±3
±4
±5
±1
±2
±3
±4
Max
Min
Max
Min
±5
0
5
10
15
20
25
30
35
0
20
40
60
80
100
±40
±20
Output Current (mA)
Ambient Temperature (C)
BCX = DCXn = 7Fh
C005
C006
BCX = DCXn = 7Fh
VOUTXn = 0.8 V
MCX = 4
VOUTXn = 0.8 V
Figure 5. Constant-Current Error vs Output Current
(Channel-to-Channel in Each Color Group)
Figure 6. Constant-Current Error vs Ambient Temperature
(Channel-to-Channel in Each Color Group)
10
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Typical Characteristics (continued)
At TA = +25°C and VCC = 5.0 V, unless otherwise noted.
35
35
30
25
20
15
10
5
MCX = 0
MCX = 1
MCX = 2
MCX = 3
MCX = 4
MCX = 5
MCX = 6
MCX = 7
MCX = 0
MCX = 1
MCX = 2
MCX = 3
MCX = 4
MCX = 5
MCX = 6
MCX = 7
30
25
20
15
10
5
0
0
0
16
32
48
64
80
96
112
128
0
16
32
48
64
80
96
112
128
DC Data (Decimal)
BC Data (Decimal)
C007
C008
BCX = 7Fh
VOUTXn = 0.8 V
DCXn = 7Fh
VOUTXn = 0.8 V
Figure 7. Dot Correction (DC) Linearity
Figure 8. Global Brightness Control (BC) Linearity
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
VCC = 3.3 V
VCC = 3.3 V
VCC = 5 V
VCC = 5 V
0
0
0
5
10
15
20
25
30
35
0
20
40
60
80
100
±40
±20
Output Current (mA)
SIN = 12.5 MHz
VOUT = 0.8 V
Ambient Temperature (C)
BCX = DCXn = 7Fh
GSCLK = 33 MHz
C009
C010
BCX = DCXn = 7Fh
SCLK = 25 MHz
MCX = 4
SIN = 12.5 MHz
VOUT = 0.8 V
GSCLK = 33 MHz
GSXn = FFFFh
SCLK = 25 MHz
GSXn = FFFFh
Figure 9. Supply Current vs Output Current
Figure 10. Supply Current vs Ambient Temperature
Ch1: GSCLK (5 V/div)
Ch2: OUTR4 (2 V/div)
Ch3: OUTGO (2 V/div)
Ch4: OUTB5 (2 V/div)
Time (20 ns/div)
MCX = 7
BCX = DCXn = 7Fh
RL = 120 Ω
GSCLK = 33 MHz
VLED = 4.5 V
GSXn = 0001h
Figure 11. Constant-Current Output Voltage Waveform
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7 Parameter Measurement Information
7.1 Terminal-Equivalent Input and Output Schematic Diagrams
VCC
VCC
INPUT
SOUT
GND
GND
Figure 12. SIN, SCLK, LAT, GSCLK
Figure 13. SOUT
OUTXn(1)
GND
(1) X = R, G, or B; n = 0 to 15.
Figure 14. OUTX0 Through OUTX15
7.2 Test Circuits
RL
CL
VCC
GND
VCC
VCC
(1)
OUTXn
VLED
(2)
SOUT
GND
VCC
(1)
CL
(1) X = R, G, or B; n = 0 to 15.
(2) CL includes measurement probe and jig capacitance.
(1) CL includes measurement probe and jig capacitance.
Figure 16. Rise Time and Fall Time Test Circuit
for SOUT
Figure 15. Rise Time and Fall Time Test Circuit
for OUTXn
VCC
OUTR0
VCC
(1)
OUTXn
(1)
GND
OUTB15
VOUTXn
VOUTfix
(1) X = R, G, or B; n = 0 to 15.
Figure 17. Constant-Current Test Circuit for OUTXn
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7.3 Timing Diagrams
tWH0, tWL0, tWH1, tWL1, tWH2
:
VCC
Input(1)
50%
GND
tWH
tWL
tSU0, tSU1, tSU2, tSU3, tH0, tH1
:
VCC
Clock Input(1)
50%
GND
VCC
tSU
tH
Data and Control Input(1)
50%
GND
(1) Input pulse rise and fall time is 1 ns to 3 ns.
Figure 18. Input Timing
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5, tD6, tD7, tD8
:
VCC
Input(1)
50%
GND
tD
(2)
VOH or VOUTXnH
90%
50%
10%
Output
(2)
VOL or VOUTXnL
tR or tF
(1) Input pulse rise and fall time is 1 ns to 3 ns.
(2) X = R, G, or B; n = 0 to 15.
Figure 19. Output Timing
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Timing Diagrams (continued)
GS Data Write
GS Data Write
R0
0A
B15
15B
B15
14B
B15
13B
B15
12B
R0
3B
R0
2B
R0
1B
R0
0B
B15
15C
B15
14C
B15
13C
B15
12C
B15
11C
B15
10C
SIN
SCLK
GSCLK
LAT
Low
Low
tSU1
tH0
tH1
tSU0
tWH0
1
2
3
4
5
766 767 768 769
1
2
3
4
5
tWH1
6
7
tWL0
tGSCLK
65534
65536
65538
1
2
3
4
5
6
65535
65537
tWH2
tWL1
tSU2, tSU3
Grayscale Data
In GS Data Latch
(Internal)
New Data
Old Data
tD0
LOD
B15
LOD
G15
LOD
R15
LOD
B14
R0
3A
R0
2A
R0
1A
R0
0A
LOD
B15
LOD
G15
LOD
R15
LOD
B14
LOD
G14
LOD
R14
LOD
B13
SOUT
Low
Low
tR0, tF0
Display Timing Reset Enabled, Auto Display Repeat Disabled, All GS Data Are FFFFh
tR1
tF1
(VOUTXnH
)
OUTR4, OUTR11,
OUTG4, OUTG11,
OUTB4, OUTB11
Off
(VOUTXnL
)
On
tD1
OUTR0, OUTR15,
OUTG0, OUTG15,
OUTB0, OUTB15
Off
On
tD2
OUTR5, OUTR10,
OUTG5, OUTG10,
OUTB5, OUTB10
Off
On
tD3
OUTR1, OUTR14,
OUTG1, OUTG14,
OUTB1, OUTB14
Off
On
tD4
OUTR2, OUTR13,
OUTG2, OUTG13,
OUTB2, OUTB13
Off
On
tD5
OUTR6, OUTR9,
OUTG6, OUTG9,
OUTB6, OUTB9
Off
On
tD6
OUTR3, OUTR12,
OUTG3, OUTG12,
OUTB3, OUTB12
Off
On
tD7
OUTR7, OUTR8,
OUTG7, OUTG8,
OUTB7, OUTB8
Off
On
tD8
Figure 20. Data Input, Output, and Constant Output Timing
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8 Detailed Description
8.1 Overview
The TLC5955 is 48-channel, 30-mA, constant-current LED driver that can control LED on-time with pulse width
modulation (PWM) in 65,536 steps for grayscale (GS) control. A maximum of 281 trillion colors can be generated
with red, green, and blue LEDs connected to the constant-current outputs.
The device has a 128-step, 7-bit, output current control function called dot correction (DC) that can control each
constant-current output. Inherently, LED lamps have different intensities resulting from manufacturing differences.
The DC function can reduce the inherent differences in intensity and improve LED lamp brightness uniformity.
The device also has a 128-step, 7-bit, output current control function called global brightness control (BC) that
can control each color group output. The BC function can adjust the red, green, and blue LED intensity for true
white with constant-current control. The device contributes higher image quality to LED displays with fine white
balance tuning by using these GS, DC, and BC functions.
The display controller can locate LED lamp failures via the device because the controller can detect LED lamp
failures with the LED open detection (LOD) and LED short detection (LSD) functions and the reliability of the
display can be improved by the LOD, LSD function.
The device maximum constant-current output value can be set by internal register data instead of the general
method of using an external resistor setting. Thus, any failure modes that occur from the external resistor can be
eliminated and one resistor can be eliminated.
The device constant-current output can drive approximately 19 mA at a 0.25-V output voltage and a +25°C
ambient temperature. This voltage is called knee voltage. This 0.25-V, low-knee voltage can contribute to the
design of a lower-power display system. The total number of LED drivers on one LED display panel can be
reduced because 48 LED lamps can be driven by one LED driver. Therefore, designing fine-pitch LED displays is
simplified.
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8.2 Functional Block Diagram
LSB
MSB
lodisdlat
96-Bit LOD, LSD Data Latch
VCC
0
95
96
LSB
MSB
SIN
769-Bit Common Shift Register
SOUT
0
Bit 768
768
SCLK
latgs
768
LSB
MSB
768-Bit Grayscale (GS) Data Latch
0
767
379
371
8
MSB
LSB
8-Bit Write
Command
Decoder
371-Bit Control Data Latch
(DC, MC, BC, FC)
LAT
0
370
336
336-Bit DC Data Latch
MC, BC, FC Bits
UVLO
768
LSB
MSB
335
35
1
lodisdlat
latgs
0
3
16-Bit GS
Counter
48-Channel,
16-Bit ES, Conventional PWM Timing
GSCLK
336
48
8-Set, 6-Channel Grouped
Switching Delay
30
48
Reference
Current Control
with 3-Bit MC and
7-Bit BC for Each
Color
48-Channel Constant Sink Current Driver
with 7-Bit DC
1
LED Open Detection (LOD)
LED Short Detection (LSD)
96
GND
OUTR0 OUTG0 OUTB0
OUTR15 OUTG15 OUTB15
16
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8.3 Feature Description
8.3.1 Output Current Calculation
The output current value controlled by MC, DC, and BC can be calculated by Equation 1.
DCXn
127
BCX
127
IOUTn (mA) = IOLCMax (mA) ´
0.262 + 0.738 ´
´ 0.10 + 0.90 ´
where:
•
•
•
•
•
IOLCMax = the maximum constant-current value for all OUTXn for each color group programmed by MC data,
DCXn = the dot correction value for each channel (0h to 7Fh),
BCX = the global brightness control value (0h to 7Fh),
X = R, G, or B for the red, green, or blue color group, and
n = 0 to 15.
(1)
Each output sinks the IOLCMax current when they turn on and the dot correction (DC) data and the global
brightness control (BC) data are set to the maximum value of 7Fh (127d). Each output sink current can be
reduced by lowering the DC and BC values.
When IOUT is set lower than 1 mA by both MC and BC or BC only, the output may be unstable. Output currents
lower than 1 mA can be achieved by setting IOUT to 1 mA with MC and BC or BC only and then using DC to
lower the output current.
8.3.2 Register and Data Latch Configuration
The TLC5955 has one common shift register and three data latches: the grayscale (GS) data latch, the control
data latch, and the dot correction (DC) data latch. The common shift register is 769 bits long, the GS data latch is
768 bits long, the control data latch is 371 bits long, and the DC data latch is 336 bits long.
If the common shift register MSB is 0, the least significant 768 bits from the common shift register are latched
into the GS data latch. If the MSB is 1, and bits 767 to 760 are 96h (10010110b), the data are latched into the
control data latch. Refer to Figure 21 for the common shift register, GS data latch, control data latch, and DC
data latch configurations.
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Feature Description (continued)
Common Shift Register (769 Bits)
MSB
LSB
Latch
Select
Bit
Common Common Common Common
Data Bit Data Bit Data Bit
Common Common Common Common Common
Data Bit
5
Common
Data Bit
763
Common
Data Bit
0
SIN
SOUT
Data Bit
764
Data Bit Data Bit Data Bit Data Bit
3
767
766
765
4
2
1
SCLK
768
767
766
765
764
763
3
2
1
0
5
4
Lower 768 Bits
Bits 767:0
768 Bits
32
Grayscale (GS) Data Latch (768 Bits)
MSB
The latch pulse
comes from LAT
when the MSB of
the common shift
register is 0 and the
RFRESH bit is 0.
When the REFRESH
bit is 1, the latch
pulse is input at the
65536th GS clock
after the LAT input.
LSB
0
16
15
48
47
31
752
767
OUTR0
Bit 15
OUTB0
Bit 15
OUTG0
Bit 15
OUTR0
Bit 0
OUTB15
Bit 15
OUTR1
Bit 0
OUTB0
Bit 0
OUTG0
Bit 0
OUTB15
Bit 0
GS data for OUTG0
GS data for OUTR0
GS data for OUTB15
GS data for OUTB0
768 Bits
To Grayscale Timing Control Circuit
Bits 335:0
Bits 344:336
9–Bit
Previous
MC data
RESET
from
UVLO
Bits Bits
341:339 338:336
Bits
344:342
Bits 370:345
LatMC
Control Data
Latch (371 Bits)
Bits 767:760
MSB
767 --- 760
8-Bit Command
LSB
LSB
6:0
MSB - 366
370:366
338:336
341:339
335:329 328:322
358:352 351:345
BRIGHT BRIGHT
344:342
Max
Bits 6:0, Bits 6:0, Current
365:359
DOTCOR DOTCOR
Bits 6:0, Bits 6:0,
OUTB15 OUTG15
DOTCOR
Bits 6:0,
OUTR0
Max
Current
OUTGn
Max
Current
OUTRn
BRIGHT
Bits 6:0,
OUTBn
FUNC
Bits 4:0
Decoder
LAT
(96h)
OUTGn
OUTRn
OUTBn
FC, 5 Bits
BC, 21 Bits
MC, 9 Bits
DC, 336 Bits
336 Bits
LSB
6:0
335:322
335:329
DOTCOR DOTCOR
Bits 6:0, Bits 6:0,
OUTB15 OUTG15
DOTCOR
Bits 6:0,
OUTR0
DC, 336 Bits
DC Data Latch (336 Bits)
The latch pulse
comes from LAT
when the MSB of
the common shift
register is 1.
5 Bits
To Control Logic
21 Bits
To BC Circuit
9 Bits
336 Bits
To Dot Correction Circuit
To Output Current
Reference Circuit
Figure 21. Common Shift Register and Data Latches Configuration
8.3.2.1 769-Bit Common Shift Register
The 769-bit common shift register is used to shift data from the SIN terminal into the TLC5955. The data shifted
into the register are used for GS, DC, maximum output current, global BC functions, and function control data
write operations. The common shift register LSB is connected to SIN and the MSB is connected to SOUT. On
each SCLK rising edge, the data on SIN are shifted into the LSB and all 769 bits are shifted towards the MSB.
The register MSB is always connected to SOUT. When the device is powered up, the data in the 769-bit
common shift register are random.
18
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Feature Description (continued)
8.3.2.2 Grayscale (GS) Data Latch
The GS data latch is 768 bits long, and sets the PWM timing for each constant-current output. The on-time of all
constant-current outputs is controlled by the data in this data latch. The 768-bit GS data in the common shift
register are copied to the data latch at a LAT rising edge when the common shift resister MSB is 0.
When the device is powered up, the data are random and all constant-current outputs are forced off. However,
no outputs turn on until GS data are written to the GS data latch even if a GSCLK is input. The data bit
assignment is shown in Table 1. Refer to Figure 22 for a GS data write timing diagram.
Table 1. Grayscale Data Latch Bit Description
GS DATA
LATCH BIT
NUMBER
GS DATA
LATCH BIT
NUMBER
CONTROLLED
CHANNEL
CONTROLLED
CHANNEL
DEFAULT
VALUE
DEFAULT
VALUE
BIT NAME
GSR0[15:0]
GSG0[15:0]
GSB0[15:0]
GSR1[15:0]
GSG1[15:0]
GSB1[15:0]
GSR2[15:0]
GSG2[15:0]
GSB2[15:0]
GSR3[15:0]
GSG3[15:0]
GSB3[15:0]
GSR4[15:0]
GSG4[15:0]
GSB4[15:0]
GSR5[15:0]
GSG5[15:0]
GSB5[15:0]
GSR6[15:0]
GSG6[15:0]
GSB6[15:0]
GSR7[15:0]
GSG7[15:0]
GSB7[15:0]
BIT NAME
GSR8[15:0]
GSG8[15:0]
GSB8[15:0]
GSR9[15:0]
GSG9[15:0]
GSB9[15:0]
GSR10[15:0]
GSG10[15:0]
GSB10[15:0]
GSR11[15:0]
GSG11[15:0]
GSB11[15:0]
GSR12[15:0]
GSG12[15:0]
GSB12[15:0]
GSR13[15:0]
GSG13[15:0]
GSB13[15:0]
GSR14[15:0]
GSG14[15:0]
GSB14[15:0]
GSR15[15:0]
GSG15[15:0]
GSB15[15:0]
15-0
Bits[15:0] for OUTR0
Bits[15:0] for OUTG0
Bits[15:0] for OUTB0
Bits[15:0] for OUTR1
Bits[15:0] for OUTG1
Bits[15:0] for OUTB1
Bits[15:0] for OUTR2
Bits[15:0] for OUTG2
Bits[15:0] for OUTB2
Bits[15:0] for OUTR3
Bits[15:0] for OUTG3
Bits[15:0] for OUTB3
Bits[15:0] for OUTR4
Bits[15:0] for OUTG4
Bits[15:0] for OUTB4
Bits[15:0] for OUTR5
Bits[15:0] for OUTG5
Bits[15:0] for OUTB5
Bits[15:0] for OUTR6
Bits[15:0] for OUTG6
Bits[15:0] for OUTB6
Bits[15:0] for OUTR7
Bits[15:0] for OUTG7
Bits[15:0] for OUTB7
399-384
415-400
431-416
447-432
463-448
479-464
495-480
511-496
527-512
543-528
559-544
575-560
591-576
607-592
623-608
639-624
655-640
671-656
687-672
703-688
719-704
735-720
751-736
767-752
Bits[15:0] for OUTR8
Bits[15:0] for OUTG8
Bits[15:0] for OUTB8
Bits[15:0] for OUTR9
Bits[15:0] for OUTG9
Bits[15:0] for OUTB9
Bits[15:0] for OUTR10
Bits[15:0] for OUTG10
Bits[15:0] for OUTB10
Bits[15:0] for OUTR11
Bits[15:0] for OUTG11
Bits[15:0] for OUTB11
Bits[15:0] for OUTR12
Bits[15:0] for OUTG12
Bits[15:0] for OUTB12
Bits[15:0] for OUTR13
Bits[15:0] for OUTG13
Bits[15:0] for OUTB13
Bits[15:0] for OUTR14
Bits[15:0] for OUTG14
Bits[15:0] for OUTB14
Bits[15:0] for OUTR15
Bits[15:0] for OUTG15
Bits[15:0] for OUTB15
31-16
47-32
63-48
79-64
95-80
111-96
127-112
143-128
159-144
175-160
191-176
207-192
223-208
239-224
255-240
271-256
287-272
303-288
319-304
335-320
351-336
367-352
383-368
N/A
(no default
value)
N/A
(no default
value)
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B15
14B
R0
3B
R0
2B
R0
1B
B15 B15
12C 11C
B15
15B
B15
13B
R0
0B
B15
15C 14C 13C
B15
B15
R0
0A
Low
Low
SIN
SCLK
LAT
1
2
3
4
1
2
3
4
5
6
766
767 768
769
Common Shift Register LSB
(Internal)
R0
0A
R0
0B
B15
15B
B15
14B
R0
3B
R0
2B
R0
1B
B15
15C
B15
B15
B15
14C 13C 12C
Low
Low
Common Shift Register LSB+1
(Internal)
R0
1B
R0
0A
R0
4B
R0
3B
R0
2B
R0
0B
B15
15C
B15 B15
14C 13C
R0
1A
B15
15B
Low
Low
CommonShift Register MSB–2
(Internal)
LOD
R15
B15
14A
LOD
G15
LOD LOD
B14 G14
B15
15B
LOD LOD LOD LOD LOD
R15A B14A G14A R14A B13A
R0
0A
B15
14B
LOD
G15A
Low
Common Shift Register MSB–1
(Internal)
LOD
B15
B15
15A
LOD
G15
R0
0A
B15
15B
LOD LOD LOD LOD LOD
G15A R15A B14A G14A R14A
LOD LOD
R15 B14
R0
1A
LOD
B15A
Low
Common Shift Register MSB
(Internal)
LOD LOD LOD
R15
R0
2A
R0
1A
R0
0A
LOD LOD LOD LOD LOD
B15A G15A R15A B14A G14A
Low
Low
B15 G15
Grayscale Data Latch
(Internal)
GS Data
GS Data
Control Data Latch
(DC, MC, BC, FC)
(Internal)
DC, MC, BC, FC Data
Control data are not changed.
336-Bit DC Data Latch
(Internal)
Same data are copied from the DC data latch in the control data latch.
DC Data
LOD LOD LOD
R15
R0
2A
R0
1A
R0
0A
LOD LOD LOD LOD LOD
Low
L
SOUT
B15 G15
B15A G15A R15A B14A G14A
Figure 22. Grayscale Data Write Timing Diagram (RFRESH = 0)
8.3.2.3 Control Data Latch
The control data latch is 371 bits long. The data latch contains dot correction (DC) data, maximum current (MC)
data, global brightness control (BC) data, and function control (FC) data. The DC for each constant-current
output are controlled by the data in the DC data latch. The control data in the data latch are updated with the
lower 371 bits of the common shift register at the LAT rising edge when the common shift register MSB is 1. The
336 bits of DC data are copied from the control data latch when the 65,536th GSCLK is input with RFRESH set
to 1 in the control data latch after the GS data are written or the LAT rising edge for GS data writes is input when
the RFRESH bit is 0.
When the device is powered up, the data in the control data latch (except the MC bits) are random. Therefore,
DC, BC, and FC data must be written to the control data latch before turning on the constant-current outputs.
Furthermore, MC data should be set appropriately for the application. Refer to Figure 23 for a control data write
timing diagram.
20
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DCR0
0A
DCR0 DCR0 DCR0 DCR0
3B 2B 1B 0B
L
H
L
H
H
L
H
H
L
H
L
SIN
DC, MC, BC, FC are selected
when the MSB is high.
DC, MC, BC, FC data writes are selected when the MSB[1:9] bits are 96h (HLLHLHHL).
SCLK
1
2
3
4
5
1
2
3
4
5
6
766
767
768
769
LAT
Common Shift Register LSB
(Bit 0, Internal)
DCR0
0A
0
DCR0 DCR
1B
DCR0
0B
DCR0
3B
H
H
H
H
H
L
H
L
L
L
L
L
L
H
2B
Common Shift Register LSB +1
(Bit 1, Internal)
DCR0
0A
DCR0
1A
DCR1
1B
DCR0
4B
DCR0
0B
DCR0 DCR0
3B 2B
H
H
Common Shift Register
(Bit 336, Internal)
DCB0
6A
DCB0 DCB0
3A
4A
MCR
0A
DCB0
5A
DCB0
6B
DCB0
4B
MCR
0B
DCB0
5B
DCB0 DCB0
3B 2B
MCG MCR MCR
2B
0B 1B
Common Shift Register
(Bit 344, Internal)
MCB
2A
MCB
2B
MCB MCB MCG MCB
1A
BCR BCR BCR
1B
MCB MCB MCG MCG MCG
1B
2A
1A
0A
0B
2B
2B
0B
0B
1B
Common Shift Register MSB–1
(Bit 767, Internal)
DCR0 DCR0
1A 0A
H
L
L
L
H
L
H
L
H
H
L
L
L
H
L
L
L
H
H
Common Shift Register MSB
(Bit 768, Internal)
DCR0
0A
DCR0 DCR0
2A 1A
H
H
H
H
GS Data Latch
(Internal)
On and off control data are not changed.
DC data in the data latch are updated when the MSB of the common shift register
is 1 and the write command bit (bits 767 :760) is 96h (10010110b).
DC Data in Control Data Latch
(Internal)
New DC Data
Old DC Data
The 336-bit DC data are not updated at this time. DC data in the control data latch
are copied to the 336-bit DC data latch when the GS data are copied from common
shift register to the GS data latch.
336-Bit DC Data Latch
(Internal)
DC Data are Not Changed
DC Data
MC data are updated when the same data are written twice with the write command
data (96h). MCB2B to MCR0B data must be the same as MCB2A to MCR0A.
The 9-bit MC data (bits 344:336) in the data latch are not updated at this time
because the previous MC data (MCB2A to MCR0A) are written.
MC Data Latch
(Internal)
New MC Data
Old MC Data
BC Data Latch
(Internal)
New BC Data
Old BC Data
BC and FC data in the data latch are updated when the MSB of the common shift
register is 1 and write command bit (bits 767:760) is 96h10010110b.
FC Data Latch
(Internal)
New FC Data
Old FC Data
DCR0 DCR0 DCR0
0
H
L
L
H
L
H
L
L
H
H
SOUT
H
2
1
Figure 23. Control Data Write Timing Diagram for DC, MC, BC, and FC
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8.3.2.4 Dot Correction (DC) Data Latch
DC data are 336 bits long; the data for each constant-current output are controlled by seven bits. Each constant-
current output DC is controlled by the DC data latch. Each DC value individually adjusts the output current for
each constant-current output. As explained in the Dot Correction (DC) Function section, the DC values are used
to adjust the output current from 26.2% to 100% of the current value set by MC and BC data. When the device is
powered on, the data in the DC data latch are random.
The DC data bit assignment is shown in Table 2. See Table 9 for a summary of the DC data value versus set
current value.
Table 2. Dot Correction Data Bit Description
CONTROL
DATA LATCH
BIT NUMBER
CONTROL
DATA LATCH
BIT NUMBER
CONTROLLED
CHANNEL
CONTROLLED
CHANNEL
DEFAULT
VALUE
DEFAULT
VALUE
BIT NAME
DCR0[6:0]
DCG0[6:0]
DCB0[6:0]
DCR1[6:0]
DCG1[6:0]
DCB1[6:0]
DCR2[6:0]
DCG2[6:0]
DCB2[6:0]
DCR3[6:0]
DCG3[6:0]
DCB3[6:0]
DCR4[6:0]
DCG4[6:0]
DCB4[6:0]
DCR5[6:0]
DCG5[6:0]
DCB5[6:0]
DCR6[6:0]
DCG6[6:0]
DCB6[6:0]
DCR7[6:0]
DCG7[6:0]
DCB7[6:0]
BIT NAME
DCR8[6:0]
DCG8[6:0]
DCB8[6:0]
6-0
DC bits[6:0] for OUTR0
DC bits[6:0] for OUTG0
DC bits[6:0] for OUTB0
DC bits[6:0] for OUTR1
DC bits[6:0] for OUTG1
DC bits[6:0] for OUTB1
DC bits[6:0] for OUTR2
DC bits[6:0] for OUTG2
DC bits[6:0] for OUTB2
DC bits[6:0] for OUTR3
DC bits[6:0] for OUTG3
DC bits[6:0] for OUTB3
DC bits[6:0] for OUTR4
DC bits[6:0] for OUTG4
DC bits[6:0] for OUTB4
DC bits[6:0] for OUTR5
DC bits[6:0] for OUTG5
DC bits[6:0] for OUTB5
DC bits[6:0] for OUTR6
DC bits[6:0] for OUTG6
DC bits[6:0] for OUTB6
DC bits[6:0] for OUTR7
DC bits[6:0] for OUTG7
DC bits[6:0] for OUTB7
174-168
181-175
188-182
195-189
202-196
209-203
216-210
223-217
230-224
237-231
244-238
251-245
258-252
265-259
272-266
279-273
286-280
293-287
300-294
307-301
314-308
321-315
328-322
335-329
DC bits[6:0] for OUTR8
DC bits[6:0] for OUTG8
DC bits[6:0] for OUTB8
DC bits[6:0] for OUTR9
DC bits[6:0] for OUTG9
DC bits[6:0] for OUTB9
DC bits[6:0] for OUTR10
DC bits[6:0] for OUTG10
DC bits[6:0] for OUTB10
DC bits[6:0] for OUTR11
DC bits[6:0] for OUTG11
DC bits[6:0] for OUTB11
DC bits[6:0] for OUTR12
DC bits[6:0] for OUTG12
DC bits[6:0] for OUTB12
DC bits[6:0] for OUTR13
DC bits[6:0] for OUTG13
DC bits[6:0] for OUTB13
DC bits[6:0] for OUTR14
DC bits[6:0] for OUTG14
DC bits[6:0] for OUTB14
DC bits[6:0] for OUTR15
DC bits[6:0] for OUTG15
DC bits[6:0] for OUTB15
13-7
20-14
27-21
DCR9[6:0]
DCG9[6:0]
DCB9[6:0]
34-28
41-35
48-42
DCR10[6:0]
DCG10[6:0]
DCB10[6:0]
DCR11[6:0]
DCG11[6:0]
DCB11[6:0]
DCR12[6:0]
DCG12[6:0]
DCB12[6:0]
DCR13[6:0]
DCG13[6:0]
DCB13[6:0]
DCR14[6:0]
DCG14[6:0]
DCB14[6:0]
DCR15[6:0]
DCG15[6:0]
DCB15[6:0]
55-49
62-56
69-63
76-70
N/A
(no default
value)
N/A
(no default
value)
83-77
90-84
97-91
104-98
111-105
118-112
125-119
132-126
139-133
146-140
153-147
160-154
167-161
8.3.2.5 Maximum Current (MC) Data Latch
The maximum output current per channel, IOLCMax, is programmed by MC data and can be set with the serial
interface. IOLCMax is the largest current for each output. Each output sinks the IOLCMax current when they turn on
with DC and BC data set to the maximum value of 7Fh (127d). MC data must have the same data continuously
written twice in order to change the data. When the device is powered on, the MC data are set to 0.
The MC data bit assignment is shown in Table 3. See Table 8 for a summary of the MC data value for each color
group versus the set current value.
Table 3. Maximum Current Data Bit Assignment in the Control Data Latch
CONTROL DATA
LATCH BIT
NUMBER
CONTROLLED CHANNEL
BIT NAME
MCR[2:0]
MCG[2:0]
MCB[2:0]
DEFAULT VALUE
338-336
341-339
344-342
0
0
0
MC bits[2:0] for red color group channels (OUTR0 to OUTR15)
MC bits[2:0] for green color group channels (OUTG0 to OUTG15)
MC bits[2:0] for blue color group channels (OUTB0 to OUTB15)
22
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8.3.2.6 Global Brightness Control (BC) Data Latch
Global BC data are seven bits long. The global brightness for all outputs is controlled by the data in the control
data latch. The data are used to adjust the constant-current values for the 48-channel constant-current outputs.
As explained in the Global Brightness Control (BC) Function section, the BC values are used to adjust the output
current from 10% to 100% of the maximum value. When the device is powered on, the BC data are random.
The global BC data bit assignment in the control data latch is shown in Table 4. See Table 10 for a summary of
the BC data value versus set current value.
Table 4. Global Brightness Control Data Bit Assignment in the Control Data Latch
CONTROL DATA
LATCH BIT
NUMBER
CONTROLLED CHANNEL
BIT NAME
BCR[6:0]
BCG[6:0]
BCB[6:0]
DEFAULT VALUE
351-345
358-352
365-359
BC bits[6:0] for red color group channels (OUTR0 to OUTR15)
N/A (no default value) BC bits[6:0] for green color group channels (OUTG0 to OUTG15)
BC bits[6:0] for blue color group channels (OUTB0 to OUTB15)
8.3.2.7 Function Control (FC) Data Latch
The FC data latch is 5 bits long. This latch enables the auto display repeat and display timing reset functions,
and sets the DC data auto refresh, PWM control mode, and the LSD detection voltage. Each function is selected
by the data in the control data latch. When the device is powered on, the FC data are random. The FC data bit
assignment in the control data latch is shown in Table 5.
Table 5. Function Control Data Latch Bit Description
DEFAULT
BIT
BIT
VALUE
NUMBER
NAME
(Binary)
DESCRIPTION
Auto display repeat mode enable bit
0 = Disabled, 1 = Enabled
366
367
DSPRPT
TMGRST
When this bit is 0, the auto display repeat function is disabled. Each constant-current
output is turned on and off for one display period.
When this bit is 1, each output repeats the PWM control every 65,536 GSCLKs.
Display timing reset mode enable bit
0 = Disabled, 1 = Enabled
When this bit is 0, the GS counter is not reset and the outputs are not forced off even
when a LAT rising edge is input for a GS data write.
When this bit is 1, the GS counter is reset to 0 and all outputs are forced off at the
LAT rising edge for a GS data write. Afterwards, PWM control resumes from the next
GSCLK rising edge.
Auto data refresh mode enable bit
0 = Disabled, 1 = Enabled
When this bit is 0, the auto data refresh function is disabled. The data in the common
shift register are copied to the GS data latch at the next LAT rising edge for a GS
data write. DC data in the control data latch are copied to the DC data latch at the
same time.
When this bit is 1, the auto data refresh function is enabled. The data in the common
shift register are copied to the GS data latch at the 65,536th GSCLK after the LAT
rising edge for a GS data write. DC data in the control data latch are copied to the
DC data latch at the same time.
N/A
(no default
value)
368
RFRESH
ES-PWM mode enable bit
0 = Disabled, 1 = Enabled
When this bit is 0, the conventional PWM control mode is selected. If the TLC5955 is
used for multiplexing a drive, the conventional PWM mode should be selected to
prevent excess on or off switching.
369
370
ESPWM
LSDVLT
When this bit is 1, ES-PWM control mode is selected.
LSD detection voltage selection bit
LED short detection (LSD) detects a fault caused by a shorted LED by comparing the
OUTXn voltage to the LSD detection threshold voltage. The threshold voltage is
selected by this bit.
When this bit is 0, the LSD voltage is VCC × 70%. When this bit is 1, the LSD voltage
is VCC × 90%.
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8.3.3 Status Information Data (SID)
The status information data (SID) contains the status of the LED open detection (LOD) and LED short detection
(LSD). When the MSB of the common shift register is set to 0 and the RFRESH bit in the control data latch is 0,
the SID are loaded to the common shift register at the LAT falling edge after the data in the common shift
register are loaded to the grayscale data latch. If the common shift register MSB is 1, the SID are not loaded to
the common shift register.
When the MSB of the common shift register is set to 0 and the RFRESH bit in the control data latch is 1, the SID
are loaded to the common shift register at the GS counter 0000h just after LAT when the GS data are input. If
the common shift register MSB is 1, the SID are not loaded to the common shift register. When the RFRESH bit
is 1, the SCLK rising edge must be input with a low-level LAT signal after 65,538 GSCLKs (or more) are input
from the LAT rising signal input.
After being loaded into the common shift register, new SID data cannot be loaded until at least one new bit of
data is written into the common shift register. To recheck SID without changing the GS data, reprogram the
common shift register with the same data currently programmed into the GS latch. When LAT goes high, the GS
data do not change, but new SID data are loaded into the common shift register. LOD and LSD are shifted out of
SOUT with each SCLK rising edge. The SID load configuration is shown in Figure 24 and Table 6.
SID are loaded
to the common
shift register at
LOD
Data of
OUTB15
LSD
Data of
OUTR0
LOD
Data of
OUTR0
the LAT falling
edge when the
common shift
LOD
Data of
OUTB0
LOD
Data of
OUTG0
LSD
Data of
OUTB15
LSD
Data of
OUTB0
LSD
Data of
OUTG0
register MSB is 0.
MSB
LSB
Common Common
Data Bit Data Bit
Latch
Select
bit
Common
Data Bit
767
Common Common Common Common
Data Bit Data Bit Data Bit Data Bit
Common
Data Bit
674
Common
Data Bit
673
SIN
SOUT
SCLK
672
671-0
722
721
720
719
Common Shift Register (769 Bits)
Figure 24. SID Load Configuration
24
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Table 6. SID Load Description
COMMON SHIFT REGISTER BIT
NUMBER
COMMON SHIFT REGISTER BIT
LOADED SID
No data loaded
NUMBER
LOADED SID
671-0
672
720
OUTR0 LOD data
OUTR0 LSD data
(0 = No error, 1 = Error)
721
OUTG0 LOD data
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
OUTG0 LSD data
OUTB0 LSD data
OUTR1 LSD data
OUTG1 LSD data
OUTB1 LSD data
OUTR2 LSD data
OUTG2 LSD data
OUTB2 LSD data
OUTR3 LSD data
OUTG3 LSD data
OUTB3 LSD data
OUTR4 LSD data
OUTG4 LSD data
OUTB4 LSD data
OUTR5 LSD data
OUTG5 LSD data
OUTB5 LSD data
OUTR6 LSD data
OUTG6 LSD data
OUTB6 LSD data
OUTR7 LSD data
OUTG7 LSD data
OUTB7 LSD data
OUTR8 LSD data
OUTG8 LSD data
OUTB8 LSD data
OUTR9 LSD data
OUTG9 LSD data
OUTB9 LSD data
OUTR10 LSD data
OUTG10 LSD data
OUTB10 LSD data
OUTR11 LSD data
OUTG11 LSD data
OUTB11 LSD data
OUTR12 LSD data
OUTG12 LSD data
OUTB12 LSD data
OUTR13 LSD data
OUTG13 LSD data
OUTB13 LSD data
OUTR14 LSD data
OUTG14 LSD data
OUTB14 LSD data
OUTR15 LSD data
OUTG15 LSD data
OUTB15 LSD data
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
OUTB0 LOD data
OUTR1 LOD data
OUTG1 LOD data
OUTB1 LOD data
OUTR2 LOD data
OUTG2 LOD data
OUTB2 LOD data
OUTR3 LOD data
OUTG3 LOD data
OUTB3 LOD data
OUTR4 LOD data
OUTG4 LOD data
OUTB4 LOD data
OUTR5 LOD data
OUTG5 LOD data
OUTB5 LOD data
OUTR6 LOD data
OUTG6 LOD data
OUTB6 LOD data
OUTR7 LOD data
OUTG7 LOD data
OUTB7 LOD data
OUTR8 LOD data
OUTG8 LOD data
OUTB8 LOD data
OUTR9 LOD data
OUTG9 LOD data
OUTB9 LOD data
OUTR10 LOD data
OUTG10 LOD data
OUTB10 LOD data
OUTR11 LOD data
OUTG11 LOD data
OUTB11 LOD data
OUTR12 LOD data
OUTG12 LOD data
OUTB12 LOD data
OUTR13 LOD data
OUTG13 LOD data
OUTB13 LOD data
OUTR14 LOD data
OUTG14 LOD data
OUTB14 LOD data
OUTR15 LOD data
OUTG15 LOD data
OUTB15 LOD data
No data loaded
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8.3.4 LED Open Detection (LOD)
LOD detects a fault caused by an LED open circuit or a short from OUTXn to ground with low resistance by
comparing the OUTXn voltage to the LOD detection threshold voltage (0.3 V, typically). If the OUTXn voltage is
lower than the threshold voltage when OUTXn is on, that output LOD bit is set to 1 to indicate an open LED.
Otherwise, the LOD bit is set to 0. LOD data are only valid for outputs that are programmed to be on. LOD data
are latched into the LOD, LSD data latch at the 33rd GSCLK. LOD data for outputs programmed to be off at the
33rd GSCLK are always 0. The LED open detection circuit is shown in Figure 25 and Table 7 lists an LOD truth
table. Refer to Figure 26 for an LOD read timing diagram.
8.3.5 LED Short Detection (LSD)
LSD data detect a fault caused by a shorted LED between LED terminals by comparing the OUTXn voltage to
the LSD detection threshold voltage level set by LSDVLT in the control data latch. If the OUTXn voltage is higher
than the programmed voltage when OUTXn is on, the corresponding output LSD bit is set to 1 to indicate a
shorted LED. Otherwise, the LSD bit is set to 0. LSD data are only valid for outputs that are programmed to be
on. LSD data are latched into the LOD, LSD data latch at the 33rd GSCLK. LSD data for outputs programmed to
be off at the 33rd GSCLK are always 0. The LSD open detection circuit is shown in Figure 25 and Table 7 lists
an LSD truth table. Refer to Figure 26 for an LSD read timing diagram.
VLED
LED Lamp
LSD Data
OUTXn
1 = Error
VLSD
Constant current is set
by MC data.
PWM
Control
LOD Data
1 = Error
VLOD
GND
Figure 25. LOD and LSD Circuit
Table 7. LOD and LSD Truth Table
CONDITION
LSD
SID DATA
LOD
LED is not opened (VOUTXn > VLOD
0
)
LED is not shorted (VOUTXn ≤ VLSD
LED is shorted between anode and cathode, or shorted to
higher voltage side (VOUTXn > VLSD
)
1
LED is open or shorted to GND (VOUTXn ≤ VLOD)
)
26
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65533 65535
65534 65536
1
2
3
4
5
31 32 33 34 35
1
2
3
4
5
GSCLK
Programmed output current
(ON)
OUTXn current
(WhenGSDATA=FFFFh)
0mA (OFF)
Output current set by MC/DC/BC data
0mA (OFF)
LOD/LSD data
aren’t stable just
after OUTXn on.
LOD data is always 0
when OUTXn is off.
48-bit LOD/LSD
Circuit Output Data
(Internal)
XXXXh
XXXXh
XXXXh
0000h
XXXXh
0000h
LOD/LSD data latch is updated at 33rd GSCLK of the display period.
96 Bit LOD/LSD
Data Latch
(Internal)
Old data
XXXXh
XXXXh
LAT signal for
grayscale data writing
LAT
When RFRESH bit is 1, SID is loaded
at 65536th GSCLK and SCLK must be
input after 1st GSCLK input.
769-bit common
Shift Register Data
(Internal)
Grayscale Data
XXXXh is loaded as SID.
Figure 26. LOD and LSD Read and Load Timing Diagram
8.3.6 Noise Reduction
Large surge currents may flow through the device and the board on which the device is mounted if all 48 outputs
turn on simultaneously at the start of each GS cycle. These large current surges can introduce detrimental noise
and electromagnetic interference (EMI) into other circuits. The TLC5955 independently turns the outputs on with
a series delay for each group to provide a soft-start feature. The output current sinks are grouped into eight
groups. The first output group that is turned on or off are OUTR4, OUTG4, OUTB4, OUTR11, OUTG11, and
OUTB11; the second output group is OUTX0 and OUTX15; the third output group is OUTX5 and OUTX10; the
fourth output group is OUTX1 and OUTX14; the fifth output group is OUTX2 and OUTX13; the sixth output group
is OUTX6 and OUTX9; the seventh output group is OUTX3 and OUTX12; and the eighth output group is OUTX7
and OUTX8. Each output group is turned on and off sequentially with a small delay between groups.
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8.4 Device Functional Modes
8.4.1 Maximum Current Control (MC) Function
The maximum output current per channel, IOLCMax, is programmed by the MC data and is set with the serial
interface. IOLCMax is the largest current for each output. Each OUTXn sinks the IOLCMax current when they turn on
and the dot correction and global brightness control data are set to the maximum value of 7Fh (127d).
When the device is powered on, the MC data are set to 0. MC data should be changed when all constant-current
outputs (OUTXn, where X = R, G, or B; n = 0 to 7) are off. MCX = 6 and MCX = 7 are used when VCC is greater
than 3.6 V. The same MC data must be written twice to change the maximum constant-current output. Table 8
shows the characteristics of the constant-current sink versus the maximum current (MC) control data.
Table 8. Maximum Constant-Current Output versus MC Data
MCX(1) DATA
IOLCMax (mA), OUTXn(2)
BINARY
000 (default)
001
DECIMAL
HEX
0 (default)
0 (default)
3.2
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8.0
010
11.2
15.9
19.1
23.9
27.1
31.9
011
100
101
110(3)
111(3)
(1) X = R, G, or B.
(2) X = R, G, or B. n = 0 to 15.
(3) MCX7 and MCX6 can be used when VCC is greater than 3.6 V.
8.4.2 Dot Correction (DC) Function
The TLC5955 can individually adjust the output current of each channel (OUTx0 to OUTx15, where x is R, G, or
B) by using DC. The DC function allows the brightness deviations of the LEDs connected to each output to be
individually adjusted. Each output DC is programmed with a 7-bit word, so the value is adjusted with 128 steps
within the range of 26.2% to 100% of IOLCMax. DC data are programmed into the TLC5955 with the serial
interface. When the device is powered on, the DC data in the control latch contains random data. Therefore, DC
data must be written to the DC data latch before turning the constant-current outputs on. Table 9 summarizes the
DC data value versus the set current value.
Table 9. DC Data versus Current Ratio and Set Current Value
DCXn(1) DATA
RATIO OF
OUTPUT
CURRENT TO
IOLCMax (%)
IOUT (mA)
(MC = 7, typical) (MC = 0, typical)
IOUT (mA)
BINARY
000 0000
000 0001
000 0010
—
DECIMAL
HEX
00
BC DATA (Hex)
0
1
7F
7F
7F
—
26.2
26.7
27.3
—
8.36
8.54
8.73
—
0.84
0.86
0.88
—
01
2
02
—
—
111 1101
111 1110
111 1111
125
126
127
7D
7E
7F
7F
7F
7F
98.8
99.4
100.0
31.5
31.7
31.9
3.16
3.18
3.20
(1) X = R, G, or B. n = 0 to 15.
28
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8.4.3 Global Brightness Control (BC) Function
The TLC5955 has the ability to adjust the output current of all constant-current outputs of each color group
(OUTR0 to OUTR15, OUTG0 to OUTG15, and OUTB0 to OUTB15) simultaneously to the same current ratio.
This function is called global brightness control (BC). The BC function allows the global brightness of LEDs
connected to the output to be adjusted. All outputs of each color group can be adjusted in 128 steps from 10% to
100% of the maximum output current, IOLCMax. BC data are programmed into the TLC5955 with the serial
interface. When the BC data change, the output current also changes immediately. When the device is powered
on, the BC data contain random data. Table 10 summarizes the BC data versus the set current value.
Table 10. BC Data versus Constant-Current Ratio and Set Current Value
BCX(1) DATA
RATIO OF
OUTPUT
CURRENT TO
IOLCMax(%)
DCXn(2) DATA
IOUT (mA)
IOUT (mA)
BINARY
000 0000
000 0001
000 0010
—
DECIMAL
HEX
00
(Hex)
(MC = 7, typical) (MC = 0, typical)
0
1
7F
7F
7F
—
10.0
10.7
11.4
—
3.19
3.42
3.64
—
0.32
0.34
0.37
—
01
2
02
—
—
111 1101
111 1110
111 1111
125
126
127
7D
7E
7F
7F
7F
7F
98.6
99.3
100.0
31.5
31.7
31.9
3.15
3.18
3.20
(1) X = R, G, or B.
(2) X = R, G, or B. n = 0 to 15.
8.4.4 Grayscale (GS) Function (PWM Control)
The TLC5955 can adjust the brightness of each output channel using a pulse width modulation (PWM) control
scheme. The architecture of 16 bits per channel results in 65,536 brightness steps, from 0% up to 100%
brightness.
The PWM operation for OUTn is controlled by a 16-bit grayscale (GS) counter. The GS counter increments on
each GS reference clock (GSCLK) rising edge. The GS counter resets to 0000h when the LAT rising signal for a
GS data write is input with the display timing reset mode enabled.
The TLC5955 has two types of PWM control: conventional PWM control and enhanced spectrum (ES) PWM
control. The conventional PWM control can be selected when the ESPWM bit in the control data latch is 0. The
ES PWM control is selected when the ESPWM bit is 1. The conventional PWM control should be selected for
multiplexing a drive. The ES-PWM control should be selected for a static drive.
The on-time (tOUT_ON) of each output (OUTn) can be calculated by Equation 2.
tOUT_ON (ns) = tGSCLK (ns) × GSXn
where:
•
•
•
•
TGSCLK = one GS clock period,
GSXn = the programmed GS value for OUTXn (GSXn = 0d to 65535d),
X = R, G, or B for the red, green, or blue color group, and
n = 0 to 15.
(2)
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Table 11 summarizes the GS data values versus the output on-time duty cycle. When the device powers up, all
OUTXn are forced off, the GS counter initializes to 0000h, and the status remains the same until GS data are
written. After that, each OUTXn on and off status can be controlled by GS data and GSCLK.
Table 11. Output Duty Cycle and On-Time versus GS Data
GS DATA
GS DATA
DECIMAL
0
HEX
0
ON-TIME DUTY (%)
0
DECIMAL
32768
32769
32770
32771
—
HEX
8000
8001
8002
8003
—
ON-TIME DUTY (%)
50.000
50.002
50.003
50.005
—
1
1
0.002
2
2
0.003
3
3
0.005
—
—
—
8191
8192
8193
—
1FFF
2000
2001
—
12.498
12.500
12.502
—
40959
40960
40961
—
9FFF
A000
A001
—
62.498
62.500
62.502
—
16381
16382
16383
16384
16385
16386
16387
—
3FFD
3FFE
3FFF
4000
4001
4002
4003
—
24.996
24.997
24.998
25.000
25.002
25.003
25.005
—
49149
49150
49151
49152
49153
49154
49155
—
BFFD
BFFE
BFFF
C000
C001
C002
C003
—
74.995
74.997
74.998
75.000
75.002
75.003
75.005
—
24575
24576
24577
—
5FFF
6000
6001
—
37.498
37.500
37.502
—
57343
57344
57345
—
DFFF
E000
E001
—
87.498
87.500
87.502
—
32765
32766
32767
7FFD
7FFE
7FFF
49.995
49.997
49.998
65533
65534
65535
FFFD
FFFE
FFFF
99.995
99.997
99.998
30
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8.4.4.1 Conventional PWM Control
The first GS clock rising edge increments the GS counter by one and switches on all outputs with a non-zero GS
value programmed into the GS data latch. Each additional GS clock rising edge increases the corresponding GS
counter by one.
The GS counter keeps track of the number of clock pulses from the respective GS clock inputs. Each output
stays on while the counter is less than or equal to the programmed GS value. Each output turns off at the GS
counter value rising edge when the counter becomes greater than the output GS latch value. Figure 27 illustrates
the conventional PWM operation.
LAT
32768
32769
32770
65535
65536
1
2
3
4
- - -
1
2
3
4
- - -
GSCLK
OUTXn
(VOUTXnH)
(VOUTXnL)
OFF
ON
No driver turns on when Grayscale data is zero.
(GSDATA=000h)
T=GSCLK*1
(VOUTXnH)
OFF
OUTXn
ON
(VOUTXnL)
(GSDATA=001h)
T=GSCLK*2
(VOUTXnH)
OFF
OUTXn
(VOUTXnL)
ON
(GSDATA=002h)
T=GSCLK*3
(VOUTXnH)
OFF
OUTXn
(VOUTXnL)
ON
(GSDATA=003h)
T=GSCLK*32767
T=GSCLK*32768
(VOUTXnH)
(VOUTXnL)
OFF
OUTXn
ON
(GSDATA=7FFFh)
(VOUTXnH)
(VOUTXnL)
OFF
OUTXn
ON
(GSDATA=8000h)
T=GSCLK*32769
(VOUTXnH)
(VOUTXnL)
OFF
OUTXn
ON
(GSDATA=8001h)
T=GSCLK*65533
T=GSCLK*65534
T=GSCLK*65535
(VOUTXnH)
(VOUTXnL)
OFF
OUTXn
ON
(GSDATA=FFFDh)
(VOUTXnH)
(VOUTXnL)
OFF
OUTXn
ON
(GSDATA=FFFEh)
(VOUTXnH)
(VOUTXnL)
OFF
OUTXn
ON
(GSDATA=FFFFh)
OUTXn turn on at the first GSCLK rising edge except when GS data are 0 after the
LAT rising signal for GS data writes is input with the display timing reset mode enabled.
OUTXn do not turn on again except for when the LAT rising signal
for GS data writes is input with the display timing reset mode
enabled (TMGRST = 1), otherwise the auto repeat mode
(DSPRPT = 1) is enabled.
Figure 27. Conventional PWM Operation
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8.4.4.2 Enhanced Spectrum (ES) PWM Control
In this PWM control, the total display period is divided into 128 display segments. The total display period is the
time from the first GS clock (GSCLK) to the 65,536th GSCLK input. Each display segment has a maximum of
512 GSCLKs. The OUTXn on-time changes, depending on the 16-bit GS data. Refer to Table 12 for the
sequence of information and to Figure 28 for the timing information.
Table 12. ES PWM Drive Turn On-Time Length
GS DATA
DECIMAL
HEX
OUTn DRIVER OPERATION
0
1
2
3
4
5
6
0000h
0001h
0002h
0003h
0004h
0005h
0006h
Does not turn on
Turns on for one GSCLK period in the first display segment
Turns on for one GSCLK period in the first and 65th display segments
Turns on for one GSCLK period in the first, 65th, and 33rd display segments
Turns on for one GSCLK period in the first, 65th, 33rd, and 97th display segments
Turns on for one GSCLK period in the first, 65th, 33rd, 97th, and 17th display segments
Turns on for one GSCLK period in the first, 65th, 33rd, 97th, 17th, and 81st display segments
The number of display segments where OUTn is turned on for one GSCLK is incremented by increasing GS data
in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 > 101 > 21 > 85 >
53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83 > 51 > 115 > 11 > 75 > 43 >
107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 > 15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 >
2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42 > 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86
> 54 > 118 > 14 > 78 > 46 > 110 > 30 > 94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44
> 108 > 28 > 92 > 60 > 124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 >
128.
—
—
Turns on for one GSCLK period in the first to 127th display segments, but does not turn on in the 128th display
segment
127
007Fh
128
129
0080h
0081h
Turns on for one GSCLK period in all display segments (first to 128th)
Turns on for two GSCLK periods in the first display period and for one GSCLK period in all other display periods
The number of display segments where OUTn is turned on for one GSCLK is incremented by increasing GS data
in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 > 101 > 21 > 85 >
53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83 > 51 > 115 > 11 > 75 > 43 >
107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 > 15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 >
2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42 > 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86
> 54 > 118 > 14 > 78 > 46 > 110 > 30 > 94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44
> 108 > 28 > 92 > 60 > 124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 >
128.
—
—
Turns on for two GSCLK periods in the first to 127th display segments and turns on one GSCLK period in the
128th display segment
255
256
257
00FFh
0100h
0101h
Turns on for two GSCLK periods in all display segments (first to 128th)
Turns on for three GSCLK periods in the first display segments and for two GSCLK periods in all other display
segments
The number of display segments where OUTn is turned on for one GSCLK is incremented by increasing GS data
in the following order:
1 > 65 > 33 > 97 > 17 > 81 > 49 > 113 > 9 > 73 > 41 > 105 > 25 > 89 > 57 > 121 > 5 > 69 > 37 > 101 > 21 > 85 >
53 > 117 > 13 > 77 > 45 > 109 > 29 > 93 > 61 > 125 > 3 > 67 > 35 > 99 > 19 > 83 > 51 > 115 > 11 > 75 > 43 >
107 > 27 > 91 > 59 > 123 > 7 > 71 > 39 > 103 > 23 > 87 > 55 > 119 > 15 > 79 > 47 > 111 > 31 > 95 > 63 > 127 >
2 > 66 > 34 > 98 > 18 > 82 > 50 > 114 > 10 > 74 > 42 > 106 > 26 > 90 > 58 > 122 > 6 > 70 > 38 > 102 > 22 > 86
> 54 > 118 > 14 > 78 > 46 > 110 > 30 > 94 > 62 > 126 > 4 > 68 > 36 > 100 > 20 > 84 > 52 > 116 > 12 > 76 > 44
> 108 > 28 > 92 > 60 > 124 > 8 > 72 > 40 > 104 > 24 > 88 > 56 > 120 > 16 > 80 > 48 > 112 > 32 > 96 > 64 >
128.
—
—
Turns on for 511 GSCLK periods in the first to 127th display segments, but only turns on for 510 GSCLK periods
in the 128th display segment
65479
65480
65481
—
FEFFh
FF00h
FF01h
—
Turns on for 511 GSCLK periods in all display segments (first to 128th)
Turns on for 512 GSCLK periods in the first display period and for 511 GSCLK periods in the second to 128th
display segments
—
Turns on for 512 GSCLK periods in the first to 63rd and 65th to 127th display segments; also turns on for 511
GSCLK periods in the 64th and 128th display segments
65534
FFFEh
Turns on for 512 GSCLK periods in the first to 127th display segments but only turns on for 511 GSCLK periods
in the 128th display segment
65535
FFFFh
32
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LAT
16382 16385
16383 16386
16384 16387
32766
32767
32768
32769
32770
32771
49150
49151
49152
49153
49154
49155
65023
65024
65025
65026
65536
65534
65535
511
512
513
514
1
2
3
GSCLK
32nd 33rd
Period Period
2nd
Period
64th 65th
Period Period
96th
Period
97th
Period
127th
Period
128th
Period
1st
Period
(Voltage Level = H)
1st Period
OFF
ON
OUTXn
(Voltage Level = L)
T = GSCLK x 1d
(GS Data = 0000h)
OFF
OUTXn
When Auto
Display Repeat
is On
ON
(GS Data = 0001h)
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
OFF
OUTXn
ON
(GS Data = 0002h)
T = GSCLK x 1d
OFF
OUTXn
ON
(GS Data = 0003h)
T = GSCLK x 1d
T = GSCLK x 1d
OFF
OUTXn
ON
(GS Data = 0004h)
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
OFF
OUTXn
ON
(GS Data = 0041h)
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 511d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
OFF
OUTXn
ON
(GS Data = 0080h)
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 1d
T = GSCLK x 2d
T = GSCLK x 2d
T = GSCLK x 1d
T = GSCLK x 2d
OFF
OUTXn
ON
(GS Data = 0081h)
OUTXn
OFF
ON
(GS Data = 0082h)
T = GSCLK x 511d
T = GSCLK x 512d
T = GSCLK x 511d in 2nd to 128th Periods
T = GSCLK x 511d in 2nd to 128th Periods
OUTXn
OFF
(GS Data = FF80h)
OFF
OUTXn
ON
(GS Data = FF81h)
T = GSCLK x 512d
T = GSCLK x 512d
T = GSCLK x 512d in 2nd to 63rd and 65rd to 127th Periods, T = GSCLK x 511din 64th Period
T = GSCLK x 511d
T = GSCLK x 511d
OFF
OUTXn
ON
T = GSCLK x 512d in 2nd to 127th Periods
(GS Data = FFFEh)
OFF
OUTXn
ON
(GS Data = FFFFh)
Figure 28. ES PWM Operation
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8.4.4.3 Auto Display Repeat Function
This function can repeat the total display period as long as GSCLK is present, as shown in Figure 29. This
function is switched on or off by the content of the DSPRPT bit in the control data latch.
When the DSPRPT bit is 1, auto display repeat is enabled and the entire display period repeats. When the
DSPRPT bit is 0, auto display repeat is disabled and the entire display period only executes one time after a LAT
signal rising edge is input for GS data writes when the display timing reset is enabled.
LAT
1
4
65534
65535
65536
1
4
65534
65535
65536
1
4
7
1
65534
65535
65536
1
2
5
2
5
2
5
8
2
2
3
65533
3
65533
3
6
9
GSCLK
1 (Auto Display
Repeat enabled)
DSPRPT= 0
(Auto Display
Repeat disabled)
TMGRST bit
in Control Data
Latch (Internal)
TMGRST bit=1
DSPRPT bit
in Control Data
Latch (Internal)
1st entire
display period
1st entire display period
2nd entire display period
3rd entire display period
Display period is repeated
by Auto DisplayRepeat
function.
OUTXn is forced off
when LAT rising edge is
input for GS data writing
with timing reset mode
enable (TMGRST=1).
OFF
OUTXn
ON
OUTXn is not turned on again
because Display Auto Repeat
is disable (DSPRPT=0).
(GSDATA=FFFFh)
Figure 29. Auto Display Repeat Function
34
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8.4.4.4 Display Timing Reset Function
The display timing reset function allows initializing the display timing with a LAT rising edge. This function can be
switched on or off with the TMGRST bit in the control data latch. When the TMGRST bit is 1, the GS counter is
reset to 0 and all outputs are forced off at the LAT rising edge for a GS data write. Furthermore, the 768-bit GS
data latch is updated with the data from the common shift register and the 336-bit DC data latch is updated with
the DC data in the 371-bit control data latch. When the TMGRST bit is 0, the GS counter is not reset and the
outputs are not forced off, even if a LAT rising edge is input. A timing diagram for this function is shown in
Figure 30.
Control Data Write (MSB of the Common Shift Register = 1)
Grayscale Data Write (MSB of the Common Shift Register = 0)
Grayscale Data Write
DCR0 DCR0 DCR0 DCR0
2A
DCR0
0A
GSB15 GSB15
14A
GSR0 GSR0 GSR0
1A
GSR0
0A
GSB15 GSB15 GSB15
13B
Low
1
SIN
SCLK
LAT
Low
4A
3A
1A
15A
3A
2A
15B
14B
1
2
3
764
765
766
767
768
769
766
767
768
769
2
3
4
GSCLK
DSPRPT Bit in Control Data
(Internal)
DSPRPT Bit = 1
TMGRST Bit = 1
RFRESH Bit = 0
TMGRST Bit in Control Data
(Internal)
RFRESH Bit in Control Data
(Internal)
CommonShift Register
(Internal)
SID are loaded at the LAT falling edge.
GS Counter Data
(Internal)
GS counter data are incremented at each
GSCLK rising edge.
GS counter data are incremented
at each GSCLK rising edge.
0
GS counter is reset to zero when LAT for
GS data writes is input with TMGRST = 1.
Internal LAT Enable
(Internal)
Always Enabled
Internal LAT Signal
(Internal)
GS Data Latch
(Internal)
Old Grayscale Data
New Grayscale Data
Control Data Latch
(Internal)
New Control Data
Old Control Data
DC Data Latch
(Internal)
New DC Data
Old DC Data
OUTXn are forced off when LAT for GS data
writes is input with the TMGRST bit = 1.
OFF
(1)
OUTXn are controlled by old GS, DC data.
OUTXn are controlled by new GS, DC data.
OUTXn
ON
LOD
B15A
LOD
LOD
G15A R15A B14A
LOD
DCR0 DCR0 DCR0
0A
Low
SOUT
High
2A
1A
Figure 30. Display Timing Reset Function (DSPRPT = 1, TMGRST = 1, and RFRESH = 0)
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8.4.4.5 Auto Data Refresh Function
This function delays updating the grayscale (GS) and dot correction (DC) data until the end of one entire display
period. If both DC data and GS data are written by the end of an entire display period, the input DC data are held
in the control data latch and the GS data are held in the common shift register. Both DC and GS data are copied
to the 336-bit DC data latch and 768-bit GS data latch at the end of an entire display period. The data latches
are used for the next display period. GS data are directly copied from the common shift register to the GS data
latch. Therefore, GS data must be written after the DC data are written. Furthermore, the GS data in the common
shift resistor must not be changed until all data are copied to the GS data latch. Figure 31 and Figure 32 show
timing diagrams for this function.
Control Data Write (MSB of the Common Shift Register = 1)
Grayscale Data Wriet (MSB of the Common Shift Register = 0)
Grayscale Data Write
GSB15 GSB15
14A
GSR0 GSR0 GSR0
3A
GSR0
0A
GSB15
L
15B
DCR0 DCR0 DCR0 DCR0
3A
DCR0
0A
L
SIN
SCLK
LAT
4A
2A
1A
15A
2A
1A
1
2
1
2
3
764
765
766
767
768
769
766
767
768
769
65535th GSCLK
65536th GSCLK
1
3
5
7
2
4
6
8
GSCLK
DSPRPT Bit
in Control Data
(Internal)
DSPRPT bit=1
TMGRST bit=0
RFRESH bit=1
TMGRST Bit
in Control Data
(Internal)
RFRESH Bit
in Control Data
(Internal)
CommonShift
Register
(Internal)
SID are loaded at 1st
GSCLK input.
GS Counter
Data (Internal)
GS counter data is incremented
at each GSCLK rising edge.
GS counter data is incremented
at each GSCLK rising edge.
0
The internal LAT enable is set
to high level when LAT is input
for GS data writing.
The internal LAT enable
is set to low level when
1st GSCLK is input.
Internal LAT
Enable
(Internal)
The internal LAT signal is generated
at 65536th GSCLK when Internal LAT
enable is high level only.
Internal
LAT Signal
(Internal)
GS Data
Latch
(Internal)
New Grayscale Data
Old Grayscale Data
Control Data
Latch
(Internal)
New Control Data
Old Control Data
DC Data
Latch
(Internal)
Old DC Data
New DC Data
OFF
OUTn are controlled
by new GS/DC data
OUTn are controlled by old GS/DC data.
DCR0 DCR0 DCR0
OUTn
.
ON
LOD LOD
B15A G15A
L
H
SOUT
2A
1A
0A
Figure 31. Auto Data Refresh Function 1 (DSPRPT = 1, TMGRST = 0, and RFRESH = 1)
36
Copyright © 2014, Texas Instruments Incorporated
TLC5955
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ZHCSC51 –MARCH 2014
Control Data Write (MSB of the Common Shift register = 1
Grayscale Data Write (MSB of the Common Shift Register = 0)
Grayscale Data Write
DCR0 DCR0 DCR0 DCR0
2A
DCR0
0A
GSB15 GSB15
14A
GSR0 GSR0 GSR0
1A
GSR0
0A
GSB15 GSB15 GSB15
13B
L
L
SIN
764
4A
3A
1A
15A
3A
2A
15B
14B
1
2
3
765
766
767
768
769
766
767
768
769
1
2
3
4
SCLK
LAT
GSCLK
DSPRPT bit
in Control Data
(Internal)
DSPRPT bit =1
TMGRST bit =0
RFRESH bit =0
TMGRST bit
in Control Data
(Internal)
RFRESH bit
in Control Data
(Internal)
CommonShift
Register
(Internal)
SID are loaded at the LAT falling edge.
GS Counter
Data (Internal)
GS counter data is incremented
at each GSCLK rising edge.
Internal LAT
Enable
(Internal)
Always enable
Internal
LAT Signal
(Internal)
GS Data
Latch
(Internal)
Old Grayscale Data
New Grayscale Data
Control Data
Latch
(Internal)
Old Control Data
New Control Data
DC Data
Latch
(Internal)
Old DC Data
New DC Data
OFF
OUTn are controlled
by old GS/DC data.
OUTn are controlled
by new GS/DC data.
OUTn
ON
LOD
G15A R15A B14A
DCR0 DCR0 DCR0
2A 1A 0A
LOD
B15A
LOD
LOD
L
H
SOUT
Figure 32. Auto Data Refresh Function 2 (DSPRPT = 1, TMGRST = 0, and RFRESH = 0)
Copyright © 2014, Texas Instruments Incorporated
37
TLC5955
ZHCSC51 –MARCH 2014
www.ti.com.cn
9 Applications and Implementation
9.1 Application Information
The device is a 48-channel, constant sink current, LED driver. This device is typically connected in series to drive
many LED lamps with only a few controller ports. Output current control data and PWM control data can be
written from the SIN input terminal. The PWM timing reference clock can be supplied from the GSCLK input
terminal. Also, the LED open and short error flag can be read out from the SOUT output terminal. Furthermore,
the device maximum GSCLK clock frequency is 33 MHz and can reduce flickering discernable by the human
eye.
9.2 Typical Application
9.2.1 Daisy-Chain Application
In this application, the device VCC and LED lamp anode voltages are supplied from different power supplies.
VLED
+
x48
¼
x48
¼
¼¼
¼
¼
OUTR0
SIN
OUTB15
SOUT
OUTR0
SIN
OUTB15
DATA
SCLK
LAT
SOUT
VCC
VCC
SCLK
LAT
SCLK
LAT
TLC5955
TLC5955
VCC
VCC
IC1
ICn
GSCLK
GSCLK
GSCLK
Controller
GND
GND
GND
GND
3
Error Read
Figure 33. Multiple Daisy-Chained TLC5955 Devices
9.2.1.1 Design Requirements
For this design example, use the following as the input parameters.
Table 13. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VCC input voltage range
3.0 V to 5.5 V
LED lamp (VLED) input voltage range
Maximum LED forward voltage (VF) + 0.3 V (knee voltage)
Low level = GND, High level = VCC
SIN, SCLK, LAT, and GSCLK voltage range
38
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TLC5955
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ZHCSC51 –MARCH 2014
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Step-by-Step Design Procedure
To begin the design process, a few parameters must be decided upon. The designer needs to know the
following:
•
•
•
•
•
•
Maximum output constant-current value for each color LED ramp.
Maximum LED forward voltage (VF).
Current ratio of red, green, and blue LED lamps for the best white balance.
Are the auto display repeat function, display timing reset function, or auto data refresh function used?
Which PWM control method is used: ES-PWM or conventional PWM?
Is the LED short detect (LSD) function used? If so, which detection level (70% VCC or 90% VCC) is used?
9.2.1.2.2 Maximum Current (MC) Data
There are a total of nine bits of MC data for the red, green, and blue LED ramp. Select the MC data to be greater
than each LED ramp current and write the data with other control data.
9.2.1.2.3 Global Brightness Control (BC) Data
There are a total of three sets of 7-bit BC data for the red, green, and blue LED ramp. Select the BC data for the
best white balance of the red, green, and blue LED ramp and write the data with other control data.
9.2.1.2.4 Dot Correction (DC) Data
There are a total of 48 sets of 7-bit DC data for each current adjustment. Select the DC data for the best
uniformity of each color LED ramp and write the data with other control data.
9.2.1.2.5 Grayscale (GS) Data
There are a total of 48 sets of 16-bit GS data for the PWM control of each output. Select the GS data of the LED
ramp intensity and color control and write the data with other GS data.
9.2.1.2.6 Other Control Data
There are five bits control data to set the function mode for the auto display repeat, display timing reset, auto
data refresh, ES-PWM, and LSD functions explained in the Device Functional Modes section. Write the 5-bit
control data for the appropriate operation of the display system with MC, BC, and DC data as the control data.
Copyright © 2014, Texas Instruments Incorporated
39
TLC5955
ZHCSC51 –MARCH 2014
www.ti.com.cn
9.2.1.3 Application Curves
One LED connected to each output.
Ch1: VCC (2 V/div)
Ch1: VCC (2 V/div)
Ch2: VLED (2 V/div)
Ch2: VLED (2 V/div)
Ch3: VOUTB0 (1 V/div, Blue LED Connected)
Ch3: VOUTB0 (1 V/div, Blue LED Connected)
Ch4: LAT (5 V/div)
Ch4: LAT (5 V/div)
Time (40 ns/div)
Time (400 ꢀs/div)
MCX = 4
BCX = DCXn = 7Fh
GSCLK = 33 MHz
DSPRPT = 1
MCX = 4
BCX = DCXn = 7Fh
GSCLK = 33 MHz
DSPRPT = 1
VLED = 4.2 V
VCC = 3.3 V
VLED = 4.2 V
VCC = 3.3 V
TMGRST, RFRESH, ESPWM, LSDVLT = 0
TMGRST, RFRESH, ESPWM, LSDVLT = 0
Figure 34. Output Waveform Immediately After First GS
Figure 35. Output Waveform Immediately After First GS
Data Latch Input (GSXn = 0001h)
Data Latch Input (GSXn = 7FFFh)
40
Copyright © 2014, Texas Instruments Incorporated
TLC5955
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ZHCSC51 –MARCH 2014
10 Power Supply Recommendations
The VCC power-supply voltage should be well regulated. An electrolytic capacitor must be used to reduce the
voltage ripple to less than 5% of the input voltage. Furthermore, the VLED voltage should be set to the voltage
calculated by Equation 3:
VLED ≥ LED VF × Number of LED Lamps Connected in Series + 0.3 V (20 mA for Constant-Current Example)
where:
•
VF = Forward voltage
(3)
Because the total current of the constant-current output is large, some electrolytic capacitors must be used to
prevent the OUTXn terminal voltage from dropping lower than the calculated voltage from Equation 3.
11 Layout
11.1 Layout Guidelines
1. Place the decoupling capacitor near the VCC and GND terminals.
2. Route the GND pattern as widely as possible for large GND currents. Maximum GND current is
approximately 1.53 A.
3. Routing between the LED cathode side and the device OUTXn should be as short and straight as possible to
reduce wire inductance.
4. The PowerPAD must be connected to the GND layer because the pad is not internally connected to GND
and should be connected to a heat sink layer to reduce device temperature.
Copyright © 2014, Texas Instruments Incorporated
41
TLC5955
ZHCSC51 –MARCH 2014
www.ti.com.cn
11.2 Layout Example
Via
Top-Side PCB Pattern
Bottom-Side PCB Pattern
LAT SIN
GND
GSCLK
VLED
VLED
SCLK
VCC
SIN
GND
SCLK
LAT
GSCLK
VCC
OUTB4
OUTB8
OUTR4
OUTG4
OUTB0
OUTR8
OUTG8
OUTB12
OUTR0
OUTR12
OUTG0
OUTB5
OUTR5
OUTG12
OUTB9
OUTR9
Power
OUTG5
OUTB1
OUTR1
OUTG9
OUTB13
OUTR13
Via to Heatsink Layer
OUTG1
OUTB2
OUTR2
OUTG13
OUTB14
OUTR14
OUTG2
OUTB2
OUTR6
OUTG6
OUTG14
OUTB10
OUTR10
OUTG10
OUTB6
OUTR3
OUTB15
OUTR15
OUTG3
OUTB7
OUTR7
OUTG15
OUTB11
OUTR11
OUTG7
SOUT
OUTG11
GND
To Next
VLED
To Next To Next
To Next
SCLK
To Next
GSCLK
To Next
VLED
LAT
SIN
Figure 36. Layout Example
42
Copyright © 2014, Texas Instruments Incorporated
TLC5955
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ZHCSC51 –MARCH 2014
12 器件和文档支持
12.1 器件支持
12.1.1 开发支持
要获得 LED 驱动器解决方案，请访问 http://www.ti.com.cn/solution/cn/lighting_signage。
12.2 文档支持
12.2.1 相关文档ꢀ
相关文档如下：
•
《PowerPAD™ 耐热增强型封装应用报告》，SLMA002
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
Copyright © 2014, Texas Instruments Incorporated
43
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IMPORTANT NOTICE
邮寄地址： 上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122
Copyright © 2014, 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLC5955DCA
TLC5955DCAR
TLC5955RTQR
TLC5955RTQT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTSSOP
HTSSOP
QFN
DCA
DCA
RTQ
RTQ
56
56
56
56
35
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
TLC5955
2000 RoHS & Green
2000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
TLC5955
TLC5955
TLC5955
QFN
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
GENERIC PACKAGE VIEW
RTQ 56
8 x 8, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224653/A
www.ti.com
PACKAGE OUTLINE
VQFN - 1 mm max height
RTQ0056G
PLASTIC QUAD FLATPACK-NO LEAD
8.15
7.85
A
B
8.15
7.85
PIN 1 INDEX AREA
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
5.6±0.1
(0.2) TYP
15
28
52X 0.5
14
29
57
4X
6.5
SYMM
5.6±0.1
1
42
0.30
0.18
56X
PIN 1 ID
(OPTIONAL)
43
56
0.1
C A B
C
0.5
0.3
56X
SYMM
0.05
4225369 / A 10/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RTQ0056G
PLASTIC QUAD FLATPACK-NO LEAD
(0.78)
(5.6)
8X (1.33)
6X (1.22)
43
56X (0.6)
56
1
42
56X (0.24)
6X (1.22)
8X (1.33)
52X (0.5)
SYMM
(7.8)
(5.6)
57
(R0.05)
TYP
14
29
(Ø0.2) TYP
VIA
15
28
SYMM
LAND PATTERN EXAMPLE
SCALE: 10X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225369 / A 10/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments
literature number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their
locations shown on this view. it is recommended thar vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RTQ0056G
PLASTIC QUAD FLATPACK-NO LEAD
(7.8)
8X (0.665)
8X (1.33)
43
56X (0.6)
56
56X (0.24)
1
42
57
8X (1.33)
52X (0.5)
SYMM
(7.8)
8X (0.665)
(R0.05) TYP
16X
(
1.13)
14
29
METAL
TYP
15
28
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
66% PRINTED COVERAGE BY AREA
SCALE: 10X
4225369 / A 10/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations..
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