TLIN1022ADRQ1 [TI]
具有显性状态超时的汽车类双路本地互连网络 (LIN) 收发器 | D | 14 | -40 to 125;型号: | TLIN1022ADRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有显性状态超时的汽车类双路本地互连网络 (LIN) 收发器 | D | 14 | -40 to 125 |
文件: | 总46页 (文件大小:2553K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLIN1022A-Q1
ZHCSMJ3 –JUNE 2021
TLIN1022A-Q1 具有显性状态超时的双路本地互连网络(LIN) 收发器
1 特性
2 应用
• 符合面向汽车应用的AEC-Q100(1 级)标准
• 符合LIN 2.0、LIN 2.1、LIN 2.2、LIN 2.2 A 和
ISO/DIS 17987–4 电气物理层(EPL) 规格标准
• 符合面向汽车应用的SAE J2602-1 LIN 网络标准
• 提供功能安全
• 车身电子装置和照明
• 混合动力电动汽车和动力总成系统
• 信息娱乐系统与仪表组
• 电器
3 说明
– 可帮助进行功能安全系统设计的文档
• 支持12V 电池应用
TLIN1022A-Q1 是一款双路本地互连网络 (LIN) 物理层
收发器,集成了唤醒和保护功能,符合 LIN 2.0、LIN
2.1、LIN 2.2、LIN 2.2A 和 ISO/DIS 17987–4 标准。
LIN 是一根单线制双向总线,通常用于低速车载网络,
数据传输速率高达 20kbps。TLIN1022A-Q1 旨在为
12V 应用提供支持,具有更宽的工作电压范围和额外
的总线故障保护。
• LIN 传输数据速率高达20kbps
• LIN 接收数据速率高达100kbps
• 宽工作电源电压范围:4V 至36V
• 休眠模式:超低电流消耗允许以下类型的唤醒事
件:
– LIN 总线
LIN 接收器支持高达 100kbps 的数据传输速率,从而
更快速地执行内联编程。TLIN1022A-Q1 使用一个可降
低电磁辐射(EME) 的限流波形整形驱动器将 TXD 输入
上的 LIN 协议数据流转化为 LIN 总线信号。接收器将
数据流转化为逻辑电平信号,此信号通过开漏 RXD 引
脚发送到微处理器。休眠模式可实现超低电流消耗,该
模式允许通过LIN 总线或EN 引脚实现唤醒。
– 通过EN 引脚的本地唤醒
• 在LIN 总线和RXD 输出上实现上电和断电无干扰
运行
• 保护特性:
– ±45V LIN 总线容错
– VSUP 欠压保护
– TXD 显性超时(DTO) 保护
– 热关断保护
器件信息
封装(1)
– 系统级未供电节点或接地断开失效防护。
• 可提供具有可湿性侧面的SOIC (14) 和无引线
VSON (14) 封装
封装尺寸(标称值)
5.00mm x 8.65mm
3.00mm x 4.50mm
器件型号
SOIC (14) (D)
TLIN1022A-Q1
VSON (14) (DMT)
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附
录。
VBAT
VSUP
VBAT
VSUP
COMMANDER
NODE
VREG
VSUP
VREG
VSUP
RESPONDER
NODE
VDD
VDD
VSUP
VSUP
VDD
VDD
NC
14
NC
14
NC
6
NC
6
EN1
Commander Node
Pullup
10
10
VDD
I/O
VDD
I/O
2
2
VDD I/O
VDD I/O
1 kΩ
MCU w/o
pullup(2)
MCU w/o
pullup(2)
LIN1
LIN1
LIN Bus
MCU
MCU
13
13
LIN Bus
220 pF
220 pF
1
3
1
3
RXD1
TXD1
RXD1
TXD1
TLIN1022A
TLIN1022A
LIN Controller
Or
SCI/UART(1)
LIN Controller
Or
SCI/UART(1)
VDD I/O
VDD I/O
LIN Bus
LIN Bus
LIN2
LIN2
9
MCU w/o
pullup(2)
MCU w/o
pullup(2)
9
220 pF
220 pF
4
7
4
7
RXD2
TXD2
RXD2
TXD2
12 NC
11 NC
12 NC
11 NC
EN2
EN2
5
5
I/O
I/O
GND
8
GND
8
简化原理图,指挥官模式1
简化原理图,响应者模式2
本文档旨在为方便起见,提供有关TI 产品中文版本的信息,以确认产品的概要。有关适用的官方英文版本的最新信息,请访问
www.ti.com,其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SLLSFK9
TLIN1022A-Q1
ZHCSMJ3 –JUNE 2021
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Table of Contents
9.2 Functional Block Diagram.........................................22
9.3 Feature Description...................................................22
9.4 Device Functional Modes..........................................25
10 Application Information Disclaimer...........................28
10.1 Application Information........................................... 28
10.2 Typical Application.................................................. 28
11 Layout...........................................................................32
11.1 Layout Guidelines................................................... 32
11.2 Layout Example...................................................... 33
12 Device and Documentation Support..........................34
12.1 Documentation Support.......................................... 34
12.2 接收文档更新通知................................................... 34
12.3 支持资源..................................................................34
12.4 Trademarks.............................................................34
12.5 Electrostatic Discharge Caution..............................35
12.6 Glossary..................................................................35
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 说明(续).........................................................................3
5 Revision History.............................................................. 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 ESD Ratings - IEC ..................................................... 5
7.4 Thermal Information ...................................................5
7.5 Recommended Operating Conditions ........................6
7.6 Electrical Characteristics ............................................6
7.7 Duty Cycle Characteristics .........................................8
7.8 Switching Characteristics .........................................10
7.9 Typical Characteristics.............................................. 11
8 Parameter Measurement Information..........................13
9 Detailed Description......................................................21
9.1 Overview...................................................................21
Information.................................................................... 35
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4 说明(续)
TLIN1022A-Q1 集成了一个用于LIN 响应节点应用、ESD 保护和故障保护的电阻器,可减少应用中的外部元件数
量。一旦发生接地漂移或电源电压断开,该器件可防止反馈电流经LIN 流向电源输入。器件还包含欠压保护、过
热关断保护和接地失效保护功能。
5 Revision History
注:以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
June 2021
*
Initial release
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6 Pin Configuration and Functions
RXD1
EN1
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
RXD1
EN1
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
LIN1
NC
LIN1
NC
TXD1
RXD2
EN2
TXD1
RXD2
EN2
Thermal
Pad
NC
NC
VSUP
LIN2
GND
VSUP
LIN2
GND
NC
NC
TXD2
8
TXD2
8
Not to scale
Not to scale
图6-2. DMT Package, 14-Pin (VSON), Top View
图6-1. D Package, 14-Pin (SOIC), Top View
表6-1. Pin Functions
PIN
NAME
Type
DESCRIPTION
NO.
1
RXD1
EN1
O
I
Channel 1 RXD Output (open-drain) interface reporting state of LIN bus voltage
Channel 1 Enable Input- High puts the channel 1 in normal operation mode and low puts it in
sleep mode
2
3
4
TXD1
RXD2
I
Channel 1 TXD input interface to control state of LIN output
O
Channel 2 RXD Output (open-drain) interface reporting state of LIN bus voltage
Channel 2 Enable Input- High puts the channel 2 in normal operation mode and low puts it in
sleep mode
5
EN2
I
7
8
TXD2
GND
LIN2
VSUP
LIN1
I
Channel 2 TXD input interface to control state of LIN output
Ground
GND
9
HV I/O
Supply
HV I/O
Channel 2 High voltage LIN bus single-wire transmitter and receiver
Device Supply Voltage (connected to battery in series with external reverse blocking diode)
Channel 1 High voltage LIN bus single-wire transmitter and receiver
10
13
6, 11, 12,
14
NC
Not Connected
–
–
Can be connected to the PCB ground plane to improve thermal coupling (DMT package
only)
Thermal Pad
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7 Specifications
7.1 Absolute Maximum Ratings
(1) (2)
Symbol
Parameter
MIN
–0.3
–45
–0.3
MAX
45
45
6
UNIT
V
VSUP
VLIN
Supply voltage range (ISO/DIS 17987)
LIN bus input voltage (ISO/DIS 17987)
Logic pin voltage (RXD, TXD, EN)
Logic pin output current
V
VLOGIC
IO
V
8
mA
°C
TJ
Junction temperature range
150
–55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltage values are with respect to ground terminal.
7.2 ESD Ratings
ESD Ratings
VALUE
UNIT
Human body model (HBM) classification level 3A: TXD, RXD,
EN Pins, per AEC Q100-002(1)
±4000
Human body model (HBM) classification level 3B: LIN and VSUP
Pin with respect to ground
±8000
±1500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM)
classification level C5, per AEC All pins
Q100-011
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 ESD Ratings - IEC
ESD and Surge Protection Ratings
VALUE
UNIT
IEC 62228-2 per ISO 10605
Contact discharge
R = 330 Ω, C = 150 pF
Electrostatic discharge, LIN, VSUP to
GND(1)
V(ESD)
±8000
V
Pulse 1
Pulse 2
Pulse 3a
Pulse 3b
V
V
V
V
–100
75
ISO 7637-2 and IEC 62228-2 per IEC
62215-3 transients according to IBEE LIN
EMC test specifications (2) (LIN , VSUP to
GND )
VTRAN
–150
100
(1) Results given here are specific to the IEC 62228-2 Integrated circuits –EMC evaluation of transceivers –Part 2: LIN transceivers.
Testing performed by OEM approved independent 3rd party, EMC report available upon request.
(2) ISO 7637 is a system level transient test. Different system level configurations may lead to different results
7.4 Thermal Information
TLIN1022AD-Q1
D (SOIC)
14-PINS
82.3
TLIN1022ADMT-Q1
THERMAL METRIC(1)
DMT (VSON)
14-PINS
35.5
UNIT
RΘJA
RΘJC(top)
RΘJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
41.5
18.1
38.4
13.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
8.9
0.6
38.1
13.1
ΨJB
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7.4 Thermal Information (continued)
TLIN1022AD-Q1
D (SOIC)
14-PINS
TLIN1022ADMT-Q1
DMT (VSON)
14-PINS
THERMAL METRIC(1)
UNIT
RΘJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
2.5
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Recommended Operating Conditions
parameters valid across -40℃≤TA ≤125℃(unless otherwise noted)
PARAMETER - DEFINITION
MIN
4
NOM
MAX
36
UNIT
V
VSUP
VLIN
Supply voltage
LIN Bus input voltage
0
36
V
VLOGIC
TA
Logic Pin Voltage (RXD, TXD, EN)
Ambient temperature range
Thermal shutdown rising threshold
Thermal shutdown hysteresis
0
5.25
125
V
-40
165
°C
°C
°C
TSD
TSD(HYS)
15
7.6 Electrical Characteristics
parameters valid across -40℃≤TA ≤125℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4
TYP
MAX UNIT
Power Supply
Device is operational beyond the LIN
defined nominal supply voltage range
See Figure 8-1 and Figure 8-2
Operational supply voltage (ISO/DIS
17987 Param 10)
VSUP
36
36
V
V
Nominal supply voltage (ISO/DIS 17987 Normal and Standby Modes: ramp VSUP
Param 10): Normal Mode: Ramp VSUP while LIN signal is a 10 kHZ square
while LIN signal is a 10 kHZ Square
Wave with 50 % duty cycle and 36V
swing
4
wave with 50 % duty cycle and 36V
swing. See Figure 8-1 and Figure 8-2
VSUP
Sleep Mode
4
36
V
V
UVSUP
UVHYS
Undervoltage VSUP threshold
2.9
3.85
Delta hysteresis voltage for VSUP
undervoltage threshold
0.2
1.2
V
Normal Mode: EN = High, bus
dominant: total bus load where RLIN
500 Ωand CLIN < 10 nF
>
>
7.5
mA
ISUP
Supply current
Standby Mode: EN = Low, bus
dominant: total bus load where RLIN
500 Ωand CLIN < 10 nF
1.1
3.75
mA
Normal Mode: EN = High, Bus
Recessive: LIN = VSUP
670
20
1300
40
µA
µA
µA
µA
Standby Mode: EN = Low, Bus
Recessive LIN = VSUP
ISUP
Supply current
Sleep Mode: 4.0 V < VSUP < 14 V, LIN =
VSUP, EN = 0 V, TXD and RXD Floating
10
20
Sleep Mode: 14 V < VSUP < 36 V, LIN =
VSUP, EN = 0 V, TXD and RXD floating
30
RXD1/RXD2 OUTPUT PIN (OPEN DRAIN)
(4)
VOL
IOL
Output Low voltage
Based upon external pull up to VCC
0.6
V
Low-level output current, open drain
LIN = 0 V, RXD = 0.4 V
1.5
mA
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7.6 Electrical Characteristics (continued)
parameters valid across -40℃≤TA ≤125℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IILG
Leakage current, high-level
LIN = VSUP, RXD = 5 V
0
5
µA
–5
TXD1/TXD2 INPUT PIN
VIL
VIH
Low-level input voltage
0.8
V
V
–0.3
High-level input voltage
2
5.25
Input threshold voltage, normal modes
& selective wake modes
VHYS
50
500
mV
IILG
Low-level input leakage current
Internal pull-down resistor value
TXD = Low
0
5
µA
–5
RTXD
125
350
800
kΩ
EN1/EN2 INPUT PIN
VIL
Low-level input voltage
0.8
5.25
500
5
V
V
–0.3
VIH
High-level input voltage
Hysteresis voltage
2
VHYS
By design and characterization
EN = Low
50
0
mV
µA
IILG
Low-level input current
Internal Pulldown resistor
–5
REN
125
350
800
kΩ
LIN1/LIN2 PIN
LIN recessive high-level output voltage
TXD = high, IO = 0 mA, VSUP = 7 V to
36 V
VOH
0.85
0.8
3
VSUP
VSUP
V
(3)
LIN recessive high-level output voltage
TXD = high, IO = 0 mA, 7 V ≤VSUP
≤
VOH
(1) (2)
18 V
LIN recessive high-level output voltage
TXD = high, IO = 0 mA, VSUP = 4 V ≤
VSUP < 7 V
VOH
(3)
LIN dominant low- level output voltage
VOL
TXD = low, VSUP = 7 V to 36 V
0.2 VSUP
0.2 VSUP
(3)
LIN dominant low- level output voltage
VOL
TXD = low, 7 V ≤VSUP ≤18 V
TXD = low, VSUP = 4 V ≤VSUP < 7 V
TXD & RXD open LIN = 4 V to 45 V
(1) (2)
LIN dominant low- level output voltage
VOL
1.2
45
V
(3)
VSUP where impact of recessive LIN
bus < 5% (ISO/DIS 17987 Param 11)
VSUP_NON_OP
IBUS_LIM
IBUS_PAS_dom
IBUS_PAS_rec1
IBUS_PAS_rec2
IBUS_NO_GND
V
–0.3
40
TXD = 0 V, VLIN = 18 V, VSUP = 18 V,
RMEAS = 440 Ω, VBUSDOM < 4.518 V
Limiting current (ISO/DIS 17987 Param
12)
90
200
mA
mA
µA
µA
mA
Receiver leakage current, dominant
(ISO/DIS 17987 Param 13)
LIN = 0 V, VSUP = 12 V Driver off/
recessive; See Figure 8-6
–1
Receiver leakage current, recessive
(ISO/DIS 17987 Param 14)
LIN > VSUP, 4 V ≤VSUP ≤36 V Driver
off; See Figure 8-7
20
5
Receiver leakage current, recessive
(ISO/DIS 17987 Param 14)
LIN = VSUP, Driver off; See Figure 8-7
–5
–1
Leakage current, loss of ground
(ISO/DIS 17987 Param 15)
GND = VSUP, 0 V ≤VLIN = 18 V, VSUP
12 V; See Figure 8-8
=
1
VSUP = 8 V, GND = open, VSUP = 18 V,
GND = open
RCommander = 1 kΩ, CL = 1 nF
RResponder = 20 kΩ, CL = 1 nF
LIN = dominant
Ileak gnd(dom)
Leakage current, loss of ground (5)
Leakage current, loss of ground (5)
-1
1
mA
µA
VSUP = 8 V, GND = open, VSUP = 18 V,
GND = open
RCommander = 1 kΩ, CL = 1 nF
RResponder = 20 kΩ, CL = 1 nF
LIN = recessive
Ileak gnd(rec)
-100
100
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MAX UNIT
7.6 Electrical Characteristics (continued)
parameters valid across -40℃≤TA ≤125℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
Leakage current, loss of supply
(ISO/DIS 17987 Param 16)
0 V ≤VLIN ≤36 V, VSUP = GND;
See Figure 8-9
IBUS_NO_BAT
5
µA
LIN dominant (including LIN dominant
for wake up); See Figure 8-4 and Figure
8-3
Low-level input voltage (ISO/DIS 17987
Param 17) (3)
VBUSdom
0.4 VSUP
High-level input voltage (ISO/DIS 17987 LIN recessive; See Figure 8-4 and
VBUSrec
VIH
0.6
0.47
0.4
VSUP
0.6 VSUP
Param 18) (3)
Figure 8-3
LIN recessive high-level input voltage (1)
7 V ≤VSUP ≤18 V
(2)
LIN dominant low-level input voltage (1)
VIL
0.53 VSUP
0.525 VSUP
0.175 VSUP
0.175 VSUP
7 V ≤VSUP ≤18 V
(2)
Receiver center threshold (ISO/DIS
17987 Param 19)
VBUS_CNT = ( VBUSdom + VBUSrec )/2; See
Figure 8-4 and Figure 8-3
VBUS_CNT
VHYS
0.475
0.5
Hysteresis voltage (ISO/DIS 17987
Param 20)
VHYS = (VBUSrec - VBUSdom); See Figure
8-4 and Figure 8-3
VHYS = VIH - VIL; See Figure 8-4 and
Figure 8-3
VHYS
Hysteresis voltage (SAE J2602)
0.07
0.4
Serial diode LIN termination pull-up
path (ISO/DIS 17987 Param 21)
VSERIAL_DIODE
0.7
45
1
V
ISERIAL_DIODE = 10 μA
Pull-up resistor to VSUP (ISO/DIS 17987
Param 26)
RPU
Normal and Standby modes
20
60
kΩ
IRSLEEP
CLINPIN
Pull-up current source to VSUP
Capacitance of the LIN pin
Sleep mode, VSUP = 14 V, LIN = GND
VSUP = 14 V
µA
pF
–20
–2
25
(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩand 899 pF/20 kΩ
(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ωand 899 pF/900 Ω
(3) ISO 17987 bus load conditions (CLINBUS, RLINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.
(4) RXD uses open drain output structure therefore VOL level is based upon microcontroller supply voltage VCC
(5) Ileak gnd = (VBAT - VLIN)/RLoad
.
7.7 Duty Cycle Characteristics
parameters valid across -40℃≤TA ≤125℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
THREC(MAX) = 0.744 x VSUP THDOM(MAX)
= 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT
= 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x
tBIT) (See Figure 8-10, Figure 8-11)
Duty Cycle 1 (ISO/DIS 17987 Param
27)(3)
D112V
0.396
THREC(MAX) = 0.625 x VSUP, THDOM(MAX)
= 0.581 x VSUP, VSUP = 4 V to 7 V, tBIT
50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x
tBIT) (See Figure 8-10, Figure 8-11)
=
D112V
Duty Cycle 1 (3)
0.396
0.396
THREC(MAX) = 0.744 x VSUP
,
THDOM(MAX) = 0.581 x VSUP
,
D1
Duty cycle 1 (1) (2)
VSUP = 7 V to 18 V, tBIT = 52 μs
D1 = tBUS_rec(min)/(2 x tBIT) (See Figure
8-10, Figure 8-11)
THREC(MIN) = 0.422 x VSUP, THDOM(MIN)
= 0.284 x VSUP, VSUP = 7 V to 18 V, tBIT
= 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2
x tBIT) (See Figure 8-10, Figure 8-11)
Duty Cycle 2 (ISO/DIS 17987 Param
28) (3)
D212V
0.581
0.581
THREC(MIN) = 0.546 x VSUP, THDOM(MIN)
= 0.4 x VSUP, VSUP = 4 V to 7 V, tBIT
=
D212V
Duty Cycle 2 (3)
50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x
tBIT) (See Figure 8-10, Figure 8-11)
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7.7 Duty Cycle Characteristics (continued)
parameters valid across -40℃≤TA ≤125℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
THREC(MIN) = 0.422 x VSUP
THDOM(MIN) = 0.284 x VSUP
VSUP = 7 V to 18 V, tBIT = 52 μs
D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure
8-10, Figure 8-11)
MIN
TYP
MAX UNIT
,
,
D2
Duty Cycle 2 (1) (2)
0.581
THREC(MAX) = 0.778 x VSUP, THDOM(MAX)
= 0.616 x VSUP, VSUP = 7 V to 18 V, tBIT
= 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2
x tBIT) (See Figure 8-10, Figure 8-11)
Duty Cycle 3 (ISO/DIS 17987 Param
29) (3)
D312V
0.417
0.417
THREC(MAX) = 0.645 x VSUP, THDOM(MAX)
= 0.616 x VSUP, VSUP = 4 V to 7 V, tBIT
=
D312V
Duty Cycle 3 (3)
96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x
tBIT) (See Figure 8-10, Figure 8-11)
THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 μs
D3 = tBUS_rec(min)/(2 x tBIT) (See Figure
8-10, Figure 8-11)
D3
Duty Cycle 3 (1) (2)
0.417
THREC(MIN) = 0.389 x VSUP, THDOM(MIN)
= 0.251 x VSUP, VSUP = 7 V to 18 V, tBIT
= 96 µs (10.4 kbps), D4 =
tBUS_rec(MAX)/(2 x tBIT) (See Figure 8-10,
Figure 8-11)
Duty Cycle 4 (ISO/DIS 17987 Param
30) (3)
D412V
D412V
D4
0.59
0.59
0.59
THREC(MIN) = 0.422 x VSUP, THDOM(MIN)
= 0.284 x VSUP, VSUP = 4 V to 7 V, tBIT
=
Duty Cycle 4 (3)
96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2
x tBIT) (See Figure 8-10, Figure 8-11)
THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
VSUP = 7 V to 18 V, tBIT = 96 μs
D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure
8-10, Figure 8-11)
Duty Cycle 4 (1) (2)
THREC(MAX) = 0.665 x VSUP
THDOM(MAX) = 0.499 x VSUP
VSUP = 5.5 V to 7 V, tBIT = 52 μs
,
,
D1LB
D2LB
D3LB
D4LB
Duty cycle 1 at low battery (1) (2)
Duty cycle 2 at low battery (1) (2)
Duty cycle 3 at low battery (1) (2)
Duty cycle 4 at low battery (1) (2)
0.396
0.396
THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
VSUP = 6.1 V to 7 V, tBIT = 52 μs
0.581
0.581
THREC(MAX) = 0.665 x VSUP
,
THDOM(MAX) = 0.499 x VSUP
VSUP = 5.5 V to 7 V, tBIT = 96 μs
,
THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
VSUP = 6.1 V to 7 V, tBIT = 96 μs
THREC(MAX) = 0.744 x VSUP
,
Transmitter propagation delay timings
for
THDOM(MAX) = 0.581 x VSUP
7 V ≤VSUP ≤18 V, tBIT = 52 μs
tREC(MAX)_D1 - tDOM(MIN)_D1
Tr-d max
Td-r max
Tr-d max
10.8
8.4
µs
µs
µs
the duty cycle (1) (2)
Recessive to dominant
THREC(MAX) = 0.422 x VSUP
,
Transmitter propagation delay timings
for
THDOM(MAX) = 0.284 x VSUP
7 V ≤VSUP ≤18 V, tBIT = 52 μs
tDOM(MAX)_D2 - tREC(MIN)_D2
the duty cycle (1) (2)
Dominant to recessive
THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP
7 V ≤VSUP ≤18 V, tBIT = 96 μs
tREC(MAX)_D3 - tDOM(MIN)_D3
Transmitter propagation delay timings
for
15.9
the duty cycle (1) (2)
Recessive to dominant
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MAX UNIT
7.7 Duty Cycle Characteristics (continued)
parameters valid across -40℃≤TA ≤125℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP
7 V ≤VSUP ≤18 V, tBIT = 96 μs
tDOM(MAX)_D4 - tREC(MIN)_D4
Transmitter propagation delay timings
for
Td-r max
17.28
10.8
8.4
µs
µs
µs
the duty cycle (1) (2)
Dominant to recessive
THREC(MAX) = 0.665 x VSUP
,
Low battery transmitter propagation
delay
THDOM(MAX) = 0.499 x VSUP
5.5 V ≤VSUP ≤7 V, tBIT = 52 μs
tREC(MAX)_low - tDOM(MIN)_low
Tr-d max_low
Td-r max_low
timings for the duty cycle (1) (2)
Recessive to dominant
THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP
6.1 V ≤VSUP ≤7 V, tBIT = 52 μs
tDOM(MAX)_low - tREC(MIN)_low
Low battery transmitter propagation
delay
timings for the duty cycle (1) (2)
Dominant to recessive
(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩand 899 pF/20 kΩ
(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ωand 899 pF/900 Ω
(3) ISO 17987 bus load conditions (CLINBUS, RLINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.
7.8 Switching Characteristics
parameters valid across -40℃≤TA ≤125℃(unless otherwise noted)
SYMBOL
DESCRIPTION
TEST CONDITIONS
MIN
NOM
MAX UNIT
Receiver rising propagation delay time
(ISO/DIS 17987 Param 31)
trx_pdr
6
6
µs
µs
RRXD = 2.4 kΩ, CRXD = 20 pF
(See Figure 8-12 and Figure 8-13 )
Receiver falling propagation delay time
(ISO/DIS 17987 Param 31)
trx_pdf
Rising edge with respect to falling edge,
Symmetry of receiver propagation delay (trx_sym = trx_pdf –trx_pdr), RRXD
time
=
2.4 kΩ, CRXD = 20 pF (See Figure 8-12
and Figure 8-13 )
trs_sym
2
µs
µs
–2
LIN wakeup time (Minimum dominant
time on LIN bus for wakeup)
See Figure 8-16, Figure 9-2, and Figure
9-3
tLINBUS
25
100
150
Time to clear false wakeup prevention
logic if LIN bus had a bus stuck
dominant fault (recessive time on LIN
bus to clear bus stuck dominant fault)
tCLEAR
See Figure 9-3
8
20
2
17
34
50
80
15
µs
ms
µs
tDST
Dominant state time out
Time to change from standby mode to
normal mode or normal mode to sleep
mode through EN pin. See Figure 8-14
and Figure 9-4
tMODE_CHANGE Mode change delay time
Time for normal mode to initialize and
data on RXD pin to be valid. See Figure
8-14
tNOMINT
Normal mode initialization time
Power up time
35
µs
Upon power up time it takes for valid
data on RXD
tPWR
1.5
ms
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7.9 Typical Characteristics
图7-1. VOH vs VSUP and Temperature
图7-2. VOL vs VSUP and Temperature
Normal Mode (Dominant)
Normal Mode (Recessive)
图7-3. Supply Current vs Voltage Supply Across Temperature
图7-4. Supply Current vs Voltage Supply Across Temperature
Standby Mode (Dominant)
Standby Mode (Recessive)
图7-5. Supply Current vs Voltage Supply and Temperature
图7-6. Supply Current vs Voltage Supply and Temperature
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7.9 Typical Characteristics (continued)
Sleep Mode
图7-7. Supply Current vs Voltage Supply and Temperature
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8 Parameter Measurement Information
1, 4
NC 11, 12, 14
10
RXD1/2
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
5 V
2, 5
VSUP
VPS
EN1/2
NC
6
9, 13
LIN1/2
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40ns
Frequency: 20 ppm
TXD1/2
3, 7
8
GND
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
图8-1. Test System: Operating Voltage Range with RX and TX Access: Parameters 9, 10
Delta t = + 5 µs
(tBIT = 50 µs)
Trigger Point
RX
2 x tBIT = 100 µs (20 kBaud)
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图8-2. RX Response: Operating Voltage Range
Period T = 1/f
Amplitude
(signal range)
LIN Bus Input
Frequency: f = 20 Hz
Symmetry: 50%
图8-3. LIN Bus Input Signal
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1, 4
NC
RXD1/2
11, 12, 14
10
Power Supply
Resolution: 10 mV / 1 mA
Accuracy: 0.2%
5 V
2, 5
6
VSUP
VPS
EN1/2
NC
9, 13
8
LIN1/2
GND
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40 ns
Frequency: 20 ppm
3, 7 TXD1/2
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
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图8-4. LIN Receiver Test with RX access Parameters 17, 18, 19, 20
Power Supply 1
Resolution: 10 mV / 1mA
Accuracy: 0.2%
NC
RXD1/2
11, 12, 14
10
1, 4
2, 5
5 V
VPS1
VSUP
EN1/2
NC
D
6
Power Supply 2
Resolution: 10 mV / 1mA
Accuracy: 0.2%
9, 13
LIN1/2
GND
3, 7
TXD1/2
8
VPS2
RBUS
Measurement Tools
O-scope:
DMM
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图8-5. VSUP_NON_OP Parameter 11
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11, 12, 14
10
NC
Power Supply
Resolution: 10mV/ 1mA
Accuracy: 0.2%
1, 4 RXD1/2
VPS
VSUP
2, 5
6
EN1/2
NC
RMEAS = 499 Ω
9, 13
8
LIN1/2
GND
TXD1/2
3, 7
Measurement Tools
O-scope:
DMM
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图8-6. Test Circuit for IBUS_PAS_dom; TXD = Recessive State VBUS = 0 V, Parameter 13
Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
1, 4
RXD1/2
NC 11, 12, 14
VPS1
10
2, 5 EN1/2
VSUP
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
TLINx022
1 kΩ
6
NC
9, 13
VPS2
LIN1/2
GND
VPS2 2 V/s ramp
[8 V à 27 V]
3, 7
TXD1/2
8
V Drop across resistor
< 20 mV
Measurement Tools
O-scope:
DMM
图8-7. Test Circuit for IBUS_PAS_rec Param 14
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Power Supply 1
Resolution: 10mV/ 1mA
Accuracy: 0.2%
11, 12, 14
10
NC
RXD1/2
1, 4
2, 5
5 V
VPS1
VSUP
EN1/2
NC
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
1 kΩ
6
9, 13
8
LIN1/2
GND
VPS2
VPS2 2 V/s ramp
[0 V à 27 V]
3, 7 TXD1/2
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
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图8-8. Test Circuit for IBUS_NO_GND Loss of GND
11, 12, 14
NC
RXD1/2
1, 4
5 V
2, 5
10
VSUP
EN1/2
NC
Power Supply 2
Resolution: 10mV/ 1mA
Accuracy: 0.2%
10 kΩ
6
9, 13
VPS
LIN1/2
VPS 2 V/s ramp
[0 V à 27 V]
3, 7
TXD1/2
8
GND
V Drop across resistor
< 1V
Measurement Tools
O-scope:
DMM
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图8-9. Test Circuit for IBUS_NO_BAT Loss of Battery
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NC 11, 12, 14
10
RXD1/2
1, 4
2, 5
5 V
Power Supply 1
Resolution: 10 mV / 1mA
Accuracy: 0.2%
VSUP
EN1/2
NC
VPS1
RMEAS
6
9, 13
8
LIN1/2
GND
Power Supply 2
Resolution: 10 mV / 1mA
Accuracy: 0.2%
Pulse Generator
VPS2
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40 ns
Frequency: 20 ppm
3, 7
TXD1/2
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
图8-10. Test Circuit Slope Control and Duty Cycle Parameters 27, 28, 29, 30
TBIT
D = 50%
TXD (Input)
D112: 0.744 * VSUP
D312: 0.778 * VSUP
THREC(MAX)
THDOM(MAX)
THREC(MIN)
THDOM(MIN)
Thresholds
RX Node 1
D112: 0.581 * VSUP
D312: 0.616 * VSUP
LIN Bus
Signal
D212: 0.422 * VSUP
D412: 0.389 * VSUP
VSUP
Thresholds
RX Node 2
D212: 0.284 * VSUP
D412: 0.251 * VSUP
tBUS_REC(MIN)
tBUS_DOM(MAX)
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
tBUS_DOM(MIN)
tBUS_REC(MAX)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
图8-11. Definition of Bus Timing Parameters
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VCC
2.4 kΩ
1, 4
2, 5
NC 11, 12, 14
RXD1/2
Power Supply
Resolution: 10 mV / 1mA
Accuracy: 0.2%
5 V
20 pF
10
VSUP
EN1/2
NC
VPS
6
9, 13
8
LIN1/2
GND
Pulse Generator
tR/tF: Square Wave: < 20 ns
tR/tF: Triangle Wave: < 40 ns
Frequency: 20 ppm
3, 7
TXD1/2
Jitter: < 25 ns
Measurement Tools
O-scope:
DMM
Copyright © 2017, Texas Instruments Incorporated
图8-12. Propagation Delay Test Circuit; Parameters 31, 32
D1: 0.744 * VSUP
D3: 0.778 * VSUP
THREC(MAX)
Thresholds
RX Node 1
D1: 0.581 * VSUP
D3: 0.616 * VSUP
THDOM(MAX)
THREC(MIN)
THDOM(MIN)
LIN Bus
Signal
D2: 0.422 * VSUP
D4: 0.389 * VSUP
VSUP
Thresholds
RX Node 2
D2: 0.284 * VSUP
D4: 0.251 * VSUP
RXD: Node 1
D1 (20 kbps)
D3 (10.4 kbps)
trx_pdr(1)
trx_pdf(1)
RXD: Node 2
D2 (20 kbps)
D4 (10.4 kbps)
trx_pdr(2)
trx_pdf(2)
图8-13. Propagation Delay
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Wake Event
tMODE_CHANGE
EN
tMODE_CHANGE
tNOMINT
Transition
Sleep
Standby
Transition
Normal
Normal
MODE
Indetermin
ate Ignore
Mirrors
Bus
Wake Request
RXD = Low
RXD
Floating
Indeterminate Ignore
Mirrors Bus
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图8-14. Mode Transitions
EN1/2
Weak Internal Pulldown
TXD1/2
Weak Internal Pulldown
VSUP
LIN1/2
RXD1/2
MODE
Floating
Sleep
Normal
图8-15. Wakeup Through EN
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0.6 x
VSUP
0.6 x
VSUP
LIN1/2
0.4 x VSUP
VSUP
0.4 x
VSUP
t < tLINBUS
tLINBUS
TXD1/2
Weak Internal Pulldown
EN1/2
Floating
Sleep
RXD1/2
MODE
Standby
Normal
图8-16. Wakeup through LIN
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9 Detailed Description
9.1 Overview
The TLIN1022A-Q1 device is a Dual Local Interconnect Network (LIN) physical layer transceiver, compliant to
LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4 standards, with integrated wake-up and protection
features. The LIN bus is a single wire bidirectional bus typically used for low speed in-vehicle networks. The
device transmitter supports data rates from 2.4 kbps to 20 kbps. The device receiver works up to 100 kbps
supporting in-line programming. The LIN protocol data stream on the TXD input is converted by the TLIN1022A-
Q1 into a LIN bus signal using a current-limited wave-shaping driver as outlined by the LIN physical layer
specification. The receiver converts the data stream to logic-level signals that are sent to the microprocessor
through the open-drain RXD pin. The LIN bus has two states: dominant state (voltage near ground) and
recessive state (voltage near battery). In the recessive state, the LIN bus is pulled high by the internal pull-up
resistor (45 kΩ) and a series diode. No external pull-up components are required for responder node
applications. Commander node applications require an external pull-up resistor (1 kΩ) plus a series diode per
the LIN specification.
The device is designed to support 12-V applications with a wide input voltage operating range and also supports
low-power sleep mode. The device also provides two methods to wake up: EN pin and from the LIN bus.
The TLIN1022A-Q1 integrates ESD protection and fault protection which allow for a reduction in the required
external components in end applications. In the event of a ground shift or supply voltage disconnection, the
device prevents back-feed current through LIN to the supply input. The device also includes undervoltage
detection, temperature shutdown protection, and loss-of-ground protection.
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9.2 Functional Block Diagram
VSUP
NC
RXD1
VSUP/2
Comp
45 kΩ
Filter
Wake Up
State & Control
EN1
Fault Detection
& Protection
LIN1
NC
DR/
Slope
CTL
Dominant
State
Timeout
TXD1
350 kΩ
NC
RXD2
VSUP/2
VSUP
Comp
Filter
45 kΩ
Wake Up
State & Control
EN2
NC
Fault Detection
& Protection
LIN2
DR/
Slope
CTL
Dominant
State
Timeout
TXD2
350 kꢀ
GND
9.3 Feature Description
9.3.1 LIN (Local Interconnect Network) Bus
This high voltage input/output pin is a single wire LIN bus transmitter and receiver. The LIN pin can survive
transient voltages up to 45 V. Reverse currents from the LIN to supply (VSUP) are minimized with blocking
diodes, even in the event of a ground shift or loss of supply (VSUP).
9.3.1.1 LIN Transmitter Characteristics
The transmitter has thresholds and AC parameters according to the LIN specification. The transmitter is a low-
side transistor with internal current limitation and thermal shutdown. During a thermal shutdown condition, the
transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure to
VSUP, so no external pull-up components are required for the LIN responder node applications. An external pull-
up resistor and series diode to VSUP must be added when the device is used for a commander node application.
9.3.1.2 LIN Receiver Characteristics
The receiver characteristic thresholds are proportional to the device supply pin according to the LIN
specification.
The receiver is capable of receiving higher data rates (> 100 kbps) than supported by LIN or SAE J2602
specifications. This allows the TLIN1022A-Q1 to be used for high speed downloads at the end-of-line production
or other applications. The actual data rate achievable depends on system time constants (bus capacitance and
pull-up resistance) and driver characteristics used in the system.
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9.3.1.2.1 Termination
There is an internal pull-up resistor with a serial diode structure to VSUP, so no external pull-up components are
required for the LIN responder node applications. An external pull-up resistor (1 kΩ) and a series diode to VSUP
must be added when the device is used for commander node applications as per the LIN specification.
图9-1 shows a commander node configuration and how the voltage levels are defined
Voltage drop across the
Simplified Transceiver
VLIN_Bus
diodes in the pullup path
RXD
VSUP
VSUP
VSUP/2
VBattery
VSUP
VLIN_Recessive
Receiver
Filter
1 kΩ
45 kΩ
LIN
LIN
Bus
TXD
350 kΩ
GND
Transmitter
with slope control
VLIN_Dominant
t
Copyright © 2017, Texas Instruments Incorporated
图9-1. Commander Node Configuration with Voltage Levels
9.3.2 TXD
TXD is the interface to the MCU's LIN protocol controller or SCI / UART that is used to control the state of the
LIN output. When TXD is low the LIN output is dominant (near ground). When TXD is high the LIN output is
recessive (near VBattery). See 图 9-1. The TXD input structure is compatible with processors using 3.3 V and 5 V
I/O. TXD has an internal pull-down resistor. The LIN bus is protected from being stuck dominant through a
system failure driving TXD low through the dominant state timeout timer.
9.3.3 RXD (Receive Output)
RXD is the interface to the MCU's LIN protocol controller or SCI / UART, which reports the state of the LIN bus
voltage. LIN recessive (near VBattery) is represented by a high level on the RXD and LIN dominant (near ground)
is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage. This
allows the device to be used with 3.3 V and 5 V I/O processors. If the microcontroller’s RXD pin does not have
an integrated pull-up, an external pull-up resistor to the processors I/O supply voltage is required. In standby
mode the RXD pin is driven low to indicate a wake up request from the LIN bus.
9.3.4 VSUP (Supply Voltage)
VSUP is the power supply pin. VSUP is connected to the battery through an external reverse battery blocking
diode (see 图 9-1 ). If there is a loss of power at the ECU level, the device has low leakage from the LIN pin,
which does not load the bus down. This is optimal for LIN systems in which some of the nodes are unpowered
(ignition supplied) while the rest of the network remains powered (battery supplied).
9.3.5 GND (Ground)
GND is the device ground connection. The device can operate with a ground shift as long as the ground shift
does not reduce the VSUP below the minimum operating voltage, as well as ensuring the input and output
voltages are within their appropriate thresholds. If there is a loss of ground at the ECU level, the device has
extremely low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in
which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered
(battery supplied).
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9.3.6 EN (Enable Input)
EN1 and EN2 control the operational modes of the respective LIN channel . When EN1/EN2 is high the LIN1/
LIN2 channel is in normal operating mode allowing a transmission path from TXD to respective LIN bus and from
LIN to RXD. When EN1/EN2 is low the LIN1/LIN2 channel is put into sleep mode and there is no transmission
path available. The channel can enter normal mode only after wake up. EN has an internal pull-down resistor to
ensure the channel remains in low power mode even if EN floats.
9.3.7 Protection Features
The TLIN1022A-Q1 has several protection features.
9.3.8 TXD Dominant Time Out (DTO)
During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application
failure, the LIN bus is protected by the dominant state timeout timer. This timer is triggered by a falling edge on
the TXD pin. If the low signal remains on TXD for longer than tDST, the transmitter is disabled, thus allowing the
LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and the
tDST timer is reset by a rising edge on TXD. The TXD pin has an internal pull-down to ensure the LIN channel
fails to a known state if TXD is disconnected. During this fault, the LIN channel remains in normal mode
(assuming no change of state request on EN), the transmitter is disabled, the RXD pin reflects the LIN bus and
the LIN bus pull-up termination remains on.
9.3.9 Bus Stuck Dominant System Fault: False Wake Up Lockout
The TLIN1022A-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from
waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus.
If the bus is dominant, the wake-up logic is locked out until a valid recessive on the bus “clears”the bus stuck
dominant, preventing excessive current use. 图9-2 and 图9-3 show the behavior of this protection.
RXD
EN
LIN Bus
tLINBUS
< tLINBUS
< tLINBUS
图9-2. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wakeup
RXD
EN
tLINBUS
tLINBUS
tLINBUS
LIN Bus
tCLEAR
< tCLEAR
图9-3. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wakeup
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9.3.10 Thermal Shutdown
The LIN transmitter is protected by limiting the current; however if the junction temperature of the device
exceeds the thermal shutdown threshold, the device puts the LIN transmitter into the recessive state. Once the
over-temperature fault condition has been removed and the junction temperature has cooled beyond the
hysteresis temperature, the transmitter is re-enabled, assuming the device remained in the normal operation
mode. During this fault, the transceiver remains in normal mode (assuming no change of state request on EN),
the transmitter is in recessive state, the RXD pin reflects the LIN bus and LIN bus pull-up termination remains
on.
9.3.11 Undervoltage on VSUP
The TLIN1022A-Q1 contains a power on reset circuit to avoid false bus messages during undervoltage
conditions when VSUP is less than UVSUP
.
9.3.12 Unpowered Device and LIN Bus
In automotive applications some LIN nodes in a system can be unpowered (ignition supplied) while others in the
network remain powered by the battery. The TLIN1022A-Q1 has a low unpowered leakage current from the bus
so an unpowered node does not affect the network or load it down.
9.4 Device Functional Modes
The TLIN1022A-Q1 has three functional modes of operation; normal, sleep, and standby. The next sections
describe these modes as well as how the device moves between the different modes. 图 9-4 graphically shows
the relationship while 表9-1 shows the state of pins.
表9-1. Operating Modes
LIN BUS
TERMINATION
MODE
Sleep
EN
Low
Low
RXD
Floating
Low
TRANSMITTER
COMMENT
Weak Current Pullup
Off
Off
Wake up event detected,
waiting on MCU to set EN
Standby
45 kΩ (typical)
45 kΩ (typical)
LIN Bus
Data
Normal
High
Off
LIN transmission up to 20 kbps
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Unpowered System
VSUP < VSUP_UNDER
VSUP < VSUP_UNDER
VSUP > VSUP_UNDER
EN = Low
VSUP < VSUP_UNDER
VSUP > VSUP_UNDER
EN = High
VSUP < VSUP_UNDER
Standby Mode
Driver: Off
RXD: Low
Termination: 45 kΩ
EN = High
LIN Bus Wake up
Normal Mode
Sleep Mode
Driver: On
RXD: LIN Bus Data
Termination: 45 kΩ
Driver: Off
RXD: Floating
Termination: Weak pullup
EN = Low
EN = High
Copyright © 2017, Texas Instruments Incorporated
图9-4. Operating State Diagram
9.4.1 Normal Mode
If the EN1 or EN2 pin is high at power up, the channel powers up in normal mode. If EN1 or EN2 is low, the
channel powers up in standby mode. The EN pin controls the mode of the channel. In normal operational mode,
the receiver and transmitter are active and the LIN transmission up to the LIN specified maximum of 20 kbps is
supported. The receiver detects the data stream on the LIN bus and outputs it on RXD for the LIN controller. A
recessive signal on the LIN bus is a logic high and a dominant signal on the LIN bus is a logic low. The driver
transmits input data from TXD to the LIN bus. Normal mode is entered as EN transitions high while the LIN
channel is in sleep or standby mode for > tMODE_CHANGE plus tNOMINT
.
9.4.2 Sleep Mode
Sleep Mode is the power saving mode for the TLIN1022A-Q1. Even with extremely low current consumption in
this mode, the LIN channel can still wake-up from LIN bus through a wake-up signal or if EN is set high for
≥tMODE_CHANGE. The LIN bus is filtered to prevent false wake-up events. The wake-up events must be active for
the respective time periods (tLINBUS).
Sleep mode is entered by setting EN low for longer than tMODE_CHANGE
While the channel is in sleep mode, the following conditions exist.
.
• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if
LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake-up events
in case an external connection to the LIN bus is lost.
• The normal receiver is disabled.
• EN input and LIN wake-up receiver are active.
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9.4.3 Standby Mode
This mode is entered whenever a wake-up event occurs through the LIN bus while the channel is in sleep mode.
The LIN bus responder termination circuit is turned on when standby mode is entered. Standby mode is signaled
through a low level on RXD. See Standby Mode Application Note for more application information.
When EN is set high for longer than tMODE_CHANGE while the channel is in standby mode, the device returns to
normal mode and the normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.
9.4.4 Wake-Up Events
There are two ways to wake-up from sleep mode:
• Remote wake-up initiated by the falling edge of a recessive (high) to dominant (low) state transition on LIN
bus where the dominant state is held for tLINBUS filter time. After this tLINBUS filter time has been met and a
rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake-up event,
eliminating false wake-ups from disturbances on the LIN bus or if the bus is shorted to ground.
• Local wake-up through EN being set high for longer than tMODE_CHANGE
.
9.4.4.1 Wake-Up Request (RXD)
When the TLIN1022A-Q1 encounters a wake-up event from the LIN bus, RXD goes low and the channel
transitions to standby mode until EN is reasserted high and the channel enters normal mode. Once the LIN
channel enters normal mode, the RXD pin releases the wake-up request signal and the RXD pin then reflects
the receiver output from the correponding LIN bus.
9.4.4.2 Mode Transitions
When any of the LIN channel of TLIN1022A-Q1 is transitioning between modes, the device needs the time,
tMODE_CHANGE, to allow the change to fully propagate from the EN pin through the channel into the new state.
When transitioning from sleep or standby mode to normal mode, the transition time is the sum of tMODE_CHANGE
and tNOMINT
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10 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TLIN1022A-Q1 can be used as both a responder node device and a commander node device in a LIN
network. The device comes with the ability to support both remote wake-up request and local wake-up request.
10.2 Typical Application
The device comes with an integrated 45 kΩ pull-up resistor and series diode for responder node applications.
For commander node applications, an external 1 kΩ pull-up resistor with series blocking diode can be used. 图
10-1 shows the device being used in both commander mode and responder mode applications.
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COMMANDER NODE
VBAT
VSUP
VREG
VSUP
VDD
VSUP
VDD
NC NC NC
11 12 14
(4)
Commander
Node
Pullup(3)
1 kΩ
EN1
10
VDD
I/O
2
VDD I/O
MCU w/o
pullup(2)
LIN1
MCU
13
1
3
220 pF
RXD1
TXD1
TLIN1022A
LIN Controller
Or
SCI/UART(1)
VDD I/O
LIN2
MCU w/o
pullup(2)
9
220 pF
4
7
RXD2
TXD2
EN2
5
I/O
GND
6
8
NC
RESPONDER NODE
VBAT
VSUP
VREG
VSUP
VDD
VSUP
VDD
NC NC NC
11 12 14
(4)
EN1
10
VDD
I/O
2
VDD I/O
MCU w/o
pullup(2)
LIN1
MCU
13
220 pF
1
3
RXD1
TXD1
TLIN1022A
LIN Controller
Or
SCI/UART(1)
VDD I/O
LIN2
MCU w/o
pullup(2)
9
220 pF
4
7
RXD2
TXD2
EN2
5
I/O
GND
6
8
NC
A. If RXD on MCU or LIN responder has internal pullup; no external pullup resistor is needed.
B. If RXD on MCU or LIN responder does not have an internal pullup requires external pullup resistor
C. Commander node applications require and external 1 kΩ pullup resistor and serial diode.
D. Decoupling capacitor values are system dependent but usually have 100 nF, 1 µF and ≥10 µF
图10-1. Typical LIN Bus
10.2.1 Design Requirements
The RXD output structure is an open-drain output stage. This allows the TLIN1022A-Q1 to be used with 3.3-V
and 5-V I/O processor. If the RXD pin of the processor does not have an integrated pull-up, an external pull-up
resistor to the processor I/O supply voltage is required. The select external pull-up resistor value should be
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between 1 kΩ to 10 kΩ, depending on supply used (See IOL in electrical characteristics). The VSUP pin of the
device should be decoupled with a 100 nF capacitor by placing it close to the VSUP supply pin. The system
should include additional decoupling on the VSUP line as needed per the application requirements.
10.2.2 Detailed Design Procedures
10.2.2.1 Normal Mode Application Note
When using the TLIN1022A-Q1 in systems which are monitoring the RXD pin for a wake up request, special
care should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition
period between states as the receivers are switched. The application software should not look for an edge on the
RXD pin indicating a wake up request until tMODE_CHANGE . This is shown in 图8-14.
10.2.2.2 Standby Mode Application Note
If the TLIN1022A-Q1 detects an undervoltage on VSUP the RXD pin transitions low, and signals to the software
that the TLIN1022A-Q1 is in standby mode and should be returned to sleep mode for the lowest power state.
10.2.2.3 TXD Dominant State Timeout Application Note
The maximum dominant TXD time allowed by the TXD dominant state time out limits the minimum possible data
rate of the device. The LIN protocol has different constraints for commander and responder applications thus
there are different maximum consecutive dominant bits for each application case and thus different minimum
data rates.
10.2.3 Application Curves
图 10-2 and 图 10-3 show the propagation delay from the TXD pin to the LIN pin for both dominant to recessive
and recessive to dominant edges. Waveforms are for 1 channel of the device configured in commander mode
with external pull-up resistor (1 kΩ) and 680 pF bus capacitance.
图10-2. Dominant to Recessive Propagation
图10-3. Recessive to Dominant Propagation
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Power Supply Recommendations
The TLIN1022A-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 4 V
to 36 V. A 100 nF decoupling capacitor should be placed as close to the VSUP pin of the device as possible. It is
good practice for some applications with noisier supplies to include 1 μF and 10 μF decoupling capacitor.
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11 Layout
In order for the PCB design to be successful, start with the design of the protection and filtering circuitry.
Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high
frequency layout techniques must be applied during PCB design. Placement at the connector also prevents
these noisy events from propagating further into the PCB and system.
11.1 Layout Guidelines
• Pin 1, 4 (RXD1/2): The pin is an open-drain outputs and require an external pull-up resistor in the range of 1
kΩ and 10 kΩ to function properly. If the microprocessor paired with the transceiver does not have an
integrated pull-up, an external resistor should be placed between RXD and the regulated voltage supply for
the microprocessor.
• Pin 2, 5 (EN1/2): EN is an input pin that is used to place the device in a low power sleep mode. If this feature
is not used, the pin should be pulled high to the regulated voltage supply of the microprocessor through a
series resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may be placed on the pin to
limit current on the digital lines in the event of an over voltage fault.
• Pin 6 (NC): Not Connected.
• Pin 3, 7 (TXD1/2): The TXD pins are the transmitter input signals to the device from the processor. A series
resistor can be placed to limit the input current to the device in the case of an over-voltage on this pin. A
capacitor to ground can be placed close to the input pin of the device to filter noise.
• Pin 8 (GND): This is the ground connection for the device. This pin should be tied to the ground plane
through a short trace with the use of two vias to limit total return inductance.
• Pin 9, 13 (LIN1/2): This pin connects to the LIN bus. For responder node applications, a 220 pF capacitor to
ground is implemented. For commander node applications and additional series resistor, a blocking diode
should be placed between the LIN pin and the VSUP pin. See 图10-1.
• Pin 10 (VSUP): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed as close
to the device as possible.
• Pin 11, 12 and 14 (NC): Not Connected.
Note
All ground and power connections should be made as short as possible and use at least two vias to
minimize the total loop inductance.
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11.2 Layout Example
VDD
VSUP
RXD1
NC 14
1
2
3
4
5
6
7
RXD1
Only needed for
the Commander
node
U1
VDD
LIN1
R2
EN1
LIN1 13
EN1
TXD1
RXD2
EN2
GND
GND
R4
TXD1
RXD2
EN2
NC
12
VDD
11
NC
VDD
VSUP
R6
10
C5
VSUP
LIN2
GND
GND
Only needed for
the Commander
node
D1
LIN2
NC
9
GND
GND
TXD2
8
TXD2
R8
GND
图11-1. Layout Example
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12 Device and Documentation Support
This device will conform to the following LIN standards. The core of what is needed is covered within this system
spec, however reference should be made to these standards and any discrepancies pointed out and discussed.
This document should provide all the basics of what is needed.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• LIN Standards:
– ISO/DIS 17987-1: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and
use case definition
– ISO/DIS 17987-4: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer
(EPL) specification 12V/24V
– SAEJ2602-1: LIN Network for Vehicle Applications
– LIN2.0, LIN2.1, LIN2.2 and LIN2.2A specification
• EMC requirements:
– SAEJ2962-1
– ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge
– ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband
radiated electromagnetic energy - Part 4: Harness excitation methods
– ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1:
Definitions and general considerations
– ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical
transient transmission by capacitive and inductive coupling via lines other than supply lines
– IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz -
Part 4: Direct RF power injection method
– IEC 61000-4-2
– IEC 61967-4
– CISPR25
• Conformance Test requirements:
– ISO/DIS 17987-7: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer
(EPL) conformance test specification
– SAEJ2602-2: LIN Network for Vehicle Applications Conformance Test
•
12.2 接收文档更新通知
要接收文档更新通知,请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册,即可每周接收产品信息更
改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料,可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范,并且不一定反映 TI 的观点;请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
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12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLIN1022ADMTRQ1
TLIN1022ADRQ1
ACTIVE
ACTIVE
VSON
SOIC
DMT
D
14
14
3000 RoHS & Green
2500 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
T022A
(TL022, TL022A)
Samples
Samples
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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23-Jun-2023
Addendum-Page 2
GENERIC PACKAGE VIEW
DMT 14
3 x 4.5, 0.65 mm pitch
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225088/A
www.ti.com
PACKAGE OUTLINE
DMT0014A
VSON - 0.9 mm max height
SCALE 3.200
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.05)
SECTION A-A
SCALE 30.000
SECTION A-A
TYPICAL
C
0.9 MAX
SEATING PLANE
0.08 C
0.05
0.00
1.6 0.1
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
7
8
A
A
2X
3.9
15
SYMM
4.2 0.1
14
1
12X 0.65
0.35
0.25
14X
0.45
0.35
14X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
4223033/B 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DMT0014A
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
14X (0.6)
14X (0.3)
SYMM
1
14
2X
(1.85)
12X (0.65)
SYMM
15
(4.2)
(0.69)
TYP
(
0.2) VIA
TYP
8
7
(R0.05) TYP
(0.55) TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223033/B 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DMT0014A
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.47)
15
14X (0.6)
1
14
14X (0.3)
(1.18)
12X (0.65)
SYMM
(1.38)
(R0.05) TYP
METAL
TYP
8
7
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15
77.4% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4223033/B 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DMT0014B
VSON - 1 mm max height
SCALE 3.200
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.13)
1.0
0.8
SECTION A-A
SCALE 30.000
SECTION A-A
TYPICAL
C
SEATING PLANE
0.08 C
0.05
0.00
1.6 0.1
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
7
8
(0.19) TYP
A
A
2X
3.9
15
SYMM
4.2 0.1
14
1
12X 0.65
0.35
0.25
14X
0.45
0.35
PIN 1 ID
14X
0.1
C A B
(OPTIONAL)
0.05
C
4225087/B 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DMT0014B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
14X (0.6)
14X (0.3)
SYMM
1
14
2X
(1.85)
12X (0.65)
SYMM
15
(4.2)
(0.69)
TYP
(
0.2) VIA
TYP
8
7
(R0.05) TYP
(0.55) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225087/B 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DMT0014B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.47)
15
14X (0.6)
1
14
14X (0.3)
(1.18)
12X (0.65)
SYMM
(1.38)
(R0.05) TYP
METAL
TYP
8
7
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15
77.4% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4225087/B 01/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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