TLIN2024ARGYRQ1 [TI]

具有显性状态的汽车类四路本地互连网络 (LIN) 收发器 | RGY | 24 | -40 to 125;


型号：	TLIN2024ARGYRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有显性状态的汽车类四路本地互连网络 (LIN) 收发器 \| RGY \| 24 \| -40 to 125
文件：	总37页 (文件大小：2691K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLIN2024A-Q1

ZHCSNE4 –JUNE 2022

TLIN2024A-Q1 具有显性状态超时的

四路本地互连网络(LIN) 收发器

1 特性

2 应用

• 符合面向汽车应用的AEC-Q100（1 级）标准

• 符合LIN 2.0、LIN 2.1、LIN 2.2、LIN2.2A 和

ISO/DIS 17987–4 电气物理层(EPL) 规格标准

• 符合SAE J2602-1 面向汽车应用的LIN 网络标准

• 提供功能安全

• 车身电子装置和照明

• 混合动力电动汽车和动力总成系统

• 信息娱乐系统与仪表组

• 电器

3 说明

– 可帮助进行功能安全系统设计的文档

• 支持12V 和24V 电池应用

• LIN 传输数据速率高达20kbps

• LIN 接收数据速率高达100kbps

• 宽工作电源电压范围：4 V 至48 V

• 睡眠模式：超低电流消耗支持以下类型的唤醒事

件：

TLIN2024A-Q1 器件是一款四路本地互连网络 (LIN) 物

理层收发器，集成了唤醒和保护功能，符合 LIN 2.0、

LIN 2.1、LIN 2.2、LIN 2.2A 和 ISO/DIS 17987–4 标

准。LIN 是一根单线制双向总线，通常用于低速车载网

络，数据传输速率高达 20kbps。TLIN2024A-Q1 旨在

为 12V 和 24V 应用提供支持，具有更宽的工作电压范

围和额外的总线故障保护。该器件具有两个独立的双路

LIN 收发器模块。V_SUP1/2可控制独立的双路收发器模

块。

– LIN 总线

– 通过EN 引脚实现本地唤醒

• 集成45kΩLIN 上拉电阻器

• 在LIN 总线和RXD 输出上实现上电和断电无干扰

运行

TLIN2024A-Q1 接收器支持高达 100kbps 的数据速

率，从而更快速地执行内联编程。该器件通过使用可降

低电磁发射 (EME) 的限流波形整形驱动器，将TXD 输

入上的 LIN 协议数据流转化为 LIN 总线信号。接收器

将数据流转化为逻辑电平信号，此信号通过开漏 RXD

引脚发送到微处理器。睡眠模式可实现超低电流消耗，

该模式允许通过LIN 总线或EN 引脚实现唤醒。

• 保护特性：

– ±60V LIN 总线容错

– V_SUP欠压保护

– TXD 显性超时(DTO) 保护

– 热关断保护

– 系统级未供电节点或接地断开失效防护。

• 3.5mm × 5.5mm VQFN 封装，提高了自动光学检测

(AOI) 能力

器件信息

封装⁽¹⁾

封装尺寸（标称值）

器件型号

TLIN2024A-Q1

VQFN (24)

3.50mm × 5.50mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

空白

Node 1

Commander

Node 2

Node 3

Node n

MCU or DSP

LIN

Controller

TLIN2024A

TLIN1022A

TLIN1029A

LIN Bus

24V - V_BAT

简化版原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSFM7

TLIN2024A-Q1

ZHCSNE4 –JUNE 2022

www.ti.com.cn

Table of Contents

9.1 Overview...................................................................19

9.2 Functional Block Diagram.........................................20

9.3 Feature Description...................................................20

9.4 Device Functional Modes..........................................24

10 Application and Implementation Disclaimer.............26

10.1 Application Information........................................... 26

10.2 Typical Application.................................................. 26

10.3 Power Supply Recommendations...........................28

10.4 Layout..................................................................... 28

11 Device and Documentation Support..........................30

11.1 Documentation Support.......................................... 30

11.2 接收文档更新通知................................................... 30

11.3 支持资源..................................................................30

11.4 Trademarks............................................................. 30

11.5 术语表..................................................................... 30

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 说明（续）.........................................................................2

6 Pin Configuration and Functions...................................3

7 Specifications.................................................................. 4

7.1 Absolute Maximum Ratings........................................ 4

7.2 ESD Ratings............................................................... 4

7.3 ESD Ratings - IEC...................................................... 4

7.4 Thermal Information....................................................5

7.5 Recommended Operating Conditions.........................5

7.6 Electrical Characteristics.............................................6

7.7 Duty Cycle Characteristics..........................................8

7.8 Switching Characteristics..........................................10

8 Parameter Measurement Information.......................... 11

9 Detailed Description......................................................19

Information.................................................................... 31

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

June 2022

Initial release

5 说明（续）

TLIN2024A-Q1 集成了适用于LIN 响应者节点应用的电阻器，还集成了ESD 保护和故障保护功能，有助于减少应

用中的外部元件数量。一旦发生接地漂移或电源电压断开，该器件可防止反馈电流经LIN 流向电源输入。器件还

包含欠压保护、过热关断保护和接地失效保护功能。

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6 Pin Configuration and Functions

EN1

TXD1

RXD2

EN2

LIN1

V_SUP1

LIN2

GND1

Thermal

Pad

TXD2

RXD3

EN3

LIN3

V_SUP2

LIN4

GND2

TXD3

RXD4

EN4

图6-1. RGY Package, 24-Pin RGY (VQFN)

(Top View)

表6-1. Pin Functions

TYPE⁽¹⁾

DESCRIPTION

NAME

RXD1

EN1

NO.

Channel 1 RXD Output (open-drain) interface reporting state of LIN1 bus voltage

Channel 1 Enable Input

TXD1

RXD2

EN2

Channel 1 TXD input interface to control state of LIN output

Channel 2 RXD Output (open-drain) interface reporting state of LIN2 bus voltage

Channel 2 Enable Input

TXD2

RXD3

EN3

Channel 2 TXD input interface to control state of LIN2 output

Channel 3 RXD Output (open-drain) interface reporting state of LIN3 bus voltage

Channel 3 Enable Input

TXD3

RXD4

EN4

Channel 3 TXD input interface to control state of LIN3 output

Channel 4 RXD Output (open-drain) interface reporting state of LIN4 bus voltage

Channel 4 Enable Input

TXD4

GND2

LIN4

Channel 4 TXD input interface to control state of LIN4 output

Ground pin for Channels 3 and 4

I/O

Supply

I/O

Channel 4 LIN Bus single-wire transmitter and receiver

V_SUP2

LIN3

Channels 3 and 4 Supply Voltage (connected to battery in series with external reverse blocking diode)

Channel 3 LIN Bus single-wire transmitter and receiver

GND1

LIN2

Ground pin for Channels 1 and 2

I/O

Supply

I/O

–

Channel 2 LIN Bus single-wire transmitter and receiver

V_SUP1

LIN1

Channels 1 and 2 Supply Voltage (connected to battery in series with external reverse blocking diode)

Channel 1 LIN Bus single-wire transmitter and receiver

13, 18, 23, 24

Not Connected

Thermal Pad

Can be connected to the PCB ground plane to improve thermal coupling

–

(1) I = Input, O = Output, I/O = Input or Output, G = Ground.

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7 Specifications

7.1 Absolute Maximum Ratings

(1) (2)

Symbol

Parameter

MIN

–0.3

–60

–0.3

MAX

UNIT

V_SUP

V_LIN

Supply voltage range (ISO/DIS 17987 Param 10)

LIN bus input voltage (ISO/DIS 17987 Param 82)

Logic pin voltage (RXD, TXD, EN)

Logic pin output current

V_LOGIC

I_O

°C

T_J

Junction temperature range

150

–55

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to ground terminal.

7.2 ESD Ratings

ESD Ratings

VALUE

UNIT

Human body model (HBM) classification level 3A: TXD, RXD,

EN Pins, per AEC Q100-002⁽¹⁾

±4000

Human body model (HBM) classification level 3B: LIN and V_SUP

Pin with respect to ground

±8000

±1500

V_(ESD)

Electrostatic discharge

Charged device model (CDM)

classification level C5, per AEC All pins

Q100-011

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 ESD Ratings - IEC

ESD and Surge Protection Ratings

VALUE

UNIT

IEC 62228-2 per ISO 10605

Contact discharge

R = 330 Ω, C = 150 pF

Electrostatic discharge, LIN, V_SUPto

GND⁽¹⁾

V_(ESD)

±8000

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7.3 ESD Ratings - IEC (continued)

ESD and Surge Protection Ratings

VALUE

UNIT

IEC 62228-2 per IEC 62215-3

12 V electrical systems

Pulse 1

–100

IEC 62215-3

24 V electrical systems ⁽²⁾

Pulse 1

–450

IEC 62228-2 per IEC 62215-3

12 V electrical systems

24 V electrical systems ⁽²⁾

Pulse 2

ISO 7637-2 and IEC 62228-2 per IEC

62215-3 transients according to IBEE LIN IEC 62228-2 per IEC 62215-3

V_TRAN

EMC test specifications ⁽²⁾(LIN, V_SUPto

GND )

12 V electrical systems

Pulse 3a

–150

-225

100

IEC 62215-3

24 V electrical systems ⁽²⁾

Pulse 3a

IEC 62228-2 per IEC 62215-3

12 V electrical systems

Pulse 3b

IEC 62215-3

24 V electrical systems ⁽²⁾

Pulse 3b

225

(1) Results given here are specific to the IEC 62228-2 Integrated circuits –EMC evaluation of transceivers –Part 2: LIN transceivers.

Testing performed by OEM approved independent 3rd party, EMC report available upon request.

(2) Verified during characterization.

7.4 Thermal Information

TLIN2024A

THERMAL METRIC⁽¹⁾

RGY (QFN)

24-PINS

34.3

UNIT

R_ΘJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_ΘJC(top)

R_ΘJB

30.8

13.3

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.5

Ψ_JT

13.3

Ψ_JB

R_ΘJC(bot)

2.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

7.5 Recommended Operating Conditions

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER - DEFINITION

MIN

NOM

MAX

UNIT

V_SUP1/2

V_LINx

V_LOGIC

T_A

Supply voltage

LIN Bus input voltage

Logic Pin Voltage (RXDx, TXDx, ENx)

Ambient temperature range

Thermal shutdown rising threshold

Thermal shutdown hysteresis

5.25

125

-40

165

°C

TSD

TSD_(HYS)

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MAX UNIT

7.6 Electrical Characteristics

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

Power Supply

Device is operational beyond the LIN

defined nominal supply voltage range;

See Figure 8-1 and Figure 8-2

Operational supply voltage (ISO/DIS

17987 Param 10)

V_SUP1/2

Normal and Standby Modes: ramp V_SUP

while LIN signal is a 10 kHz square

wave with 50 % duty cycle and 36V

swing; See Figure 8-1 and Figure 8-2

Nominal supply voltage (ISO/DIS 17987

Param 10)

V_SUP1/2

Sleep Mode

UV_SUP

UV_HYS

Under voltage V_SUPthreshold

2.9

3.85

Delta hysteresis voltage for V_SUPunder

voltage threshold

0.2

1.2

Normal Mode: EN = High, bus

dominant: total bus load where R_LIN

500 Ωand C_LIN< 10 nF

8.5

I_SUP

Supply current ⁽⁶⁾

Standby Mode: EN = Low, bus

dominant: total bus load where R_LIN

500 Ωand C_LIN< 10 nF

1.1

3.75

Normal Mode: EN = High, Bus

Recessive: LIN = V_SUP

670

1600

µA

Standby Mode: EN = Low, Bus

Recessive LIN = V_SUP

I_SUP

Supply current ⁽⁶⁾

Sleep Mode: 4.0 V < V_SUP< 14 V, LIN =

V_SUP, EN = 0 V, TXD and RXD Floating

Sleep Mode: 14 V < V_SUP< 36 V, LIN =

V_SUP, EN = 0 V, TXD and RXD floating

RXDx OUTPUT PIN (OPEN DRAIN)

(4)

V_OL

I_OL

Output Low voltage

Based upon External pull up to V_CC

0.6

Low level output current, open drain

Leakage current, high-level

LIN = 0 V, RXD = 0.4 V

LIN = V_SUP, RXD = 5 V

1.5

µA

I_ILG

–5

TXDx INPUT PIN

V_IL

V_IH

Low level input voltage

0.8

–0.3

High level input voltage

5.25

Input threshold voltage, normal modes

& selective wake modes

V_HYS

500

I_ILG

Low level input leakage current

Internal pull-down resistor value

TXD = Low

µA

–5

R_TXD

125

350

800

kΩ

ENx INPUT PIN

V_IL

Low level input voltage

High level input voltage

Hysteresis voltage

0.8

5.25

500

–0.3

V_IH

V_HYS

I_ILG

By design and characterization

EN = Low

µA

Low level input current

Internal Pulldown resistor

–5

R_EN

125

350

800

kΩ

LINx PIN

TXD = high, I_O= 0 mA, 7 V ≤V_SUP

≤

LIN recessive high-level output voltage

V_OH

0.85

V_SUP

(3)

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7.6 Electrical Characteristics (continued)

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TXD = high, I_O= 0 mA, 7 V ≤V_SUP

≤

LIN recessive high-level output voltage

V_OH

0.8

V_SUP

(1) (2)

LIN recessive high-level output voltage

TXD = high, I_O= 0 mA, 4 V ≤

V_SUP< 7 V

V_OH

(3)

V_OL

LIN dominant low-level output voltage ⁽³⁾

0.2 V_SUP

TXD = low, 7 V ≤V_SUP≤48 V

TXD = low, 7 V ≤V_SUP≤18 V

TXD = low, 4 V ≤V_SUP< 7 V

TXD & RXD open, LIN = 4 V to 58 V

LIN dominant low-level output voltage ⁽¹⁾

V_OL

(2)

V_OL

LIN dominant low-level output voltage ⁽³⁾

1.2

V_SUPwhere impact of recessive LIN bus

< 5% (ISO/DIS 17987 Param 11)

V_{SUP_NON_OP}

–0.3

Limiting current (ISO/DIS 17987 Param

57)

TXD = 0 V, V_LIN= 48 V, R_MEAS= 440 Ω,

V_SUP= 48 V, V_BUSdom< 4.518 V

I_{BUS_LIM}

120

300

µA

Receiver leakage current, dominant

(ISO/DIS 17987 Param 13)

LIN = 0 V, V_SUP= 24 V Driver off/

recessive; See Figure 8-6

I_{BUS_PAS_dom}

I_{BUS_PAS_rec1}

I_{BUS_PAS_rec2}

I_{BUS_NO_GND}

–2

Receiver leakage current, recessive

(ISO/DIS 17987 Param 14)

LIN > V_SUP, 8 V ≤V_SUP≤48 V, Driver

off; See Figure 8-7

Receiver leakage current, recessive

(ISO/DIS 17987 Param 14)

LIN = V_SUP, Driver off; See Figure 8-7

µA

–5

–2

Leakage current, loss of ground

(ISO/DIS 17987 Param 60)

GND = V_SUP, 0 V ≤V_LIN< 36 V, V_SUP

24 V; Figure 8-8

V_SUP= 8 V, GND = open, V_SUP= 18 V,

GND = open

R_Commander= 1 kΩ, C_L= 1 nF

R_Responder= 20 kΩ, C_L= 1 nF

LIN = dominant

I_{leak gnd(dom)}

Leakage current, loss of ground ⁽⁵⁾

–1

V_SUP= 8 V, GND = open, V_SUP= 18 V,

GND = open

R_Commander= 1 kΩ, C_L= 1 nF

R_Responder= 20 kΩ, C_L= 1 nF

LIN = recessive

I_{leak gnd(rec)}

-100

100

µA

Leakage current, loss of supply

(ISO/DIS 17987 Param 61)

0 V ≤V_LIN≤48 V, V_SUP= GND;

See; Figure 8-9

I_{BUS_NO_BAT}

LIN dominant (including LIN dominant

for wake-up); See Figure 8-4 and Figure

8-3

Low level input voltage (ISO/DIS 17987

Param 62) ⁽³⁾

V_BUSdom

0.4 V_SUP

High level input voltage (ISO/DIS 17987 LIN recessive; See Figure 8-4 and

V_BUSrec

V_IH

0.6

0.47

0.4

V_SUP

0.6 V_SUP

Param 63) ⁽³⁾

Figure 8-3

LIN recessive high-level input voltage ⁽¹⁾

7 V ≤V_SUP≤18 V

(2)

LIN dominant low-level input voltage ⁽¹⁾

V_IL

0.53 V_SUP

0.525 V_SUP

0.175 V_SUP

7 V ≤V_SUP≤18 V

(2)

Receiver center threshold (ISO/DIS

17987 Param 64)

V_{BUS_CNT}= (V_BUSdom+ V_BUSrec)/2 See

Figure 8-4 and Figure 8-3

V_{BUS_CNT}

V_HYS

0.475

0.5

Hysteresis voltage (ISO/DIS 17987

Param 65)

V_HYS= (V_BUSrec- V_BUSdom) See Figure

8-4 and Figure 8-3

V_HYS= V_IH- V_ILSee Figure 8-4 and

Figure 8-3

Hysteresis voltage (SAE J2602)

0.07

0.4

V_{SERIAL_DIODE}Serial diode LIN termination pullup path

0.7

I_{SERIAL_DIODE}= 10 μA

Pullup resistor to V_SUP(ISO/DIS 17987

Param 26)

R_PU

Normal and Standby modes

Sleep mode, V_SUP= 27 V, LIN = GND

kΩ

µA

I_RSLEEP

Pullup current source to V_SUP

–20

–2

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MAX UNIT

7.6 Electrical Characteristics (continued)

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

C_LINPIN

Capacitance of the LIN pin

V_SUP= 14 V

(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩand 899 pF/20 kΩ

(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ωand 899 pF/900 Ω

(3) ISO 17987 bus load conditions (C_LINBUS, R_LINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.

(4) RXD uses open drain output structure therefore V_OLlevel is based upon microcontroller supply voltage V_CC

(5) I_{leak gnd}= (V_BAT- V_LIN)/R_Load

(6) Values are for each V_SUPpin

7.7 Duty Cycle Characteristics

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TH_REC(MAX)= 0.744 x V_SUPTH_DOM(MAX)

= 0.581 x V_SUP, V_SUP= 7 V to 18 V, t_BIT

= 50 µs (20 kbps), D1 = t_{BUS_rec(min)}/(2 x

t_BIT) (See Figure 8-10, Figure 8-11)

Duty Cycle 1 (ISO/DIS 17987 Param

27)⁽³⁾

D1_12V

0.396

TH_REC(MAX)= 0.625 x V_SUP, TH_DOM(MAX)

= 0.581 x V_SUP, V_SUP= 4 V to 7 V, t_BIT

50 µs (20 kbps), D1 = t_{BUS_rec(min)}/(2 x

t_BIT) (See Figure 8-10, Figure 8-11)

D1_12V

Duty Cycle 1 ^{(3) (4)}

0.396

TH_REC(MAX)= 0.744 x V_SUP

TH_DOM(MAX)= 0.581 x V_SUP

Duty Cycle 1 ^{(1) (2) (4)}

V_SUP= 7 V to 18 V, t_BIT= 52 μs

D1 = t_{BUS_rec(min)}/(2 x t_BIT) (See Figure

8-10, Figure 8-11)

TH_REC(MIN)= 0.422 x V_SUP, TH_DOM(MIN)

= 0.284 x V_SUP, V_SUP= 7 V to 18 V, t_BIT

= 50 µs (20 kbps), D2 = t_{BUS_rec(MAX)}/(2

x t_BIT) (See Figure 8-10, Figure 8-11)

Duty Cycle 2 (ISO/DIS 17987 Param

28) ⁽³⁾

D2_12V

0.581

TH_REC(MIN)= 0.546 x V_SUP, TH_DOM(MIN)

= 0.4 x V_SUP, V_SUP= 4 V to 7 V, t_BIT

D2_12V

Duty Cycle 2 ^{(3) (4)}

50 µs (20 kbps), D2 = t_{BUS_rec(MAX)}/(2 x

t_BIT) (See Figure 8-10, Figure 8-11)

TH_REC(MIN)= 0.422 x V_SUP

TH_DOM(MIN)= 0.284 x V_SUP

Duty Cycle 2 ^{(1) (2) (4)}

0.581

V_SUP= 7 V to 18 V, t_BIT= 52 μs

D2 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure

8-10, Figure 8-11)

TH_REC(MAX)= 0.778 x V_SUP, TH_DOM(MAX)

= 0.616 x V_SUP, V_SUP= 7 V to 18 V, t_BIT

= 96 µs (10.4 kbps), D3 = t_{BUS_rec(min)}/(2

x t_BIT) (See Figure 8-10, Figure 8-11)

Duty Cycle 3 (ISO/DIS 17987 Param

29) ⁽³⁾

D3_12V

0.417

TH_REC(MAX)= 0.645 x V_SUP, TH_DOM(MAX)

= 0.616 x V_SUP, V_SUP= 4 V to 7 V, t_BIT

D3_12V

Duty Cycle 3 ^{(3) (4)}

96 µs (10.4 kbps), D3 = t_{BUS_rec(min)}/(2 x

t_BIT) (See Figure 8-10, Figure 8-11)

TH_REC(MAX)= 0.778 x V_SUP

TH_DOM(MAX)= 0.616 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 96 μs

D3 = t_{BUS_rec(min)}/(2 x t_BIT) (See Figure

8-10, Figure 8-11)

Duty Cycle 3 ^{(1) (2) (4)}

0.417

TH_REC(MIN)= 0.389 x V_SUP, TH_DOM(MIN)

= 0.251 x V_SUP, V_SUP= 7 V to 18 V, t_BIT

= 96 µs (10.4 kbps), D4 =

t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 8-10,

Figure 8-11)

Duty Cycle 4 (ISO/DIS 17987 Param

30) ⁽³⁾

D4_12V

0.59

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7.7 Duty Cycle Characteristics (continued)

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

TH_REC(MIN)= 0.422 x V_SUP, TH_DOM(MIN)

= 0.284 x V_SUP, V_SUP= 4 V to 7 V, t_BIT

96 µs (10.4 kbps), D4 = t_{BUS_rec(MAX)}/(2

x t_BIT) (See Figure 8-10, Figure 8-11)

D4_12V

Duty Cycle 4 ^{(3) (4)}

0.59

TH_REC(MIN)= 0.389 x V_SUP

TH_DOM(MIN)= 0.251 x V_SUP

V_SUP= 7 V to 18 V, t_BIT= 96 μs

D4 = t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure

8-10, Figure 8-11)

Duty Cycle 4 ^{(1) (2) (4)}

0.59

TH_REC(MAX)= 0.710 x V_SUP, TH_DOM(MAX)

= 0.544 x V_SUP, V_SUP= 15 V to 36 V,

t_BIT= 50 µs (20 kbps), D1 =

t_{BUS_rec(min)}/(2 x t_BIT) (See Figure 8-10,

Figure 8-11)

Duty Cycle 1 (ISO/DIS 17987 Param

72)

D1_24V

0.33

TH_REC(MIN)= 0.446 x V_SUP, TH_DOM(MIN)

= 0.302 x V_SUP, V_SUP= 15.6 V to 36 V,

t_BIT= 50 µs (20 kbps), D2 =

t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 8-10,

Figure 8-11)

Duty Cycle 2 (ISO/DIS 17987 Param

73)

D2_24V

D3_24V

D4_24V

0.642

TH_REC(MAX)= 0.744 x V_SUP, TH_DOM(MAX)

= 0.581 x V_SUP, V_SUP= 7 V to 36 V, t_BIT

= 96 µs (10.4 kbps), D3 = t_{BUS_rec(min)}/(2

x t_BIT) (See Figure 8-10, Figure 8-11)

Duty Cycle 3 (ISO/DIS 17987 Param

74)

0.386

TH_REC(MIN)= 0.422 x V_SUP, TH_DOM(MIN)

= 0.284 x V_SUP, V_SUP= 7.6 V to 36 V,

t_BIT= 96 µs (10.4 kbps), D4 =

t_{BUS_rec(MAX)}/(2 x t_BIT) (See Figure 8-10,

Figure 8-11)

Duty Cycle 4 (ISO/DIS 17987 Param

75) ⁽⁴⁾

0.591

TH_REC(MAX)= 0.665 x V_SUP

TH_DOM(MAX)= 0.499 x V_SUP

V_SUP= 5.5 V to 7 V, t_BIT= 52 μs

D1_LB

D2_LB

D3_LB

D4_LB

Duty cycle 1 at low battery ^{(1) (2) (4)}

Duty cycle 2 at low battery^{(1) (2) (4)}

Duty cycle 3 at low battery ^{(1) (2) (4)}

Duty cycle 4 at low battery ^{(1) (2) (4)}

0.396

TH_REC(MAX)= 0.496 x V_SUP

TH_DOM(MAX)= 0.361 x V_SUP

V_SUP= 6.1 V to 7 V, t_BIT= 52 μs

0.581

TH_REC(MAX)= 0.665 x V_SUP

TH_DOM(MAX)= 0.499 x V_SUP

V_SUP= 5.5 V to 7 V, t_BIT= 96 μs

TH_REC(MAX)= 0.496 x V_SUP

TH_DOM(MAX)= 0.361 x V_SUP

V_SUP= 6.1 V to 7 V, t_BIT= 96 μs

TH_REC(MAX)= 0.744 x V_SUP

Transmitter propagation delay timings

for the duty cycle ^{(1) (2) (4)}

Recessive to dominant

TH_DOM(MAX)= 0.581 x V_SUP

7 V ≤V_SUP≤18 V, t_BIT= 52 μs

t_{REC(MAX)_D1}- t_{DOM(MIN)_D1}

Tr-d max

Td-r max

Tr-d max

Td-r max

10.8

8.4

µs

TH_REC(MAX)= 0.422 x V_SUP

Transmitter propagation delay timings

for the duty cycle ^{(1) (2) (4)}

Dominant to recessive

TH_DOM(MAX)= 0.284 x V_SUP

7 V ≤V_SUP≤18 V, t_BIT= 52 μs

t_{DOM(MAX)_D2}- t_{REC(MIN)_D2}

TH_REC(MAX)= 0.778 x V_SUP

TH_DOM(MAX)= 0.616 x V_SUP

7 V ≤V_SUP≤18 V, t_BIT= 96 μs

t_{REC(MAX)_D3}- t_{DOM(MIN)_D3}

Transmitter propagation delay timings

for the duty cycle ^{(1) (2) (4)}

Recessive to dominant

15.9

17.28

TH_REC(MIN)= 0.389 x V_SUP

TH_DOM(MIN)= 0.251 x V_SUP

7 V ≤V_SUP≤18 V, t_BIT= 96 μs

t_{DOM(MAX)_D4}- t_{REC(MIN)_D4}

Transmitter propagation delay timings

for the duty cycle ^{(1) (2) (4)}

Dominant to recessive

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MAX UNIT

7.7 Duty Cycle Characteristics (continued)

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

TH_REC(MAX)= 0.665 x V_SUP

Low battery transmitter propagation

Tr-d max_low delay timings for the duty cycle ^{(1) (2) (4)}

Recessive to dominant

TH_DOM(MAX)= 0.499 x V_SUP

5.5 V ≤V_SUP≤7 V, t_BIT= 52 μs

t_{REC(MAX)_low}- t_{DOM(MIN)_low}

10.8

8.4

µs

TH_REC(MAX)= 0.496 x V_SUP

TH_DOM(MAX)= 0.361 x V_SUP

6.1 V ≤V_SUP≤7 V, t_BIT= 52 μs

t_{DOM(MAX)_low}- t_{REC(MIN)_low}

Low battery transmitter propagation

Td-r max_low delay timings for the duty cycle ^{(1) (2) (4)}

Dominant to recessive

(1) SAE 2602 commander node load conditions: 5.5 nF/4 kΩand 899 pF/20 kΩ

(2) SAE 2602 responder node load conditions: 5.5 nF/875 Ωand 899 pF/900 Ω

(3) ISO 17987 bus load conditions (C_LINBUS, R_LINBUS) include 1 nF/1 kΩ; 6.8 nF/660 Ω; 10 nF/500 Ω.

(4) Specified by design

7.8 Switching Characteristics

parameters valid across -40℃≤T_A≤125℃(unless otherwise noted)

SYMBOL

DESCRIPTION

TEST CONDITIONS

MIN

NOM

MAX UNIT

Receiver rising propagation delay time

(ISO/DIS 17987 Param 31)

t_{rx_pdr}

µs

R_RXD= 2.4 kΩ, C_RXD= 20 pF;

(See Figure 8-12 and Figure 8-13 )

Receiver falling propagation delay time

(ISO/DIS 17987 Param 31)

t_{rx_pdf}

Rising edge with respect to falling edge,

Symmetry of receiver propagation delay (trx_sym = trx_pdf –trx_pdr), R_RXD

t_{rs_sym}

µs

–2

time

2.4 kΩ_,C_RXD= 20 pF; (See Figure

8-12 and Figure 8-13 )

LIN wake-up time (Minimum dominant

time on LIN bus for wake-up)

t_LINBUS

100

150

See Figure 8-16, 图9-2, and 图9-3

See 图9-3

Time to clear false wake-up prevention

logic if LIN bus had a bus stuck

dominant fault (recessive time on LIN

bus to clear bus stuck dominant fault)

t_CLEAR

µs

t_DST

Dominant state time out

Time to change from standby mode to

normal mode or normal mode to sleep

mode through EN pin; See Figure 8-14

and 图9-4

t_{MODE_CHANGE}Mode change delay time

Time for normal mode to initialize and

data on RXD pin to be valid; See Figure

8-14

t_NOMINT

Normal mode initialization time

Power up time

µs

Upon power up time it takes for valid

data on RXD

t_PWR

1.5

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8 Parameter Measurement Information

1,4,7,10

NC 13,18,23,24

16,21

RXD1/2/3/4

Power Supply

Resolution: 10mV/ 1mA

Accuracy: 0.2%

5 V

V_SUP1/2

V_PS

EN1/2/3/4

2,5,8,11

3,6,9,12

15,17,20,22

LIN1/2/3/4

Pulse Generator

t_R/t_F^:Square Wave: < 20 ns

t_R/t_F^:Triangle Wave: < 40ns

Frequency: 20 ppm

TXD1/2/3/4

14,19

GND1/2

Jitter: < 25 ns

Measurement Tools

O-scope:

DMM

图8-1. Test System: Operating Voltage Range with RX and TX Access

Delta t = + 5 µs (t_BIT= 50 µs)

Trigger Point

2 x t_BIT= 100 µs (20 kBaud)

图8-2. RX Response: Operating Voltage Range

Period T = 1/f

Amplitude

(signal range)

LIN Bus Input

Frequency: f = 20 Hz

Symmetry: 50%

图8-3. LIN Bus Input Signal

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1,4,7,10

RXD1/2/3/4

EN1/2/3/4

13,18,23,24

16,21

5 V

Power Supply

Resolution: 10mV/ 1mA

Accuracy: 0.2%

V_SUP1/2

V_PS

2,5,8,11

3,6,9,12

15,17,20,22

14,19

LIN1/2/3/4

GND1/2

Pulse Generator

t_R/t_F^:Square Wave: < 20 ns

t_R/t_F^:Triangle Wave: < 40ns

Frequency: 20 ppm

TXD1/2/3/4

Jitter: < 25 ns

Measurement Tools

O-scope:

DMM

图8-4. LIN Receiver Test with RX Access

13,18,23,24

1,4,7,10

RXD1/2/3/4

5 V

Power Supply 1

Resolution: 10mV/ 1mA

Accuracy: 0.2%

16,21

V_SUP1/2

EN1/2/3/4

V_PS1

2,5,8,11

3,6,9,12

LIN1/2/3/4 15, 17, 20, 22

Power Supply 2

Resolution: 10mV/ 1mA

Accuracy: 0.2%

TXD1/2/3/4

14,19

V_PS2

R_BUS

GND1/2

Measurement Tools

O-scope:

DMM

图8-5. V_{SUP_NON_OP}

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1,4,7,10

NC 13,18,23,24

16,21

RXD1/2/3/4

EN1/2/3/4

Power Supply

Resolution: 10 mV / 1mA

V_SUP1/2

Accuracy: 0.2%

V_PS

2,5, 8,11

3,6,9,12

R_MEAS= 499

15,17,20,22

14,19

LIN1/2/3/4

GND1/2

TXD1/2/3/4

Measurement Tools

O-scope:

DMM

图8-6. Test Circuit for I_{BUS_PAS_dom}; TXD = Recessive State V_BUS= 0 V

1,4,7,10

NC 13,18,23,24

RXD1/2/3/4

EN1/2/3/4

Power Supply

Resolution: 10 mV / 1mA

Accuracy: 0.2%

V_PS1

16,21

V_SUP1/2

2,5, 8,11

3,6,9,12

Power Supply 2

Resolution: 10mV/ 1mA

Accuracy: 0.2%

1 k

15,17,20,22

14,19

LIN1/2/3/4

GND1/2

V_PS2

TXD1/2/3/4

V_PS22 V/s ramp

[8 V à 36 V]

V Drop across resistor

< 20 mV

Measurement Tools

O-scope:

DMM

图8-7. Test Circuit for I_{BUS_PAS_rec}

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1,4,7,10

NC 13,18,23,24

16,21

RXD1/2/3/4

EN1/2/3/4

Power Supply

Resolution: 10 mV / 1mA

Accuracy: 0.2%

V_PS1

V_SUP1/2

2,5, 8,11

3,6,9,12

Power Supply 2

Resolution: 10mV/ 1mA

Accuracy: 0.2%

15,17,20,22

14,19

1 kΩ

LIN1/2/3/4

GND1/2

V_PS2

TXD1/2/3/4

V_PS22 V/s ramp

[0 V → 36 V]

V Drop across resistor

< 1V

Measurement Tools

O-scope: DMM

图8-8. Test Circuit for I_{BUS_NO_GND}Loss of GND

1,4,7,10

NC 13,18,23,24

RXD1/2/3/4

EN1/2/3/4

16,21

V_SUP1/2

2,5, 8,11

3,6,9,12

Power Supply 2

Resolution: 10mV/ 1mA

Accuracy: 0.2%

V_PS

15,17,20,22

14,19

10 k

LIN1/2/3/4

GND1/2

TXD1/2/3/4

V_PS22 V/s ramp

[0 V → 36 V]

V Drop across resistor

< 1V

Measurement Tools

O-scope: DMM

图8-9. Test Circuit for I_{BUS_NO_BAT}Loss of Battery

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1,4,7,10

NC 13,18,23,24

16,21

RXD1/2/3/4

EN1/2/3/4

Power Supply

Resolution: 10 mV / 1mA

Accuracy: 0.2%

V_PS1

V_SUP1/2

2,5, 8,11

3,6,9,12

R_MEAS

Power Supply 2

Resolution: 10mV/ 1mA

Accuracy: 0.2%

15,17,20,22

14,19

LIN1/2/3/4

GND1/2

Pulse Generator

t_R/t_F^:Square Wave: < 20 ns

t_R/t_F^:Triangle Wave: < 40ns

Frequency: 20 ppm

V_PS2

TXD1/2/3/4

Jitter: < 25 ns

Measurement Tools

O-scope:

DMM

图8-10. Test Circuit Slope Control and Duty Cycle

T_BIT

D = 50%

TXD (Input)

D1₁₂: 0.744 * V_SUP

D3₁₂: 0.778 * V_SUP

TH_REC(MAX)

TH_DOM(MAX)

TH_REC(MIN)

TH_DOM(MIN)

Thresholds

RX Node 1

D1₁₂: 0.581 * V_SUP

D3₁₂: 0.616 * V_SUP

LIN Bus

Signal

D2₁₂: 0.422 * V_SUP

D4₁₂: 0.389 * V_SUP

V_SUP

Thresholds

RX Node 2

D2₁₂: 0.284 * V_SUP

D4₁₂: 0.251 * V_SUP

t_{BUS_REC(MIN)}

t_{BUS_DOM(MAX)}

RXD: Node 1

D1 (20 kbps)

D3 (10.4 kbps)

t_{BUS_DOM(MIN)}

t_{BUS_REC(MAX)}

RXD: Node 2

D2 (20 kbps)

D4 (10.4 kbps)

图8-11. Definition of Bus Timing Parameters

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V_CC

2.4 k

1,4,7,10

NC 13,18,23,24

16,21

RXD1/2/3/4

EN1/2/3/4

5 V

20 pF

Power Supply

Resolution: 10 mV / 1mA

Accuracy: 0.2%

V_PS

V_SUP1/2

2,5, 8,11

3,6,9,12

15,17,20,22

14,19

Pulse Generator

t_R/t_F^:Square Wave: < 20 ns

t_R/t_F^:Triangle Wave: < 40ns

Frequency: 20 ppm

LIN1/2/3/4

GND1/2

TXD1/2/3/4

Jitter: < 25 ns

Measurement Tools

O-scope: DMM

图8-12. Propagation Delay Test Circuit

D1: 0.744 * V_SUP

D3: 0.778 * V_SUP

TH_REC(MAX)

TH_DOM(MAX)

TH_REC(MIN)

TH_DOM(MIN)

Thresholds

RX Node 1

D1: 0.581 * V_SUP

D3: 0.616 * V_SUP

LIN Bus

Signal

D2: 0.422 * V_SUP

D4: 0.389 * V_SUP

V_SUP

Thresholds

RX Node 2

D2: 0.284 * V_SUP

D4: 0.251 * V_SUP

RXD: Node 1

D1 (20 kbps)

D3 (10.4 kbps)

t_{rx_pdr(1)}

t_{rx_pdf(1)}

RXD: Node 2

D2 (20 kbps)

D4 (10.4 kbps)

t_{rx_pdr(2)}

t_{rx_pdf(2)}

图8-13. Propagation Delay

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Wake Event

t_{MODE_CHANGE}

t_NOMINT

t_{MODE_CHANGE}

Transition

Sleep

Standby

Transition

Normal

MODE

Indeterminate

Ignore

Mirrors

Bus

Wake Request

RXD = Low

RXD

Floating

Indeterminate Ignore

Mirrors Bus

图8-14. Mode Transitions

图8-15. Wake-Up Through EN

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0.6 x

V_SUP

0.6 x

V_SUP

LINx

0.4 x V_SUP

V_SUP

0.4 x

V_SUP

t < t_LINBUS

t_LINBUS

TXDx

Weak Internal Pulldown

ENx

Floating

Sleep

RXDx

MODE

Standby

Normal

图8-16. Wake-Up Through LIN

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9 Detailed Description

9.1 Overview

The TLIN2024A-Q1 device is a Quad Local Interconnect Network (LIN) physical layer transceiver, compliant to

LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A and ISO/DIS 17987–4 standards, with integrated wake-up and protection

features. The device has two separate dual LIN transceiver blocks. V_SUP1/2provides power to the separate dual

transceiver blocks. The LIN bus is a single wire bidirectional bus typically used for low speed in-vehicle networks

using data rates up to 20 kbps. The device's LIN receivers work up to 100 kbps supporting in-line programming.

The LIN protocol output data stream on the TXD in converted by the device into LIN bus signal using a current-

limited wave shaping driver as outlined by the LIN physical layer specification. The receiver converts the data

stream to logic level signals that are sent to the microprocessor through the open-drain RXD pin. The LIN bus

has two states: dominant state (voltage near ground) and recessive state (voltage near battery). In the recessive

state, the LIN bus is pulled high by the internal pull-up resistor (45 kΩ) and a series diode. No external pull-up

components are required for responder node applications. Commander node applications require an external

pull-up resistor (1 kΩ) plus a series diode per the LIN specification.

The device is designed to support 12-V and 24-V applications with a wide input voltage operating range and also

supports low-power sleep mode. The device also provides two methods to wake-up: EN pin and from the LIN

bus.

The TLIN2024A-Q1 integrates ESD protection and fault protection which allow for a reduction in the required

external components in the applications. In the event of a ground shift or supply voltage disconnection, the

device prevents back-feed current through LIN to the supply input. The device also includes undervoltage

detection, temperature shutdown protection, and loss-of-ground protection.

V_SUP1and GND1 supplies transceivers 1 and 2 while V_SUP2and GND2 supplies transceiver 3 and 4. The device

is part of the LIN family that includes the TLIN2022A and TLIN2029A LIN transceivers.

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9.2 Functional Block Diagram

V_SUP1

RXD1

V_SUP1/2

Comp

GND1

Filter

Wake Up

State &

EN1

Fault Detection

& Protection

22 LIN1

GND1

21 V_SUP1

18 GND1

DR/

Slope

CTL

Dominant

State

Timeout

TXD1

GND1

RXD2

EN2

20 LIN2

Channel 2 is same as Channel 1

TXD2

V_SUP2

RXD3

V_SUP2/2

Comp

GND2

Filter

Wake Up

State &

EN3

Fault Detection

& Protection

LIN3

GND2

DR/

Slope

CTL

Dominant

State

Timeout

TXD3

16 V_SUP2

GND2

RXD4 10

EN4 11

15 LIN4

Channel 4 is same as Channel 3

TXD4

9.3 Feature Description

9.3.1 LIN (Local Interconnect Network) Bus

These high voltage input/output pins are single wire LIN bus transmitters and receivers. The LIN pins can survive

excessive DC and transient voltages up to 60 V. Reverse currents from the LIN pins to supply (V_SUP1/2) are

minimized with blocking diodes, even in the event of a ground shift or loss of supply (V_SUP1/2).

9.3.1.1 LIN Transmitter Characteristics

The transmitter has thresholds and AC parameters according to the LIN specification. The transmitter is a low

side transistor with and internal current limitation and thermal shutdown. During a thermal shutdown condition,

the transmitter is disabled to protect the device. There is an internal pull-up resistor with a serial diode structure

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to V_SUP1/2, so no external pull-up components are required for the LIN responder node applications. An external

pull-up resistor and series diode to V_SUP1/2must be added when the device is used for a commander node

application.

9.3.1.2 LIN Receiver Characteristics

The receiver characteristic thresholds are proportional with the device supply pin according to the LIN

specification.

The receiver is capable of receiving higher data rates (> 100 kbps) than supported by LIN or SAE J2602

specifications. This allows the TLIN2024A-Q1 to be used for high speed downloads at the end-of-line production

or other applications. The actual data rate achievable depends on system time constants (bus capacitance and

pull-up resistance) and driver characteristics used in the system.

9.3.1.2.1 Termination

There is an internal pull-up resistor with a serial diode structure to V_SUP1/2, so no external pull-up components

are required for the LIN responder node applications. An external pull-up resistor (1 kΩ) and a series diode to

V_SUP1/2must be added when the device is used for commander node applications as per the LIN specification.

图9-1 shows a commander node configuration and how the voltage levels are defined

Voltage drop across the

Simplified Transceiver

V_{LIN_Bus}

diodes in the pullup path

RXD

V_SUP1/2

V_SUP

V_SUP/2

V_Battery

V_SUP

V_{LIN_Recessive}

Receiver

Filter

1 k

45 k

LIN 1/2/3/4

GND1/2

LIN

Bus

TXD

350 k

Transmitter

with slope control

V_{LIN_Dominant}

图9-1. Commander Node Configuration with Voltage Levels

9.3.2 TXD (Transmit Input and Output)

TXD is the interface to the processor's LIN protocol controller or SCI/UART that is used to control the state of the

LIN output. When TXD is low the LIN output is dominant (near ground). When TXD is high the LIN output is

recessive (near V_Battery). See 图 9-1. The TXD input structure is compatible with microprocessors with 3.3 V and

5 V I/O. TXD has an internal pull-down resistor. The LIN bus is protected from being stuck dominant through a

system failure driving TXD low through the dominant state timeout timer.

9.3.3 RXD (Receive Output)

RXD is the interface to the processor's LIN protocol controller or SCI/UART, which reports the state of the LIN

bus voltage. LIN recessive (near V_Battery) is represented by a high level on the RXD and LIN dominant (near

ground) is represented by a low level on the RXD pin. The RXD output structure is an open-drain output stage.

This allows the device to be used with 3.3 V and 5 V I/O microprocessors. If the microprocessor’s RXD pin

does not have an integrated pull-up, an external pull-up resistor to the microprocessor I/O supply voltage is

required. In standby mode the RXD pin is driven low to indicate a wake-up request from the LIN bus.

9.3.4 V_SUP1/2(Supply Voltage)

V_SUP1/2are the power supply pins. V_SUP1/2is connected to the battery through and external reverse battery

blocking diode (See 图 9-1). If there is a loss of power at the ECU level, the device has extremely low leakage

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from the LIN pin, which does not load the bus down. This is optimal for LIN systems in which some of the nodes

are unpowered (ignition supplied) while the rest of the network remains powered (battery supplied).

9.3.5 GND1/2 (Ground)

GND1 and GND2 are the ground connections for LIN1/2 and LIN3/4 channels respectively. V_SUP1is referred to

GND1 and V_SUP2is referred to GND2. The device can operate with a ground shift as long as the ground shift

does not reduce V_SUP1/2below the minimum operating voltage. If there is a loss of ground at the ECU level, the

device has a low leakage from the LIN pin, which does not load the bus down. This is optimal for LIN systems in

which some of the nodes are unpowered (ignition supplied) while the rest of the network remains powered

(battery supplied).

9.3.6 EN (Enable Input)

EN1, EN2, EN3 and EN4 control the operational modes of the respective LIN channel. When EN1/EN2/EN3/EN4

is high, the LIN1/LIN2/LIN3/LIN4 channel is in normal operating mode allowing a transmission path from TXD to

LIN and from LIN to RXD. When either of the EN pins is low, the respective LIN channel is put into sleep mode

and there is no transmission path available. The device can enter normal mode only after wake-up. EN has an

internal pull-down resistor to ensure the device remains in low power mode even if EN floats.

9.3.7 Protection Features

The TLIN2024A-Q1 has several protection features.

9.3.8 TXD Dominant Time Out (DTO)

During normal mode, if TXD is inadvertently driven permanently low by a hardware or software application

failure, the LIN bus is protected by the dominant state timeout timer. This timer is triggered by a falling edge on

the TXD pin. If the low signal remains on TXD for longer than t_DST, the transmitter is disabled, thus allowing the

LIN bus to return to recessive state and communication to resume on the bus. The protection is cleared and the

t_DSTtimer is reset by a rising edge on TXD. The TXD pin has an internal pull-down to ensure the device fails to a

known state if TXD is disconnected. During this fault, the transceiver remains in normal mode (assuming no

change of state request on EN), the transmitter is disabled, the RXD pin reflects the LIN bus and the LIN bus

pull-up termination remains on.

9.3.9 Bus Stuck Dominant System Fault: False Wake-Up Lockout

The TLIN2024A-Q1 contains logic to detect bus stuck dominant system faults and prevents the device from

waking up falsely during the system fault. Upon entering sleep mode, the device detects the state of the LIN bus.

If the bus is dominant, the wake-up logic is locked out until a valid recessive on the bus “clears”the bus stuck

dominant, preventing excessive current use. 图9-2 and 图9-3 show the behavior of this protection.

RXDx

ENx

LINxBus

t_LINBUS

< t_LINBUS

图9-2. No Bus Fault: Entering Sleep Mode with Bus Recessive Condition and Wake-up

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RXDx

ENx

t_LINBUS

LINxBus

t_CLEAR

< t_CLEAR

图9-3. Bus Fault: Entering Sleep Mode with Bus Stuck Dominant Fault, Clearing, and Wake-up

9.3.10 Thermal Shutdown

The LIN transmitter is protected by limiting the current; however if the junction temperature of the device

exceeds the thermal shutdown threshold, the device puts the LIN transmitter into the recessive state. Once the

over temperature fault condition has been removed and the junction temperature has cooled beyond the

hysteresis temperature, the transmitter is re-enabled, assuming the device remains in the normal operation

mode. During this fault, the transceiver remains in normal mode (assuming no change of state request on EN),

the transmitter is in recessive state, the RXD pin reflects the LIN bus and LIN bus pull-up termination remains

on.

9.3.11 Under Voltage on V_SUP

The TLIN2024A-Q1 contains a power on reset circuit to avoid false bus messages during under voltage

conditions when V_SUP1/2is less than UV_SUP1/2

9.3.12 Unpowered Device and LIN Bus

In automotive applications some LIN nodes in a system can be unpowered (ignition supplied) while others in the

network remains powered by the battery. The TLIN2024A-Q1 has a low unpowered leakage current from the bus

so an unpowered node does not affect the network or load it down.

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9.4 Device Functional Modes

The TLIN2024A-Q1 has three functional modes of operation, normal, sleep, and standby. The next sections

describe these modes as well as how the device moves between the different modes. 图 9-4 graphically shows

the relationship while 表9-1 shows the state of pins.

表9-1. Operating Modes

LIN BUS

TERMINATION

MODE

ENx

RXDx

TRANSMITTER

COMMENT

Weak Current Pull-

Sleep

Low

Floating

Off

Wake-up event detected, waiting on

MCU to set EN

Standby

Normal

Low

Off

45 kΩ (typical)

High

LINx Bus Data

LINx transmission up to 20 kbps

Unpowered System

V_SUP< UV_SUP

V_SUP> UV_SUP

EN = LOW

V_SUP> UV_SUP

EN = High

V_SUP< UV_SUP

Standby Mode

Driver: Off

RXD: Low

LIN termination: 45 kΩ

V_SUP< UV_SUP

EN = High

Normal Mode

LIN bus wake-up

Sleep Mode

Driver: On

RXD: LIN Bus Data

LIN termination: 45 kΩ

Driver: Off

RXD: Floating

LIN termination: Weak pull-up

EN = Low

EN = High

图9-4. Operating State Diagram

9.4.1 Normal Mode

The EN pin controls the mode of the channel. If the EN1/EN2/EN3/EN4 pin is high at power up, the channel

powers up in normal mode. In normal operational mode, the receiver and transmitter are active and the LIN

transmission up to the LIN specified maximum of 20 kbps is supported. The receiver detects the data stream on

the LIN bus and outputs it on RXD for the LIN controller. A recessive signal on the LIN bus is a digital high and a

dominant signal on the LIN bus is a digital low. The driver transmits input data from TXD to the LIN bus. Normal

mode is entered as EN transitions high while the LIN channel is in sleep or standby mode for > t_{MODE_CHANGE}

plus t_NOMINT

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9.4.2 Sleep Mode

Sleep Mode is the power saving mode for the TLIN2024A-Q1. Even with extremely low current consumption in

this mode, the LIN channel can still wake-up from LIN bus through a wake-up signal or if EN is set high for >

t_{MODE_CHANGE}. The LIN bus is filtered to prevent false wake-up events. The wake-up events must be active for

the respective time periods (t_LINBUS).

The sleep mode is entered by setting EN low for longer than t_{MODE_CHANGE}

While the device is in sleep mode, the following conditions exist.

• The LIN bus driver is disabled and the internal LIN bus termination is switched off (to minimize power loss if

LIN is short circuited to ground). However, the weak current pull-up is active to prevent false wake-up events

in case an external connection to the LIN bus is lost.

• The normal receiver is disabled.

• EN input and LIN wake-up receiver are active.

9.4.3 Standby Mode

If the device powers up with any of the ENx pins held low, the corresponding LINx channel is in standby mode.

Standby mode is also entered whenever a wake-up event occurs through the LIN bus while the device is in

sleep mode. The LIN bus responder termination circuit is turned on when standby mode is entered. Standby

mode is signaled through a low level on RXD. See Standby Mode Application Note for more application

information.

When EN is set high for longer than t_{MODE_CHANGE}while the device is in standby mode the device returns to

normal mode and the normal transmission paths from TXD to LIN bus and LIN bus to RXD are enabled.

9.4.4 Wake-Up Events

There are two ways to wake-up from sleep mode:

• Remote wake-up initiated by the falling edge of a recessive (high) to dominant (low) state transition on LIN

bus where the dominant state is be held for t_LINBUSfilter time. After this t_LINBUSfilter time has been met and a

rising edge on the LIN bus going from dominant state to recessive state initiates a remote wake-up event,

eliminating false wake-ups from disturbances on the LIN bus or if the bus is shorted to ground.

• Local wake-up through EN being set high for longer than t_{MODE_CHANGE}

9.4.4.1 Wake-Up Request (RXD)

When the TLIN2024A-Q1 encounters a wake-up event from the LIN bus, RXD goes low and the channel

transitions to standby mode until EN is reasserted high and the channel enters normal mode. Once the channel

enters normal mode the RXD pin releases the wake-up request signal and the RXD pin then reflects the receiver

output from the LIN bus.

9.4.4.2 Mode Transitions

When the TLIN2024A-Q1 is transitioning between modes the device needs the time, t_{MODE_CHANGE}, to allow the

change to fully propagate from the EN pin through the device into the new state. When transitioning from sleep

or standby mode to normal mode the transition time is the sum of t_{MODE_CHANGE}and t_NOMINT

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10 Application and Implementation Disclaimer

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

The TLIN2024A-Q1 can be used as both a responder device and a commander device in a LIN network. The

device comes with the ability to support both remote wake-up request and local wake-up request.

10.2 Typical Application

The device comes with an integrated 45 kΩ pull-up resistor and series diode for responder node applications.

For commander node applications, an external 1 kΩ pull-up resistor with series blocking diode can be used.

Typical LIN Bus shows the device being used in both commander and responder applications.

V_SUP

24 V - V_BAT

VREG

V_SUP

Commander

Node

V_DD

Pullup

V_SUP2

V_SUP1

EN1

EN2

16 21

V_DD

I/O

1 k

LIN1

MCU

V_DDI/O

MCU w/o

pullup⁽²⁾

220 pF

LIN2

RXD1

TXD1

V_DDI/O

MCU w/o

pullup⁽²⁾

220 pF

RXD2

TXD2

LIN Controller

V_DDI/O

TLIN2024A

SCI/UART⁽¹⁾

MCU w/o

pullup⁽²⁾

LIN3

RXD3

TXD3

220 pF

V_DDI/O

MCU w/o

pullup⁽²⁾

LIN4

RXD4

TXD4

220 pF

EN3

EN4

I/O

GND

(1) If RXD on MCU, or LIN transceiver, has an internal pull-up, then an external pull-up resistor is not required.

(2) If RXD on MCU, or LIN transceiver, does not have an internal pull-up, then an external pull-up resistor is required.

(3) Commander node applications require an external 1 k pull-up resistor and serial diode.

(4) Decoupling capacitor values are system dependent but usually have 100 nF, 1 μF and ≥10 μF

图10-1. Typical LIN Bus

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10.2.1 Design Requirements

The RXD output structure is an open-drain output stage. This allows the TLIN2024A-Q1 to be used with 3.3 V

and 5 V I/O microprocessors. If the RXD pin of the microprocessor does not have an integrated pull-up, an

external pull-up resistor to the microprocessor I/O supply voltage is required.

The V_SUP1/2pins of the device should be decoupled with a 100 nF capacitor as close to the supply pin on the

device as possible. The system should include additional decoupling on the V_SUPline as needed per the

application requirements.

10.2.1.1 Detailed Design Procedures

10.2.1.2 Normal Mode Application Note

When using the TLIN2024A-Q1 in systems which are monitoring the RXD pin for a wake-up request, special

care should be taken during the mode transitions. The output of the RXD pin is indeterminate for the transition

period between states as the receivers are switched. The application software should not look for an edge on the

RXD pin indicating a wake-up request until t_{MODE_CHANGE}when going from sleep or standby to normal mode.

This is shown in Mode Transitions

10.2.1.3 Standby Mode Application Note

If the TLIN2024A-Q1 detects an under voltage on V_SUP1/2, the RXD pin transitions low and would signal to the

software that the device is in standby mode and should be returned to sleep mode for the lowest power state.

10.2.1.4 TXD Dominant State Timeout Application Note

The maximum dominant TXD time allowed by the TXD dominant state time out limits the minimum possible data

rate of the device. The LIN protocol has different constraints for commander and responder applications thus

there are different maximum consecutive dominant bits for each application case and thus different minimum

data rates.

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10.2.2 Application Curves

图 10-2 and 图 10-3 show the propagation delay from the TXD pin to the LIN pin for both dominant to recessive

and recessive to dominant edges. Waveforms are for 1 channel of the device configured in commander mode

with external pull-up resistor (1 kΩ) and 680 pF bus capacitance.

图10-2. Dominant to Recessive Propagation

图10-3. Recessive to Dominant Propagation

10.3 Power Supply Recommendations

The TLIN2024A-Q1 was designed to operate directly off a car battery, or any other DC supply ranging from 4 V

to 48 V. A 100 nF decoupling capacitor should be placed as close to the V_SUP1/2pin of the device as possible. It

is good practice for some applications with noisier supplies to include 1 µF and 10 µF decoupling capacitor.

10.4 Layout

In order for the PCB design to be successful, start with the design of the protection and filtering circuitry.

Because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high

frequency layout techniques must be applied during PCB design. Placement at the connector also prevents

these noisy events from propagating further into the PCB and system.

10.4.1 Layout Guidelines

• Pins 1, 4, 7 and 10 (RXD1/2/3/4): The pins are open drain outputs and require an external pull-up resistor in

the range of 1 kΩ and 10 kΩ to function properly. If the microprocessor paired with the transceiver does not

have an integrated pull-up, an external resistor should be placed between RXD and the regulated voltage

supply for the microprocessor.

• Pins 2, 5, 8 and 11 (EN1/2/3/4): EN is an input pin that is used to place the device in a low power sleep

mode. If this feature is not used the pin should be pulled high to the regulated voltage supply of the

microprocessor through a series resistor, values between 1 kΩ and 10 kΩ. Additionally, a series resistor may

be placed on the pinto limit current on the digital lines in the case of an over voltage fault.

• Pin 13, 18, 23 and 24 (NC): Not Connected

• Pins 3, 6, 9 and 12 (TXD1/2/3/4): The TXD pins are the transmitter input signals to the device from the

microprocessor. A series resistor can be placed to limit the input current to the device in the case of an

overvoltage on this pin. A capacitor to ground can be placed close to the input pin of the device to filter noise.

• Pin 14, 19 (GND2/1): This is the ground connection for the device. This pin should be tied to the ground

plane through a short trace with the use of two vias to limit total return inductance.

• Pins 22, 20, 17 and 15 (LIN1/2/3/4): This pin connects to the LIN bus. For responder node applications a

220 pF capacitor to ground is implemented. For commander node applications and additional series resistor

and blocking diode should be placed between the LIN pin and the V_SUP1/2pin.

• Pin 21, 160 (V_SUP1/2): This is the supply pin for the device. A 100 nF decoupling capacitor should be placed

as close to the device as possible.

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备注

All ground and power connections should be made as short as possible and use at least two vias to

minimize the total loop inductance.

10.4.2 Layout Example

V_DD

RXD1

V_SUP1

Onlyneededfor

theCommander

node

V_DD

EN1

GND

TXD1

V_DD

TXD1

LIN1

LIN2

V_SUP1

RXD2

V_SUP1

RXD2

GND

Onlyneededfor

theCommander

node

V_DD

EN2

LIN2

EN2

GND

TXD2

V_SUP2

GND1

TXD2

GND

Onlyneededfor

theCommander

node

Thermal Pad

RXD3

GND

V_DD

R11

R10

EN3

LIN3

LIN4

EN3

V_SUP2

GND

TXD3

V_SUP2

TXD3

R12

GND

Onlyneededfor

theCommander

node

RXD4

LIN4

RXD4

V_DD

R15

R14

EN4

GND2

EN4

GND

TXD4

R16

图10-4. Layout Example

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11 Device and Documentation Support

11.1 Documentation Support

This device will conform to the following LIN standards. The core of what is needed is covered within this system

spec, however reference should be made to these standards and any discrepancies pointed out and discussed.

This document should provide all the basics of what is needed.

11.1.1 Related Documentation

For related documentation see the following:

LIN Standards:

• ISO/DIS 17987-1: Road vehicles -- Local Interconnect Network (LIN) -- Part 1: General information and use

case definition

• ISO/DIS 17987-4: Road vehicles -- Local Interconnect Network (LIN) -- Part 4: Electrical Physical Layer (EPL)

specification 12V/24V

• SAE J2602-1: LIN Network for Vehicle Applications

EMC requirements:

• SAE J2962-1

• ISO 10605: Road vehicles - Test methods for electrical disturbances from electrostatic discharge

• ISO 11452-4:2011: Road vehicles - Component test methods for electrical disturbances from narrowband

radiated electromagnetic energy - Part 4: Harness excitation methods

• ISO 7637-1:2015: Road vehicles - Electrical disturbances from conduction and coupling - Part 1: Definitions

and general considerations

• ISO 7637-3: Road vehicles - Electrical disturbances from conduction and coupling - Part 3: Electrical

transient transmission by capacitive and inductive coupling via lines other than supply lines

• IEC 62132-4:2006: Integrated circuits - Measurement of electromagnetic immunity 150 kHz to 1 GHz - Part 4:

Direct RF power injection method

• IEC 6100-4-2

• IEC 61967-4

• CISPR25

Conformance Test requirements:

• ISO/DIS 17987-7: Road vehicles -- Local Interconnect Network (LIN) -- Part 7: Electrical Physical Layer (EPL)

conformance test specification

• SAE J2602-2: LIN Network for Vehicle Applications Conformance Test

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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6-May-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TLIN2024ARGYRQ1

ACTIVE

VQFN

RGY

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

TL2024A

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

GENERIC PACKAGE VIEW

RGY 24

5.5 x 3.5 mm, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4203539-5/J

PACKAGE OUTLINE

VQFN - 1 mm max height

RGY0024E

PLASTIC QUAD FLATPACK-NO LEAD

3.6

3.4

0.1 MIN

PIN 1 INDEX AREA

5.6

5.4

(0.13)

SECTION A-A

TYPICAL

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2.1±0.1

2X 1.5

(0.2) TYP

18X 0.5

(0.16)

SYMM

4.1±0.1

4.5

EXPOSED

THERMAL PAD

0.3

24X

0.2

PIN 1 ID

(OPTIONAL)

SYMM

24X

0.1

C A B

0.05

0.5

0.3

4225182/A 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

VQFN - 1 mm max height

RGY0024E

PLASTIC QUAD FLATPACK-NO LEAD

(3.3)

(2.1)

2X (1.5)

24X (0.6)

24X (0.25)

18X (0.5)

(Ø0.2) VIA

TYP

SYMM

(4.1)

(5.3)

(4.5)

(0.68)

(1.12)

(R0.05) TYP

(0.8)

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4225182/A 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

VQFN - 1 mm max height

RGY0024E

PLASTIC QUAD FLATPACK-NO LEAD

(3.3)

2X (1.5)

24X (0.6)

24X (0.25)

18X (0.5)

METAL

TYP

SYMM

(5.3)

(4.5)

(1.36)

6X (1.16)

(R0.05) TYP

6X (0.94)

(0.57)

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

76% PRINTED COVERAGE BY AREA

SCALE: 15X

4225182/A 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

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