TLV0832CPE4 [TI]
2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8, GREEN, PLASTIC, DIP-8;
| 型号： | TLV0832CPE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP8, GREEN, PLASTIC, DIP-8 光电二极管 转换器 |
| 文件： | 总12页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SLAS148 − SEPTEMBER 1996
D
D
D
D
D
8-Bit Resolution
2.7 V to 3.6 V V
TLV0831 . . . D OR P PACKAGE
(TOP VIEW)
CC
Easy Microprocessor Interface or
Standalone Operation
CS
IN+
V
CC
CLK
DO
1
2
3
4
8
7
6
5
Operates Ratiometrically or With V
Reference
CC
IN−
GND
REF
Single Channel or Multiplexed Twin
Channels With Single-Ended or Differential
Input Options
TLV0832 . . . D OR P PACKAGE
(TOP VIEW)
D
D
D
D
Input Range 0 V to V
With V
Reference
CC
CC
Inputs and Outputs Are Compatible With
TTL and MOS
CS
CH0
CH1
GND
V
/REF
CC
1
2
3
4
8
7
6
5
CLK
DO
DI
Conversion Time of 32 µs at
f
= 250 kHz
(CLK)
Designed to Be Functionally Equivalent to
the National Semiconductor ADC0831 and
ADC0832 at 3 V Supply
D
Total Unadjusted Error . . . 1 LSB
description
These devices are 8-bit successive-approximation analog-to-digital converters. The TLV0831 has single input
channels; the TLV0832 has multiplexed twin input channels. The serial output is configured to interface with
standard shift registers or microprocessors.
The TLV0832 multiplexer is software configured for single-ended or differential inputs. The differential analog
voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the
voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of
resolution.
The operation of the TLV0831 and TLV0832 devices is very similar to the more complex TLV0834 and TLV0838
devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input
signal value, which gives the highest possible conversion resolution. Typically, REF is set equal to V
internally on the TLV0832).
(done
CC
The TLV0831C and TLV0832C are characterized for operation from 0°C to 70°C. The TLV0831I and TLV0832I
are characterized for operation from −40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
0°C to 70°C
TLV0831CD
TLV0831ID
TLV0832CD
TLV0832ID
TLV0831CP
TLV0831IP
TLV0832CP
TLV0832IP
−40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 1996, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SLAS148 − SEPTEMBER 1996
functional block diagram
Start
Flip-Flop
CLK
CS
CLK
Shift Register
ODD/EVEN
DI
(TLV0832
D
S
R
Start
CLK
only)
To Internal
Circuits
CLK
SGL/DIF
S
R
CH0/IN+
CH1/IN−
Analog
MUX
Comparator
Time
Delay
EN
CS
CS
CS
CS
R
CS
EN
R
R
CLK
EN
CLK
SAR
Logic
and
DO
Ladder
and
Decoder
EOC
REF
9-Bit
Shift
Bits 0−7
Bits 0−7
D
(TLV0831
only)
Register
Bit 1
LSB
Latch
MSB
First
First
One
Shot
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SLAS148 − SEPTEMBER 1996
functional description
The TLV0831 and TLV0832 use a sample-data-comparator structure that converts differential analog inputs by
a successive-approximation routine. The input voltage to be converted is applied to an input terminal and is
compared to ground (single ended), or to an adjacent input (differential). The TLV0832 input terminals can be
assigned a positive (+) or negative (−) polarity. The TLV0831 contains only one differential input channel with
fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially,
between IN+ and IN−, to the TLV0831 or can be applied to IN+ with IN− grounded as a single ended input. When
the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the
converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. An interval of one clock period is
automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance
state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares
successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates
whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds,
conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock
periods, the conversion is complete. When CS goes high, all internal registers are cleared. At this time, the
output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low
transition followed by address information.
A TLV0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift
register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the
TLV0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are
shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register,
the input channel is selected and conversion starts. The TLV0832 DI terminal to the multiplexer shift register
is disabled for the duration of the conversion.
The TLV0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The DI and DO
terminals can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SLAS148 − SEPTEMBER 1996
sequence of operation
TLV0831
7
1
2
3
4
5
6
8
9
10
CLK
t
su
t
conv
CS
MSB-First Data
MUX
Settling Time
Hi-Z
Hi-Z
DO
MSB
7
LSB
0
6
5
4
3
2
1
TLV0832
1
2
3
4
5
6
10
11
12
13
14
18
19
20
21
CLK
CS
t
conv
t
su
+Sign Bit
Start
Bit
ODD
SGL
DI
(TLV0832
only)
Don’t Care
DIF EVEN
MUX
MSB-First Data
LSB-First Data
Settling Time
Hi-Z
MSB
7
LSB
0
MSB
7
DO
6
2
1
1
2
6
TLV0832 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
ODD/EVEN
CHANNEL NUMBER
CH0
CH1
SGL/DIF
+
−
+
−
+
L
L
H
H
L
H
L
+
H
H = high level, L = low level,
− or + = terminal polarity for the selected input channel
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SLAS148 − SEPTEMBER 1996
absolute maximum ratings over recommended operating free-air temperature range (unless
†
otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
CC
Input voltage range, V : Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
+ 0.3 V
+ 0.3 V
I
CC
CC
Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA
I
Total input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating free-air temperature range, T : C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: P package . . . . . . . . . . . . . . . . . . . . . 260°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
CC
(see clock operating conditions)
2.7
2
3.3
3.6
High-level input voltage, V
IH
V
Low-level input voltage, V
IL
0.8
250
600
60%
V
V
V
= 2.7 V
= 3.3 V
kHz
kHz
CC
Clock frequency, f
(CLK)
10
40%
220
350
90
CC
Clock duty cycle (see Note 2)
Pulse duration, CS high, t
wH(CS)
Setup time, CS low or TLV0832 data valid before CLK↑, t
ns
ns
ns
su
Hold time, TLV0832 data valid after CLK↑, t
h
C suffix
0
70
85
Operating free-air temperature, T
°C
A
I suffix
−40
NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the
recommended duty-cycle range, the minimum pulse duration (high or low) is 1 µs.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SLAS148 − SEPTEMBER 1996
electrical characteristics over recommended range of operating free-air temperature, V
(CLK)
= 3.3 V,
CC
f
= 250 kHz (unless otherwise noted)
digital section
C SUFFIX
I SUFFIX
†
TEST CONDITIONS
PARAMETER
UNIT
‡
TYP
‡
TYP
MIN
2.8
MAX
MIN
2.4
MAX
V
V
V
V
V
= 3 V,
= 3 V,
= 3 V,
I
I
I
= −360 µA
= −10 µA
= 1.6 mA
CC
CC
CC
OH
OH
OL
V
V
High-level output voltage
V
OH
2.9
2.8
Low-level output voltage
High-level input current
Low-level input current
0.34
1
0.4
1
V
OL
I
I
= 3.6 V
= 0
0.005
0.005
µA
µA
IH
IH
IL
−0.005
−1
−0.005
−1
IL
High-level output
(source) current
I
At V
OH
, DO= 0 V,
T
= 25°C
−6.5
8
−15
−6.5
8
−15
mA
mA
OH
OL
A
I
Low-level output (sink) current At V , DO= 0 V,
OL
T
A
= 25°C
= 25°C
= 25°C
−16
0.01
−0.01
5
−16
0.01
−0.01
5
V
= 3.3 V,
= 0,
T
A
3
3
High-impedance-state output
current (DO)
O
O
I
µA
OZ
V
T
A
−3
−3
C
C
Input capacitance
Output capacitance
pF
pF
i
5
5
o
†
‡
All parameters are measured under open-loop conditions with zero common-mode input voltage.
All typical values are at V = 3.3 V, T = 25°C.
CC
A
analog and converter section
†
‡
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
−0.05
to
V
IC
Common-mode input voltage
See Note 3
V
V
+0.05
CC
On channel
Off channel
On channel
Off channel
V = 3.3 V
1
−1
−1
1
I
V = 0
I
I
Standby input current (see Note 4)
Input resistance to REF
µA
kΩ
I(stdby)
V = 0
I
V = 3.3 V
I
r
1.3
2.4
5.9
i(REF)
†
‡
All parameters are measured under open-loop conditions with zero common-mode input voltage.
All typical values are at V = 3.3 V, T = 25°C.
CC
A
NOTES: 3. When channel IN− is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are two
on-chip diodes that conduct forward current for analog input voltages one diode drop above V . Care must be taken during testing
CC
levels (3 V) because high-level analog input voltage (3.6 V) can, especially at high temperatures, cause the input diode
to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply
at low V
CC
voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 3.3-V input range requires a minimum V
3.25 V for all variations of temperature and load.
of
CC
4. Standby input currents go in or out of the on or off channels when the A/D converter is not performing conversion and the clock is
in a high or low steady-state conditions.
total device
‡
PARAMETER
MIN
TYP
MAX
0.75
2.5
UNIT
TLV0831
TLV0832
0.2
1.5
I
Supply current
mA
CC
‡
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢄ
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SLAS148 − SEPTEMBER 1996
operating characteristics V
otherwise noted)
= V = 3.3 V, f
= 250 kHz, t = t = 20 ns, T = 25°C (unless
CC
ref
(CLK) r f A
†
PARAMETER
Supply-voltage variation error
MIN
TYP
MAX
UNIT
TEST CONDITIONS
V
= 3 V to 3.6 V
= 3.3 V,
1/16
1/4
LSB
CC
V
T
ref
A
Total unadjusted error (see Note 5)
Common-mode error
1
LSB
LSB
= MIN to MAX
Differential mode
1/16
200
1/4
Propagation delay time,
output data after CLK↑
(see Note 6)
MSB-first data
LSB-first data
500
t
pd
C
= 100 pF
ns
ns
L
80
80
200
C
C
= 10 pF,
R = 10 kΩ
125
250
L
L
L
t
t
Output disable time, DO after CS↑
dis
= 100 pF,
R = 2 kΩ
L
Conversion time (multiplexer-addressing
time not included)
clock
periods
8
conv
†
All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response
time. LSB-first data applies only to TLV0832.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢃ
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ꢃ
ꢄꢅ
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SLAS148 − SEPTEMBER 1996
PARAMETER MEASUREMENT INFORMATION
V
CC
CLK
CS
50%
50%
GND
V
CC
t
t
su
su
CLK
DO
50%
V
CC
GND
t
pd
0.4 V
2 V
GND
V
V
OH
t
t
h
h
50%
V
CC
OL
2 V
DI
0.4 V
0.4 V
Figure 2. Data-Output Timing
GND
Figure 1. TLV0832 Data-Input Timing
V
CC
Test
Point
S1
S2
R
L
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
t
t
r
r
V
V
CC
CC
90%
90%
10%
50%
CS
DO
CS
50%
10%
GND
GND
CC
t
t
dis
dis
V
CC
V
S1 closed
S2 open
90%
S1 open
S2 closed
DO
Output
10%
Output
GND
GND
VOLTAGE WAVEFORMS
NOTE A: C includes probe and jig capacitance.
VOLTAGE WAVEFORMS
L
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢄ
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SLAS148 − SEPTEMBER 1996
TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR
vs
LINEARITY ERROR
vs
REFERENCE VOLTAGE
REFERENCE VOLTAGE
16
14
1.5
V
= 3.3 V
= 250 kHz
CC
V
I+
= V = 0 V
I−
f
(CLK)
= 25°C
T
A
1.25
12
1.0
10
8
0.75
6
4
0.5
0.25
2
0
0
0.01
0.1
1.0
10
0
1
2
3
4
V
ref
− Reference Voltage − V
V
ref −
Reference Voltage − V
Figure 4
Figure 5
LINEARITY ERROR
vs
LINEARITY ERROR
vs
FREE-AIR TEMPERATURE
CLOCK FREQUENCY
0.5
0.45
0.4
2.0
1.8
1.6
1.4
1.2
1
V
= 3.3 V
= 3.3 V
ref
V
= 3.3 V
= 250 kHz
ref
V
CC
f
(CLK)
85°C
0.35
0.3
0.8
0.6
0.4
25°C
−40°C
0.2
0
0.25
−50
−25
0
25
50
75
100
0
100 200 300 400 500 600 700 800
T
A
− Free-Air Tempertature − °C
f
− Clock Frequency − kHz
(CLK)
Figure 6
Figure 7
9
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ꢄꢅ
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ꢃ
ꢄꢅ
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ꢉ
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ꢌ
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ꢋ
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SLAS148 − SEPTEMBER 1996
TYPICAL CHARACTERISTICS
TLV0831
TLV0831
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
CLOCK FREQUENCY
0.3
0.5
0.4
f
= 250 kHz
V
T
A
= 3.3 V
(CLK)
CS = High
CC
= 25°C
V
CC
= 3.6 V
V
= 3.3 V
= 3 V
0.3
0.2
CC
0.2
V
CC
0.1
0
0.1
−50
−25
0
25
50
75
100
0
100
200
300
400
500
T
A
− Free-Air Temperature — °C
f
− Clock Frequency − kHz
(CLK)
Figure 8
Figure 9
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
16.5
V
CC
= 3.3 V
16
15.5
15
I
OL (DO = 3.3 V)
−I
OH (DO = 0 V)
−I
OH (DO = 2.4 V)
14.5
I
OL (DO = 0.4 V)
14
−50
−25
0
25
50
75
100
T
A
− Free-Air Temperature − °C
Figure 10
10
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SLAS148 − SEPTEMBER 1996
TYPICAL CHARACTERISTICS
1
0.5
0
V
= 3.3 V
ref
= 25°C
−0.5
−1
T
A
F
V
= 250 kHz
(CLK)
= 3.3 V
DD
0
32
64
96
128
160
192
224
256
Output Code
Figure 11. Differential Nonlinearity With Output Code
1
V
= 3.3 V
ref
= 25°C
T
A
F
V
= 250 kHz
0.5
0
(CLK)
= 3.3 V
DD
−0.5
−1
0
32
64
96
128
160
192
224
256
Output Code
Figure 12. Integral Nonlinearity With Output Code
1
V
= 3.3 V
ref
= 25°C
T
A
0.5
0
F
V
= 250 kHz
(CLK)
= 3.3 V
DD
−0.5
−1
0
32
64
96
128
160
192
224
256
Output Code
Figure 13. Total Unadjusted Error With Output Code
11
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