TLV1570IPWLE [TI]
IC,DATA ACQ SYSTEM,8-CHANNEL,10-BIT,TSSOP,20PIN,PLASTIC;
| 型号： | TLV1570IPWLE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,DATA ACQ SYSTEM,8-CHANNEL,10-BIT,TSSOP,20PIN,PLASTIC 转换器 |
| 文件： | 总28页 (文件大小：480K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
Fast Throughput Rate: 1.25 MSPS at 5 V,
625 KSPS at 3 V
applications
Mass Storage and Hard Disk Drive
Automotive
Wide Analog Channel Input: 0 V to AV
Eight Analog Input Channels
Channel Auto-Scan
DD
Digital Servos
Process Control
Differential Nonlinearity Error: < ±1 LSB
Integral Nonlinearity Error: < ±1 LSB
Signal-to-Noise and Distortion Ratio: 57 dB
Single 2.7-V to 5.5-V Supply Operation
General Purpose DSP
Image Sensor Processing
DW OR PW PACKAGE
(TOP VIEW)
Very Low Power: 40 mW at 5.5 V,
8 mW at 2.7 V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CH4
CH3
CH2
CH1
CH0
AIN
MO
CH5
CH6
CH7
Auto-Power Down: 300 µA Max
Software Power Down: 10 µA Max
Glueless Serial Interface to TMS320 DSPs
and (Q)SPI Compatible Microcontrollers
DV
AV
DD
DD
DGND
AGND
REF
CS
Programmable Internal Reference Voltage:
3.8-V Reference for 5-V Operation,
2.3-V Reference for 3-V Operation
FS
SCLK
SDIN
SDOUT
description
The TLV1570 is a 10-bit data acquisition system that combines an 8-channel input multiplexer (MUX), a
high-speed 10-bit ADC, an on-chip reference, and a high-speed serial interface. The device contains an on-chip
control register allowing control of channel selection, conversion start, reference voltage levels, and power
down via the serial port. The MUX is independently accessible, which allows the user to insert a signal
conditioning circuit such as an anti-aliasing filter or an amplifier, if required, between the MUX and the ADC.
Therefore one signal conditioning circuit can be used for all eight channels.
The TLV1570 operates from a single 2.7-V to 5.5-V power supply. The device accepts an analog input range
from 0 V to AV
and digitizes the input at a maximum 1.25 MSPS throughput rate. Power dissipation is only
DD
8 mW with a 2.7-V supply or 40 mW with a 5.5-V supply. The device features an auto-power down mode that
automatically powers down to 300 µA, 10 ns after a conversion is performed. With software power down
enabled, the device is further powered down to only 10 µA.
The TLV1570 communicates with digital microprocessors via a simple 4- or 5-wire serial port that interfaces
directly to Texas Instruments TMS320 DSPs, and SPI and QSPI compatible microcontrollers without using
additional glue logic.
A very high throughput rate, a simple serial interface, and low power consumption make the TLV1570 an ideal
choice for high-speed digital signal processing requiring multiple analog inputs.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
SMALL OUTLINE
(DW)
SMALL OUTLINE
(PW)
0°C to 70°C
TLV1570CDW
TLV1570IDW
TLV1570CPW
TLV1570IPW
–40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
functional block diagram
AV
DD
MO
AIN
DV
DD
REFERENCE
REF
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
REF+
MUX
10-BIT
SAR ADC
REF–
AGND
SCLK
SDIN
CS
SDOUT
FS
I/O REGISTERS
AND CONTROL LOGIC
AGND
DGND
Terminal Functions
TERMINAL
NAME
AGND
AIN
AV
I/O
DESCRIPTION
NO.
14
Analog ground
20
I
ADC analog input
15
Analog supply voltage, 2.7 V to 5.5 V
Analog input channels 0 – 7
DD
CH0 – CH7
5,4,3,2,1,
18,17,16
I
I
CS
12
Chip Select. A low level signal on CS enables the TLV1570. A high level signal on CS disables the device
and disconnects power to the TLV1570.
DGND
7
6
8
Digital ground
DV
FS
Digital supply voltage, 2.7 V to 5.5 V
DD
I
Frame sync. The falling edge of the frame sync pulse from a DSP indicates the start of a serial data frame
shifted out of the TLV1570. FS is pulled high when interfaced to a microcontroller.
MO
19
13
O
I
On-chip MUX analog output
REF
Reference voltage input. The voltage applied to REF defines the input span of the TLV1570. In external
reference mode, a 0.1 µF decoupling capacitor must be placed between the reference and AGND. This
is not required for internal reference mode.
SCLK
SDIN
9
I
I
Serialclockinput. SCLKsynchronizestheserialdatatransferandisalsousedforinternaldataconversion.
Serial data input used to configure the internal control register.
10
11
SDOUT
O
Serial data output. A/D conversion results are output at SDOUT.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
detailed description
analog-to-digital converter
The TLV1570 ADC uses the SAR architecture described in this section. The CMOS threshold detector in the
successive-approximation conversion system determines the value of each bit by examining the charge on a
seriesofbinary-weightedcapacitors(seeFigure1). Inthefirstphaseoftheconversionprocess, theanaloginput
is sampled by closing the S switch and all S switches simultaneously. This action charges all of the capacitors
C
T
to the input voltage.
S
C
Threshold
Detector
To Output
Latches
512
Node 512
256
128
8
4
2
1
1
REF+
REF+
REF+
REF+
REF+
REF+
REF+
REF–
REF–
REF–
REF–
REF–
REF–
REF–
REF–
S
S
S
S
S
S
S
S
T
T
T
T
T
T
T
T
V
I
NOTE: REF– is tied to AGND
Figure 1. Simplified Model of the Successive-Approximation System
In the next phase of the conversion process, all S and S switches are opened and the threshold detector
T
C
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)
voltage (REF– is tied to AGND). In the switching sequence, ten capacitors are examined separately until all ten
bits are identified and then the charge-convert sequence is repeated. In the first step of the conversion phase,
the threshold detector looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the
REF+ voltage, and the equivalent nodes of all the other capacitors on the ladder are switched to REF–. If the
voltageatthesummingnodeisgreaterthanthetrippointofthethresholddetector(approximatelyone-halfV ),
CC
a bit 0 is placed in the output register and the 512-weight capacitor is switched to REF–. If the voltage at the
summing node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the
512-weight capacitor remains connected to REF+ through the remainder of the successive-approximation
process. The process is repeated for the 256-weight capacitor, the 128-weight capacitor, and so forth down the
line until all bits are counted.
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.
In the case of the TLV1570, REF– is tied to ground and REF+ is connected to the REF input.
The TLV1570 can be programmed to use the on-chip internal reference (DI6=1). The user can select between
two values of internal reference, 2.3 V or 3.8 V, using the control bit DI5.
During internal reference mode, the reference voltage is not output on the REF pin. Therefore it cannot be
decoupled to analog ground (AGND), which acts as the negative reference for the ADC, using an external
capacitor. Hence this mode requires the ground noise to be very low. The REF pin can be left open in this mode.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
sampling frequency, f
s
The TLV1570 requires 16 SCLKs for each sampling and conversion, therefore the equivalent maximum
sampling frequency achievable with a given SCLK frequency is:
f
= (1/16)f
SCLK
s(MAX)
power down
The TLV1570 offers two different power-down options. With auto power-down mode enabled, (DI4=0) the ADC
proceeds to power down if FS is not detected on the 17th falling SCLK edge of a cycle (a cycle starts with FS
being detected on a falling edge of SCLK) in DSP mode and after 16 SCLKs in µC mode. The TLV1570 will
recover from auto power down when FS goes high in DSP mode or when the next SCLK comes in µC mode.
In the case of software power down, the ADC goes to the software power-down state one cycle after CR.DI15
is set to 1. Unlike auto power down which recovers in 1 SCLK, software power down takes 16 SCLKs to recover.
SOFTWARE
DESCRIPTION
AUTO POWER DOWN
POWERDOWN
CS = DV
DD
Maximum power down dissipation current
Comparator
300 µA
10 µA
Power down
Power down
Active
Powerdown
Powerdown
Powerdown
Not saved
1 µs
†
Clock buffer
Reference
Register
Not saved
1 SCLK
Minimum power down time
Minimum resume time
1 SCLK
800 ns
DSP mode
No FS present one SCLK after previous conversion completed
CR.DI15 set to 1
CR.DI15 set to 1
CR.DI15 set to 1
CR.DI15 set to 1
Power down
Microprocessor mode (FS = 1) SCLK stopped after previous conversion completed
DSP mode FS present
Microprocessor mode (FS = 1) SCLK present
Only in DSP mode is input buffer of clock in power-down mode.
Power up
†
‡
Thesoftwarepowerdownenable/disablebitisnotacteduntilthestartofthenextcycle(seesectionconfiguringtheTLV1570formoreinformation.
configuring the TLV1570
The TLV1570 is to be configured by writing the control bits to SDIN. The configuration will not take affect until
the next cycle. A new configuration is needed for each conversion. Once the channel input and other options
are selected, the conversion takes place in the next cycle. Conversion results are shifted out as conversion
progresses ( see Figure 2).
One Cycle
Second Cycle
17
32
SCLK
t
s
t
t
s
t
conv
conv
Configure Data 1
Configure Data 2
SDIN
SDOUT
Result 0
Result 1
Figure 2. TLV1570 Configuration Cycle Timing
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
configuration register (CR) definition
BIT
DESCRIPTION
5 V
3 V
Software power down:
X
X
DI15
DI14
0:
1:
Normal
Power down enabled
X
X
Reads out values of the internal register, 1 – read. Only DI15 – DI1 are read out.
X
X
X
X
These two bits select the self-test voltage to be applied to the ADC input during next clock cycle:
00: Allow AIN to come in normally
01: Apply AGND to AIN
10: Apply VREF/2 to AIN
11: N/A
DI13, DI12
Choose speed application
X
X
X
X
X
X
DI11
DI10
0:
1:
High speed (higher power consumption)
Low speed (lower power consumption)
This bit enables channel auto-scan function.
0:
1:
Auto-scan disabled
Auto-scan enabled
DI9 – DI7 These three bits select which of the eight DI9, DI8 These two bits select the channel swept
channels is to be used (if DI10 = 0).
sequence used by auto scan mode (if DI10 = 1)
Analog inputs CH0, CH1, CH2, ….., CH7
sequentially selected
000: Channel 0 selected as input
00:
Analog inputs CH1, CH3, CH5, CH7
001: Channel 1 selected as input
010: Channel 2 selected as input
011: Channel 3 selected as input
01:
sequentially selected
Analog inputs CH0, CH2, CH4, CH6
sequentially selected
10:
DI9, DI8, DI7
Analog inputs CH7, CH6, CH5, ….., CH0
sequentially selected
11:
100: Channel 4 selected as input
101: Channel 5 selected as input
110: Channel 6 selected as input
111: Channel 7 selected as input
Selects Internal or external reference voltage:
DI7 Auto-scan reset
0:
1:
No reset
Reset autoscan sequence
X
X
DI6
DI5
0:
1:
External
Internal
Selects internal reference voltage value to be applied to the ADC during next conversion cycle.
0:
1:
2.3 V
3.8 V
X
X
X
X
Enables/disables auto-power down function:
DI4
DI3
1:
0:
Enable
Disable
Performance optimizer – linearity
0: AV
1: AV
= 5.5 V to 3.6 V
= 3.5 V to 2.7 V
X
X
DD
DD
DI2
DI1
DI0
Always write 0 (reserved bit)
Always write 0 (reserved bit)
Always write 0 (reserved bit)
X
X
X
X
X
X
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
initialization-software sequence
This sequence shows the default settings, unless otherwise specified. The ADC requires that the user write to
it every cycle. There is a cycle delay before control bits are implemented.
Example 1. Normal Sample Mode With Internal Reference
WRITE TO CHANNEL
OUPUT FROM
SDOUT
CYCLE
COMMENT
SDIN
0040h
01C0h
0040h
8040h
0040h
SAMPLED
1st
2nd
3rd
4th
5th
N/A
N/A
3
Invalid
No analog input channel sampled
No analog input channel sampled
Invalid
From Channel 3
From Channel 0
Invalid
0
Software power down enabled
N/A
Software power down mode, no analog input channel sampled
Recovery time, no analog input channel sampled (16 SCLKs if AV
= 5 V and
DD
Wait 800 ns
f
= 20 MHz)
CLK
6th
7th
0140h
0040h
N/A
2
Invalid
Recovery time, no analog input channel sampled
From Channel 2
Example 2. Auto Scan Mode
WRITE TO CHANNEL OUTPUT FROM
CYCLE
COMMENT
SDIN
0480h
0480h
0400h
0400h
0400h
0400h
0400h
0400h
0400h
0400h
0400h
SAMPLED
SDOUT
1st
2nd
3rd
4th
N/A
N/A
0
Invalid
Auto-scan reset enabled, no analog input channel sampled
No analog input channel sampled
Invalid
From Channel 0
From Channel 1
From Channel 2
From Channel 3
From Channel 4
From Channel 5
From Channel 6
From Channel 7
From Channel 0
1
5th
2
6th
3
7th
4
8th
5
9th
6
10th
11th
7
0
NOTE: If software power down is enabled during auto-scan mode, the next channel in the sequence is skipped.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
initialization-software sequence (continued)
Example 3. Auto-Scan Mode
This example shows a change in sequence in the middle of the current sequence. The following shows that after
the initial auto-scan reset, a reset is not necessary again when switching channel sequences.
CYCLE WRITE TO CHANNEL OUTPUT FROM
COMMENT
SDIN
0480h
0480h
0400h
0700h
0700h
0700h
0700h
0700h
0700h
0700h
0700h
0700h
SAMPLED
SDOUT
1st
2nd
3rd
4th
N/A
N/A
0
N/A
N/A
No analog input channel sampled
Auto-scan reset enabled, no analog input channel sampled
Start of sequence 0
From Channel 0
From Channel 1
From Channel 7
From Channel 6
From Channel 5
From Channel 4
From Channel 3
From Channel 2
From Channel 1
From Channel 0
1
Enable channel sequence 3 (no auto-scan reset required)
Start of sequence 3
5th
7
6th
6
7th
5
8th
4
9th
3
10th
11th
12th
2
1
0
Example 4. Auto-Scan Mode
This example shows a switch in sequence in the course of a sequence. The following shows that a particular
sequence does not have to be continued if remaining channels do not need to be sampled (i.e., only channel
1 through channel 5 sampled, not channels 6, 7, 8)
CYCLE WRITE TO CHANNEL
OUPUT FROM
SDOUT
COMMENT
SDIN
0480h
0480h
0400h
0400h
0400h
0400h
0400h
0480h
0400h
0400h
0400h
SAMPLED
1st
2nd
3rd
4th
N/A
N/A
0
N/A
No analog input channel sampled
N/A
Auto-scan reset enabled, no analog input channel sampled
From Channel 0
From Channel 1
From Channel 2
From Channel 3
From Channel 4
From Channel 5
From Channel 0
From Channel 1
From Channel 2
1
5th
2
6th
3
7th
4
8th
5
Auto-scan reset enabled
9th
0
Sequence is reset to channel 0
10th
11th
1
2
The TLV1570 is a 800-ns 10-bit 8-analog input channel analog-to-digital converter with a throughput of up to
1.25 MSPS at 5 V and up to 625 KSPS at 3 V respectively. To run at its fastest conversion rate, it must be clocked
at 20 MHz at 5-V or 10 MHz at 3-V. The TLV1570 can be easily interfaced to microcontrollers, ASICs, DSPs,
or shift registers. The TLV1570 serial interface is designed to be fully compatible with Serial Peripheral Interface
(SPI) and TMS320 DSP serial ports. No additional hardware is required to interface between the TLV1570 and
a microcontroller (µCs) with a SPI serial port or a TMS320 DSP. However, the speed is limited by the SCLK rate
of the µC or the DSP.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
initialization-software sequence (continued)
The TLV1570 interfaces to a DSP over five lines: CS, SCLK, SDOUT, SDIN, and FS, and interfaces to a µC over
fourlines:CS, SCLK, SDOUT, andSDIN. TheFSinputshouldbepulledhighinµCmode. Thedeviceisin3-state
and power-down mode when CS is high. After CS falls, the TLV1570 checks the FS input at the CS falling edge
to determine the operation mode. If FS is low, DSP mode is set, otherwise µC mode is set.
TLV1570
TMS320
CS
XF
SCLK
FS
CLKX
CLKR
FSX
FSR
DX
SDIN
DR
SDOUT
Figure 3. DSP to TLV1570 Interface
TLV1570
CS
µC
I/O Terminal
SCLK
SCLK
DV
FS
DD
SDIN
DX
DR
SDOUT
Figure 4. µC to TLV1570 Interface
grounding and decoupling considerations
General practices should apply to the PCB design to limit high frequency transients and noise that are fed back
into the supply and reference lines (see Figure 5). This requires that the supply and reference pins be sufficiently
bypassed. In most cases 0.1 µF ceramic chip capacitors are adequate to keep the impedance low over a wide
frequency range. Since their effectiveness depends largely on the proximity to the individual supply pin. They
should be placed as close to the supply pins as possible.
To reduce high frequency and noise coupling, it is highly recommended that digital and analog ground be
shorted immediately outside the package. This can be accomplished by running a low impedance line between
DGND and AGND, under the package.
TLV1570
DV
AV
DD
DD
100 nF
100 nF
100 nF
DGND
AGND
REF
Figure 5. Placement of Decoupling Capacitors
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
power supply ground layout
Printed circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the ADC AGND terminal to the system analog ground plane making sure that analog ground
currents are well managed.
simplified analog input analysis
Using the equivalent circuit in Figure 6, the time required to charge the analog input capacitance from 0 to V
S
within 1/2 LSB, t (1/2 LSB), can be derived as follows:
ch
The capacitance charging voltage is given by:
–t
R C
t
ch
1–e
i
V
V
C(t)
R = R + R
i
S
where
(1)
t
s
R = R
+ R
i(MUX)
i
i(ADC)
t
= Charge time
ch
The input impedance R is 718 Ω at 5 V, and is higher (~ 1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given
i
by:
(2)
V (1/2 LSB) = V – (V /2048)
C
S
S
Equating equation 1 to equation 2 and solving for cycle time t gives:
c
–t
R C
t
ch
1–e
i
V
V
2048
V
S
S
S
(3)
and time to change to 1/2 LSB (minimum sampling time) is:
(1/2 LSB) = R × C × ln(2048)
t
ch
t
i
where
ln(2048) = 7.625
Therefore, with the values given, the time for the analog input signal to settle is:
(1/2LSB)=(R + 718 Ω)× 15 pF × ln(2048)
(4)
(5)
(6)
t
ch
s
This time must be less than the converter sample time shown in the timing diagrams. Which is 6x SCLK.
(1/2 LSB) ≤ 6x 1/f
t
ch
(SCLK)
Therefore the maximum SCLK frequency is:
Max(f ) = 6/t (1/2 LSB) = 6/(ln(2048) × R × C )
(SCLK)
ch
t
i
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
simplified analog input analysis (continued)
†
Driving Source
TLC1570
V
V
= Input Voltage at AIN
= External Driving Source Voltage
I
S
s
MO
R
i(MUX)
AIN
R = Source Resistance
R
R
C = Input Capacitance
V
R
R
s
i(ADC)
V
I
= Input Resistance of ADC
= Input Resistance (MUX on resistance)
i(ADC)
i(MUX)
V
S
V
C
i
C
C
= Capacitance Charging Voltage
i
15 pF
†
Driving source requirements:
•
•
Noise and distortion for the source must be equivalent to the resolution of the converter.
R must be real at the input frequency.
s
Figure 6. Equivalent Input Circuit Including the Driving Source
definitions of specifications and terminology
integral nonlinearity (INL)
Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.
differential nonlinearity (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.
zero offset
The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.
gain error
The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.
signal-to-noise ratio + distortion (SINAD)
SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components
below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in
decibels.
effective number of bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
It is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
definitions of specifications and terminology (continued)
total harmonic distortion (THD)
Total harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the
measured input signal and is expressed as a percentage or in decibels.
spurious free dynamic range (SFDR)
Spurious free dynamic range is the difference in dB between the rms amplitude of the input signal and the peak
spurious signal.
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, AGND to AV , DGND to DV
Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to AV +0.3 V
Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AV +0.3 V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to DV +0.3 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V
DD
DD
DD
DD
DD
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
J
Operating free-air temperature range, T : TLV1570C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLV1570I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supplies
MIN
2.7
TYP
MAX
5.5
UNIT
V
Analog supply voltage, AV
(see Note 1)
(see Note 1)
DD
Digital supply voltage, DV
2.7
5.5
V
DD
NOTE 1: Abs (AV
– DV ) < 0.5 V
DD
DD
analog inputs
MIN
TYP
MAX
UNIT
Analog input voltage, AIN
AGND
V
REF
V
DV
DV
= 3.3 V to 2.7 V
= 5.5 V to 4.5 V
55% AV
AV
DD
DD
DD
DD
DD
Reference input voltage, REF
V
60% AV
AV
DD
digital inputs
MIN
TYP
MAX
UNIT
V
High-level input voltage, V
DV
DV
DV
DV
DV
DV
DV
DV
= 2.7 V to 5.5 V
= 2.7 V to 5.5 V
= 5.5 V to 4.5 V
= 3.6 V to 2.7 V
= 5.5 V to 4.5 V
= 3.6 V to 2.7 V
= 5.5 V to 4.5 V
= 3.6 V to 2.7 V
2.1
IH
DD
DD
DD
DD
DD
DD
DD
DD
Low-level input voltage, V
0.8
20
10
V
IL
Input SCLK frequency
MHz
ns
1
23
46
23
46
4
SCLK pulse duration, clock high, t
w(SCLKH)
SCLK pulse duration, clock low, t
ns
w(SCLKL)
I/O and control rise time, SCLK, FS, CS, SDIN
I/O and control fall time, SCLK, FS, CS, SDIN
ns
ns
4
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
electrical characteristics,over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)
digital specifications (SDOUT at 25 pF)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Logic inputs
I
I
High-level input current
Low-level input current
Input capacitance
DV
DV
= 5 V,
= 5 V,
V = 5 V
1
–1
15
µA
µA
pF
IH
DD
DD
I
V = 0 V
I
IL
C
Control inputs
5
I
Logic outputs
V
High-level output voltage
I
I
= 50 µA – 0.5 mA
DV –0.4
DD
V
OH
OL
OH
V
Low-level output voltage
= 50 µA – 0.5 mA
0.4
1
V
OL
I
I
High-impedance-state output current
Low-impedance-state output current
Output capacitance
µA
µA
pF
OZH
–1
OZL
C
5
O
dc specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Resolution
10
Bits
Accuracy
Integral nonlinearity, INL
Differential nonlinearity, DNL
Offset error
Best fit
±0.6
±1
±1
LSB
LSB
±0.65
E
E
±0.1 ±0.15 %FSR
O
Gain error
±0.1
±0.2 %FSR
G
Analog input
C
Input capacitance
15
20
±1
pF
µA
Ω
i
I
Input leakage current
V
= 0 V to AV
lkg
AIN DD
DV
DV
DV
DV
= 3 V,
= 5 V,
= 3 V,
= 5 V,
AV
AV
AV
AV
= 3 V
= 5 V
= 3 V
= 5 V
265
235
158
140
780
450
465
268
DD
DD
DD
DD
DD
DD
DD
DD
R
R
Input MUX ON resistance
Input MUX ON resistance
i(MUX)
i(ADC)
Ω
Ω
Ω
Voltage reference
REF Internal reference voltage
Internal reference mode, V
Internal reference mode, V
= 3 V
= 5 V
2.08
3.48
2.26
3.82
100
2.48
4.15
V
V
DD
DD
Temperature coefficient
Input resistance
ppm/°C
kΩ
r
i
External reference mode
External reference mode
3
C
Input capacitance
300
pF
i(VR)
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
electrical characteristics, over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)
dc specifications (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power supply
†
‡
AV
AV
AV
AV
= 2.7 V, DV
= 5.5 V, DV
= 2.7 V, DV
= 5.5 V, DV
= 2.7 V,
= 5.5 V,
= 2.7 V
= 5.5 V
f
f
= 10 MHz
= 20 MHz
3
7.2
8
5
8.5
13
mA
mA
DD
DD
DD
DD
DD
DD
DD
DD
SCLK
I
+ I
Operating supply current
Power dissipation
DD REF
SCLK
mW
mW
P
D
40
47
CS = AV
DD
3
10
AVDD = 2.7 V
AVDD = 5.5 V
µA
µA
CS = AGND
CS = AV
500
3
Software
I + I
DD REF
10
Supply current in
power down
DD
CS = AGND
2000
175
200
AVDD = 2.7V
AVDD = 5.5V
275
300
µA
µA
Auto
I + I
DD REF
†
‡
I
I
= 0.7 mA typ.
= 1.5 mA typ.
REF
REF
ac specifications
PARAMETER
TEST CONDITIONS
MIN
58
TYP
61
MAX
UNIT
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
f = 1.25 MSPS, AV
DD
= 5 V
s
53
56
f = 100 kHz,
i
70% of FS
56
61
f = 625 KSPS, AV
DD
= 3 V
= 5 V
= 3 V
= 5 V
s
53
55
Signal-to-noise
SNR
ratio
dB
61
f = 1.25 MSPS, AV
s
DD
56
f = 50 kHz,
i
90% of FS
61
f = 625 KSPS, AV
s
DD
55
55
53
53
52
58
f = 1.25 MSPS, AV
DD
s
55
f = 100 kHz,
i
70% of FS
58
f = 625 KSPS, AV
DD
= 3 V
s
54
Signal-to-noise
SINAD
dB
ratio + distortion
59
f = 1.25 MSPS, AV
DD
= 5 V
s
55
f = 50 kHz,
i
90% of FS
60
f = 625 KSPS, AV
DD
= 3 V
s
55
–60
–70
–60
–66
–64
–72
–63
–68
–55
–58
–55
–58
f = 1.25 MSPS, AV
DD
= 5 V
s
f = 100 kHz,
i
70% of FS
f = 625 KSPS, AV
DD
= 3 V
s
Total harmonic
distortion
THD
dB
f = 1.25 MSPS, AV
DD
= 5 V
s
f = 50 kHz
i
90% of FS
f = 625 KSPS, AV
DD
= 3 V
s
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
ac specifications (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
–63
–73
–61
–68
–66
–75
–65
–70
9.3
MAX
–57
–59
–57
–60
UNIT
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
External reference
Internal reference
f = 1.25 MSPS, AV
DD
= 5 V
s
f = 100 kHz,
i
70% of FS
f = 625 KSPS, AV
DD
= 3 V
s
Spurious-free
dynamic range
SFDR
dB
f = 1.25 MSPS, AV
DD
= 5 V
s
f = 50 kHz,
i
90% of FS
f = 625 KSPS, AV
DD
= 3 V
s
8.8
8.6
8.6
8.4
f = 1.25 MSPS, AV
DD
= 5 V
s
8.9
f = 100 kHz,
i
70% of FS
9.3
f = 625 KSPS, AV
DD
= 3 V
s
8.8
Effective num-
ber of bits
ENOB
dB
9.5
f = 1.25 MSPS, AV
DD
= 5 V
s
8.9
f = 50 kHz,
i
90% of FS
9.5
f = 625 KSPS, AV
DD
= 3 V
s
8.9
Analog Input
Channel-to-
channel cross-
talk
–75
dB
–1 dB full-scale input sine wave
12
15
15
25
20
35
MHz
MHz
MHz
MHz
Full-power
bandwidth
BW
BW
–3 dB full-scale input sine wave
–1 dB
–3 dB
Small-signal
bandwidth
AV
AV
= 5 V
= 3 V
0.0625
0.0625
1.25
DD
f
s
Sampling rate
MSPS
0.625
DD
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
†
timing requirements
PARAMETER
TEST CONDITIONS
MIN
50
TYP
MAX
UNIT
DV
DV
= 5.5 V to 4.5 V
= 3.6 V to 2.7 V
ns
DD
DD
t
SCLK cycle time
c(SCLK)
100
100
t
Pulse duration, chip select
Sampling period
ns
w1
s
SLCK
cycles
t
6
SLCK
cycles
t
Conversion period
10
conv
t
s1
t
h1
t
s2
t
h2
t
d1
t
d2
t
d3
Setup time, FS to SCLK falling edge in DSP mode
Hold time, FS to SCLK falling edge in DSP mode
Setup time, FS to CS falling edge in DSP mode
5
2
ns
ns
ns
ns
ns
ns
ns
5.5
9
Hold time, FS to CS falling edge in DSP mode
Delay time, FS falling edge to next SCLK falling edge in DSP mode
Delay time, SCLK rising edge after CS falling edge in µC mode
6
4
Delay time, output after SCLK rising edge in µC mode and DSP
mode
10
20
t
s3
t
h3
t
r
Setup time, serial input data to SCLK falling edge
Hold time, serial input data to SCLK falling edge
Rise time
10
4
ns
ns
ns
3
200
†
Specifications subject to change without notice.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
t
c(SCLK)
1
2
3
SCLK
CS
t
w1
t
s1
t
h1
t
d1
FS
t
s3
t
h3
t
s2
t
h2
DI15
MSB
DI14
DI13
SDIN
t
d3
0
0
SDOUT
Figure 7. DSP Mode Timing Diagrams
t
d2
1
2
3
4
SCLK
CS
t
w1
FS
t
s3
t
h3
DI15
DI14
DI13
DI12
SDIN
MSB
t
d3
0
0
0
SDOUT
Figure 8. µC Mode Timing Diagrams
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
ANALOG MUX INPUT RESISTANCE
TOTAL SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
350
300
8
6
4
AV
DD
= 5.5 V
AV
DD
= 2.7 V, AIN = 2 V
250
200
AV
DD
= 5.5 V, AIN = 3.8 V
AV
DD
= 2.7 V
150
100
2
0
50
0
–45
25
90
–45
25
90
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 10
Figure 9
SUPPLY CURRENT
vs
GAIN
vs
CLOCK FREQUENCY (SCLK)
INPUT FREQUENCY
8
7
1
V
= 5.5 V
DD
DD
0
6
–1
––2
–3
V
= 5 V, AIN = 90% of FS,
5
4
3
DD
REF = 5 V, T = 25°C
A
V
= 2.7 V
2
–4
–5
1
0
2.5
5
6.2 7.5
10
12.5 15.4 18
20
0
1
10
100
f – Frequency – MHz
f – Frequency – MHz
Figure 11
Figure 12
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
0.8
0.6
0.4
V
= 2.7 V, Internal REF = 2.3 V,
CC
SCLK = 10 MHz,
= 25°C
T
A
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
511
1023
Samples
Figure 13
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
V
= 2.7 V, Internal REF = 2.3 V,
CC
SCLK = 10 MHz,
= 25°C
0.8
0.6
0.4
0.2
T
A
0
–0.2
–0.4
–0.6
–0.8
–1
0
511
1023
Samples
Figure 14
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
0.8
0.6
0.4
V
= 2.7 V, External REF = 2.7 V,
CC
SCLK = 10 MHz,
= 25°C
T
A
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
511
1023
Samples
Figure 15
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
V
= 2.7 V, External REF = 2.7 V,
CC
SCLK = 10 MHz,
= 25°C
0.8
0.6
0.4
T
A
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
511
1023
Samples
Figure 16
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
0.8
0.6
V
= 5.5 V, Internal REF = 3.8 V,
CC
SCLK = 20 MHz,
= 25°C
T
A
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
511
1023
Samples
Figure 17
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
0.8
0.6
0.4
0.2
0
V
= 5.5 V, Internal REF = 3.8 V,
CC
SCLK = 20 MHz,
= 25°C
T
A
–0.2
–0.4
–0.6
–0.8
0
511
1023
Samples
Figure 18
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
0.8
0.6
V
= 5.5 V, External REF = 5.5 V,
CC
SCLK = 20 MHz,
= 25°C
T
A
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
511
1023
Samples
Figure 19
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
V
= 5.5 V, External REF = 5.5 V,
CC
SCLK = 20 MHz,
= 25°C
0.8
0.6
0.4
T
A
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
511
1023
Samples
Figure 20
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
0.8
0.6
V
= 5.5 V, External REF = 3.3 V,
CC
SCLK = 20 MHz,
= 25°C
T
A
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
511
1023
Samples
Figure 21
INTEGRAL NONLINEARITY ERROR
vs
DIGITAL OUTPUT CODE
1
0.8
0.6
0.4
0.2
0
V
= 5.5 V, External REF = 3.3 V,
CC
SCLK = 20 MHz,
= 25°C
T
A
–0.2
–0.4
–0.6
–0.8
0
511
1023
Samples
Figure 22
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
EFFECTIVE NUMBER OF BITS
EFFECTIVE NUMBER OF BITS
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
12
10
8
12
10
8
AV
DD
= DV
= 5 V,
DD
External REF = 5 V
AV
DD
= DV
= 3 V,
DD
External REF = 3 V
6
6
4
4
2
2
0
0
0
100
200
300
400
500
600
0
50
100
150
200
250
300
f – Frequency – kHz
f – Frequency – kHz
Figure 23
Figure 24
EFFECTIVE NUMBER OF BITS
EFFECTIVE NUMBER OF BITS
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
10
10
9
8
9
8
7
6
7
6
5
4
3
2
5
4
3
2
AV
DD
= DV
= 3 V,
AV
DD
= DV
= 5 V,
DD
Internal REF = 2.3 V
DD
Internal REF = 3.8 V
1
0
1
0
0
50
100
150
200
250
300
0
100
200
300
400
500
600
f – Frequency – kHz
f – Frequency – kHz
Figure 25
Figure 26
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM
vs
FREQUENCY
AIN = 200 kHz,
SCLK = 20 MHz,
0
AV
= DV
= 3 V,
DD
DD
Internal REF = 2.3 V
–20
–40
–60
–80
–100
–120
0
100
200
300
400
500
600
Frequency – KHz
Figure 27
FAST FOURIER TRANSFORM
vs
FREQUENCY
AIN = 200 kHz,
SCLK = 20 MHz,
0
AV
= DV
= 5 V,
DD
DD
Internal REF = 3.8 V
–20
–40
–60
–80
–100
–120
0
100
200
300
400
500
600
Frequency – KHz
Figure 28
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
FAST FOURIER TRANSFORM
vs
FREQUENCY
AIN = 200 kHz,
SCLK = 20 MHz,
0
AV
= DV
= External REF = 3 V
DD
DD
–20
–40
–60
–80
–100
–120
0
100
200
300
Frequency – KHz
400
500
600
Figure 29
FAST FOURIER TRANSFORM
vs
FREQUENCY
AIN = 200 kHz,
0
SCLK = 20 MHz,
AV = DV = External REF = 5 V
DD
DD
–20
–40
–60
–80
–100
–120
0
100
200
300
400
500
600
Frequency – KHz
Figure 30
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
Figure 31. Typical Timing Diagram for DSP Application
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV1570
2.7 V TO 5.5 V 8-CHANNEL 10-BIT 1.25-MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER
SLAS169A – DECEMBER 1997– REVISED SEPTEMBER 1998
TYPICAL CHARACTERISTICS
Figure 32. Typical Timing Diagram for µC Application
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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