TLV171QDBVRQ1 [TI]
适用于成本敏感型应用的汽车级、单路、36V、3MHz、低功耗运算放大器 | DBV | 5 | -40 to 125;
| 型号： | TLV171QDBVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于成本敏感型应用的汽车级、单路、36V、3MHz、低功耗运算放大器 | DBV | 5 | -40 to 125 放大器 运算放大器 |
| 文件： | 总33页 (文件大小：1302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLV171-Q1, TLV2171-Q1, TLV4171-Q1
SBOS858 –APRIL 2017
TLVx171-Q1 36-V, Single-Supply, General-Purpose
Operational Amplifier for Cost-Sensitive Automotive Systems
1 Features
2 Applications
1
•
•
Qualified for Automotive Applications
•
Automotive
AEC-Q100 Test Guidance With the Following
Results:
–
–
–
–
–
ADAS
Body Electronics
Lighting
–
Device Temperature Grade 1:
–40°C to +125°C Ambient Operating
Temperature
Current Sensing
Power Train
–
Device HBM ESD Classification Level:
–
–
Level 3A for TLV171-Q1 and TLV2171-Q1
Level 2 for TLV4171-Q1
3 Description
The TLVx171-Q1 family of devices is a 36-V,
single-supply, low-noise operational amplifier (op
amp) with the ability to operate on supplies ranging
from 4.5 V (± 2.25 V) to 36 V (±18 V). This series is
available in multiple packages and offers low offset,
drift, and low quiescent current. The single, dual, and
quad versions all have identical specifications for
maximum design flexibility.
–
Device CDM ESD Classification Level
–
–
Level C4A for TLV171-Q1
Level C6 for TLV2171-Q1and TLV4171-Q1
•
Supply Range:
–
–
Single-Supply: 4.5 V to 36 V
Dual-Supply ±2.25 V to ±18 V
Device Information(1)
•
•
•
•
Low Noise: 16 nV/√Hz at 1 kHz
PART NUMBER
PACKAGE
BODY SIZE (NOM)
2.90 mm × 1.60 mm
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
8.65 mm × 3.91 mm
5.00 mm × 4.40 mm
Low Offset Drift: ±1 µV/°C (Typical)
Input Range Includes Negative Supply
TLV171-Q1
SOT-23 (5)
SOIC (8)
Input Range Operates to Positive Supply With
Reduced Performance
TLV2171-Q1
TLV4171-Q1
VSSOP (8)
SOIC (14)
TSSOP (14)
•
•
•
•
•
Rail-to-Rail Output
Gain Bandwidth: 3 MHz
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Low Quiescent Current: 525 µA per Amplifier
Common-Mode Rejection: 120 dB (Typical)
Low Input Bias Current: 10 pA
Offset Voltage vs Power Supply
Offset Voltage vs Common-Mode Voltage: VSUPPLY
= ±18 V
1000
350
VSUPPLY
= 2ꢀ25 V ꢁt 18 V
10 Typical Uniꢁs Shtwn
10 Typical Units Shown
800
250
150
50
600
400
200
0
-50
-200
-400
-600
-150
-250
-350
-800
VCM = -18.1 V
0
2
4
6
8
10
12
14
16
18
20
-1000
-20
-15
-10
-5
0
5
10
15
20
VSUPPLY (V)
VCM (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV171-Q1, TLV2171-Q1, TLV4171-Q1
SBOS858 –APRIL 2017
www.ti.com
Table of Contents
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 19
Application and Implementation ........................ 20
8.1 Application Information............................................ 20
8.2 Typical Application .................................................. 21
Power Supply Recommendations...................... 23
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Description (continued)......................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
6.1 Absolute Maximum Ratings ...................................... 7
6.2 ESD Ratings.............................................................. 7
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information: TLV171-Q1 ............................. 8
6.5 Thermal Information: TLV2171-Q1 ........................... 8
6.6 Thermal Information: TLV4171-Q1 ........................... 8
6.7 Electrical Characteristics........................................... 9
6.8 Typical Characteristics............................................ 11
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ....................................... 17
8
9
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 24
11.1 Documentation Support ........................................ 24
11.2 Related Links ........................................................ 24
11.3 Community Resource............................................ 25
11.4 Trademarks........................................................... 25
11.5 Electrostatic Discharge Caution............................ 25
11.6 Glossary................................................................ 25
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
Table 1. Revision History
DATE
REVISION
NOTES
April 2017
SBOS858
Initial release.
2
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SBOS858 –APRIL 2017
4 Description (continued)
Unlike most op amps, which are specified at only one supply voltage, the TLVx171-Q1 family of devices is
specified from 4.5 V to 36 V. Input signals beyond the supply rails do not cause phase reversal.
The TLVx171-Q1 family of devices is stable with capacitive loads up to 300 pF. The input can operate 100 mV
below the negative rail and within 2 V of the top rail during normal operation. The device can operate with full
rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail.
The TLVx171-Q1 op amp family is specified from –40°C to +125°C.
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SBOS858 –APRIL 2017
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5 Pin Configuration and Functions
TLV171-Q1 DBV Package
5-Pin SOT-23
Top View
V+
OUT
1
2
3
5
4
V-
-IN
+IN
Pin Functions
PIN
I/O
DESCRIPTION
NAME
+IN
NO.
3
I
Noninverting input
Inverting input
Output
–IN
4
I
OUT
V+
1
O
—
—
5
Positive (highest) power supply
Negative (lowest) power supply
V–
2
4
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SBOS858 –APRIL 2017
TLV2171-Q1 D or DGK Packages
8-Pin SOIC or VSSOP
Top View
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
OUT B
–IN B
+IN B
Pin Functions
PIN
I/O
DESCRIPTION
NAME
+IN A
+IN B
–IN A
–IN B
OUT A
OUT B
V+
NO.
3
I
I
Noninverting input, channel A
Noninverting input, channel B
Inverting input, channel A
Inverting input, channel B
Output, channel A
5
2
I
6
I
1
O
O
—
—
7
Output, channel B
8
Positive (highest) power supply
Negative (lowest) power supply
V–
4
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SBOS858 –APRIL 2017
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TLV4171-Q1 D and PW Packages
14-Pin SOIC and TSSOP
Top View
OUT A
-IN A
+IN A
V+
1
2
3
4
5
6
7
14 OUT D
13 -IN D
12 +IN D
11 V-
+IN B
-IN B
OUT B
10 +IN C
9
8
-IN C
OUT C
Pin Functions
PIN
I/O
DESCRIPTION
NAME
+IN A
+IN B
+IN C
+IN D
–IN A
–IN B
–IN C
–IN D
OUT A
OUT B
OUT C
OUT D
V+
NO.
3
I
I
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Inverting input, channel A
Inverting input, channel B
Inverting input, channel C
Inverting input, channel D
Output, channel A
5
10
12
2
I
I
I
6
I
9
I
13
1
I
O
O
O
O
—
—
7
Output, channel B
8
Output, channel C
14
4
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
V–
11
6
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SBOS858 –APRIL 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
Supply voltage, VS
Voltage
Signal input terminals
Current
(V–) – 0.5
(V+) + 0.5
±10
V
mA
Output short circuit(2)
Continuous
Junction temperature, TJ
Latch-up per JESD78D
Storage temperature, Tstg
150
150
°C
°C
Class 1
–65
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
TLV171-Q1 IN DBV PACKAGE
V(ESD) Electrostatic discharge
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
±4000
±500
V
TLV2171-Q1 IN D AND DGK PACKAGES
Human body model (HBM), per AEC Q100-002(1)
±4000
±1000
V(ESD)
Electrostatic discharge
V
V
Charged device model (CDM), per AEC Q100-011
TLV4171-Q1 IN D AND PW PACKAGES
Human body model (HBM), per AEC Q100-002(1)
±2000
±1000
V(ESD)
Electrostatic discharge
Charged device model (CDM), per AEC Q100-011
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5 (±2.25)
–40
NOM
MAX
36 (±18)
125
UNIT
Supply voltage (V+ – V–)
V
Specified operating temperature
°C
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6.4 Thermal Information: TLV171-Q1
TLV171-Q1
DBV (SOT-23)
5 PINS
277.3
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
193.3
121.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
51.8
ψJB
109.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: TLV2171-Q1
TLV2171-Q1
THERMAL METRIC(1)
D (SOIC)
8 PINS
116.1
69.8
DGK (VSSOP)
8 PINS
186.5
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
78
56.6
107.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
22.5
15.6
ψJB
56.1
106.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: TLV4171-Q1
TLV4171-Q1
THERMAL METRIC(1)
D (SOIC)
14 PINS
93.2
PW (TSSOP)
14 PINS
106.9
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
51.8
24.4
49.4
59.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
13.5
0.6
ψJB
42.2
54.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS858 –APRIL 2017
6.7 Electrical Characteristics
at TA = 25°C, VS = 4.5 V to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
OFFSET VOLTAGE
VOS Input offset voltage
Input offset voltage over temperature TA = –40°C to 125°C
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.75
±2.7
±3
mV
mV
dVOS/d Input offset voltage drift
TA = –40°C to 125°C
VS = 4.5 V to 36 V
1
µV/°C
dB
T
(over temperature)
Input offset voltage over temperature
vs power supply
PSRR
90
120
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Electrical Characteristics (continued)
at TA = 25°C, VS = 4.5 V to 36 V, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
±10
±4
pA
pA
IOS
NOISE
Input voltage noise
f = 0.1 Hz to 10 Hz
3
27
16
µVPP
f = 100 Hz
f = 1 kHz
nV/√Hz
nV/√Hz
en
Input voltage noise density
INPUT VOLTAGE
VCM
Common-mode voltage range(1)
(V–) – 0.1
90
(V+) – 2
V
VS = ±2.25 V
(V–) – 0.1 V < VCM < (V+) – 2 V
120
120
dB
Common-mode rejection ratio (over
temperature)
CMRR
VS = ±18 V
(V–) – 0.1 V < VCM < (V+) – 2 V
94
dB
INPUT IMPEDANCE
Differential
100 || 3
6 || 3
MΩ || pF
1012Ω || pF
Common-mode
OPEN-LOOP GAIN
Open-loop voltage gain (over
VS = 4.5 V to 36 V
(V–) + 0.35 V < VO < (V+) – 0.35 V
AOL
94
130
dB
temperature)
FREQUENCY RESPONSE
GBP
SR
Gain bandwidth product
3
MHz
V/µs
Slew rate
G = 1
1.5
To 0.1%, VS = ±18 V
G = 1, 10-V step
6
µs
tS
Settling time
To 0.01% (12 bit), VS = ±18 V
G = 1, 10-V step
10
2
µs
µs
Overload recovery time
V±IN × Gain > VS
G = 1, f = 1 kHz
VO = 3 VRMS
THD+N Total harmonic distortion + noise
0.0002%
OUTPUT
Voltage output swing from rail (over
temperature)
RL = 10 kΩ
AOL ≥ 110 dB
VO
(V–) + 0.35
(V+) – 0.35
V
Sourcing
Sinking
25
ISC
Short-circuit current
mA
–37
CLOAD
RO
Capacitive load drive
See Typical Characteristics
pF
Open-loop output resistance
f = 1 MHz, IO = 0 A
150
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per amplifier
TA = –40°C to 125°C
4.5
36
V
IO = 0 A, TA = –40°C to 125°C
525
695
µA
(1) The input range can be extended beyond (V+) – 2 V up to V+ at reduced performance. See Typical Characteristics and Detailed
Description for additional information.
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SBOS858 –APRIL 2017
6.8 Typical Characteristics
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Table 2. Characteristic Performance Measurements
DESCRIPTION
Offset Voltage Production Distribution
Offset Voltage vs Common-Mode Voltage
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Input Bias Current vs Temperature
FIGURE
Figure 1
Figure 2
Figure 3
Figure 5
Output Voltage Swing vs Output Current (Maximum Supply)
CMRR and PSRR vs Frequency (Referred-to Input)
0.1Hz to 10Hz Noise
Figure 6
Figure 7
Figure 8
Input Voltage Noise Spectral Density vs Frequency
Quiescent Current vs Supply Voltage
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15,
Figure 17
Figure 18, Figure 19
Figure 20, Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Open-Loop Gain and Phase vs Frequency
Closed-Loop Gain vs Frequency
Open-Loop Gain vs Temperature
Open-Loop Output Impedance vs Frequency
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
No Phase Reversal
Small-Signal Step Response (100 mV)
Large-Signal Step Response
Large-Signal Settling Time (10-V Positive Step)
Large-Signal Settling Time (10-V Negative Step)
Short-Circuit Current vs Temperature
Maximum Output Voltage vs Frequency
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6.8.1 Typical Characteristics
16
1000
800
Distribution Taken From 3500 Amplifiers
10 Typical Units Shown
14
12
10
8
600
400
200
0
-200
-400
-600
-800
-1000
6
4
2
VCM = -18.1 V
-15 -10
0
-20
-5
0
5
10
15
20
VCM (V)
Offset Voltage (mV)
Figure 2. Offset Voltage vs Common-Mode Voltage:
VSUPPLY (V) = ±18 V
Figure 1. Offset Voltage Production Distribution
10000
8000
6000
4000
2000
0
350
250
150
50
10 Typical Units Shown
VSUPPLY
= 2ꢀ25 V ꢁt 18 V
10 Typical Uniꢁs Shtwn
-50
-2000
-4000
-6000
-8000
-10000
Normal
Operation
-150
-250
-350
VCM = 18.1 V
15.5
16
16.5
17
17.5
18
18.5
0
2
4
6
8
10
12
14
16
18
20
VCM (V)
VSUPPLY (V)
Figure 3. Offset Voltage vs Common-Mode Voltage:
VSUPPLY (V) = ±18 V
Figure 4. Offset Voltage vs Power Supply
(Upper Stage)
10000
18
17
16
IB+
IB-
1000
100
10
1
IB
IOS
15
14.5
-14.5
-15
-40°C
+25°C
+85°C
+125°C
IOS
-16
-17
-18
0
-40 -25
0
25
50
75
100
125
0
2
4
6
8
10
12
14
16
Temperature (°C)
Output Current (mA)
Figure 5. Input Bias Current vs Temperature
Figure 6. Output Voltage Swing vs Output Current
(Maximum Supply)
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SBOS858 –APRIL 2017
Typical Characteristics (continued)
140
120
100
80
60
40
+PSRR
20
0
-PSRR
CMRR
1
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Time (1s/div)
Figure 7. CMRR and PSRR vs Frequency
(Referred-to Input)
Figure 8. 0.1- to 10-Hz Noise
0.6
0.55
0.5
1000
100
10
0.45
0.4
0.35
0.3
Specified Supply-Voltage Range
0.25
1
0
4
8
12
16
20
24
28
32
36
1
10
100
1k
10k
100k
1M
Supply Voltage (V)
Frequency (Hz)
Figure 9. Input Voltage Noise Spectral Density vs
Frequency
Figure 10. Quiescent Current vs Supply Voltage
180
135
90
180
25
20
15
10
5
Gain
135
90
45
0
Phase
0
45
-5
-10
-15
-20
G = 10
G = 1
0
G = -1
-45
-45
1
10
100
1k
10k
100k
1M
10M
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 11. Open-Loop Gain and Phase vs Frequency
Figure 12. Closed-Loop Gain vs Frequency
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Typical Characteristics (continued)
3
1M
100k
10k
1k
5 Typical Units Shown
VS = 2.7 V
VS = 4 V
2.5
2
VS = 36 V
1.5
1
100
10
0.5
0
1
1m
-40 -25
0
25
50
75
100
125
1
10
100
1k
10k
100k
1M
10M
Temperature (°C)
Frequency (Hz)
Figure 13. Open-Loop Gain vs Temperature
Figure 14. Open-Loop Output Impedance vs Frequency
50
45
40
35
30
25
20
15
10
5
50
ROUT = 0 Ω
45
ROUT = 25 Ω
40
ROUT = 50 Ω
35
30
25
20
G = 1
18
V
RF = 10 kΩ
18 V
RI = 10 kΩ
G = -1
ROUT = 0 Ω
ROUT = 25 Ω
ROUT = 50 Ω
15
10
5
ROUT
TLV171-Q1
ROUT
RL
CL
-18
V
TLV171-Q1
-18 V
CL
0
0
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
RL = 10 kΩ
Figure 15. Noninverting Small-Signal Overshoot vs
Capacitive Load
Figure 16. Inverting Small-Signal Overshoot vs Capacitive
Load
(100-mV Output Step)
(100-mV Output Step)
18 V
G = 1
18 V
TLV171-Q1
TLV171-Q1
Output
-18 V
RL
CL
-18 V
37 VPP
Sine Wave
18ꢀ5 V)
(
Output
Time (100ms/div)
Time (1ms/div)
RL = 10 kΩ
CL = 100 pF
Figure 17. No Phase Reversal
Figure 18. Small-Signal Step Response (100 mV)
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Typical Characteristics (continued)
RI = 2 kΩ RF = 2 kΩ
18 V
TLV171-Q1
CL
-18 V
G = -1
Time (20 ms/div)
Time (5ms/div)
CL = 100 pF
G = 1
RL = 10 kΩ
CL = 100 pF
Figure 19. Small-Signal Step Response (100 mV)
Figure 20. Large-Signal Step Response
10
8
6
4
12-Bit Settling
2
0
-2
-4
-6
-8
-10
( 1ꢀ2ꢁSB ꢂ 0.024%)
0
4
8
12
16
20
24
28
32
36
Time (4ms/div)
Time (ms)
G = –1
RL = 10 kΩ
CL = 100 pF
G = –1
Figure 22. Large-Signal Settling Time (10-V Positive Step)
Figure 21. Large-Signal Step Response
10
8
50
45
40
6
4
35
30
25
20
15
10
5
ISC, Sink
12-Bit Settling
2
0
-2
-4
-6
-8
ISC, Source
( 1ꢀ2ꢁSB ꢂ 0.024%)
-10
0
0
4
8
12
16
20
24
28
32
36
-40
-25
0
25
50
75
100
125
Time (ms)
Temperature (°C)
G = –1
Figure 23. Large-Signal Settling Time (10-V Negative Step)
Figure 24. Short-Circuit Current vs Temperature
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Typical Characteristics (continued)
15
VS
=
15 V
12.5
10
Maximum output voltage without
slew-rate induced distortion.
7.5
VS
= 5 V
5
2.5
0
10k
100k
Frequency (Hz)
1M
10M
Figure 25. Maximum Output Voltage vs Frequency
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7 Detailed Description
7.1 Overview
The TLVx171-Q1 family of operational amplifiers provides high overall performance, making them ideal for many
general-purpose applications. The excellent offset drift of only 1 µV/°C (typical) provides excellent stability over
the entire temperature range. In addition, the device offers very good overall performance with high CMRR,
PSRR, AOL, and superior THD.
7.2 Functional Block Diagram
TLVx171-Q1
+
PCH
FF Stage
œ
Ca
Cb
+
+IN
+
+
PCH
Input Stage
2nd Stage
OUT
Output
Stage
œ
œIN
œ
œ
+
NCH
Input Stage
œ
Copyright © 2017, Texas Instruments Incorporated
7.3 Feature Description
7.3.1 Operating Characteristics
The TLVx171-Q1 family of devices is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are shown in Typical Characteristics.
7.3.2 Phase-Reversal Protection
The TLVx171-Q1 family of devices has an internal phase-reversal protection. Many op amps exhibit a phase
reversal when the input is driven beyond the linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input of the TLVx171-Q1 family of devices prevents
phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail.
Figure 26 shows this performance.
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Feature Description (continued)
18 V
TLV171-Q1
Output
-18 V
37 VPP
Sine Wave
18ꢀ5 V)
(
Output
Time (100ms/div)
Figure 26. No Phase Reversal
7.3.3 Capacitive Load and Stability
The dynamic characteristics of the TLVx171-Q1 family of devices are optimized for commonly encountered
operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase
margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be
isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT
equal to 50 Ω) in series with the output. Figure 27 and Figure 28 shows small-signal overshoot versus capacitive
load for several values of ROUT. For details of analysis techniques and application circuits, see Applications
Bulletin AB-028, available for download from TI.com.
50
45
40
35
30
25
20
15
10
5
50
45
40
35
30
25
20
15
10
5
ROUT = 0 Ω
ROUT = 25 Ω
ROUT = 50 Ω
G = 1
18
V
RF = 10 kΩ
18 V
RI = 10 kΩ
G = -1
ROUT = 0 Ω
ROUT = 25 Ω
ROUT = 50 Ω
ROUT
TLV171-Q1
ROUT
RL
CL
-18
V
TLV171-Q1
-18 V
CL
0
0
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
RL = 10 kΩ
Figure 27. Small-Signal Overshoot versus Capacitive Load
(100-mV Output Step)
Figure 28. Small-Signal Overshoot versus Capacitive Load
(100-mV Output Step)
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7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the TLVx171-Q1 family of devices extends 100 mV below the negative
rail and within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is listed in Table 3.
Table 3. Typical Performance Range
PARAMETER
Input common-mode voltage
Offset voltage
MIN
TYP
MAX
UNIT
V
(V+) – 2
(V+) + 0.1
7
mV
Offset voltage vs temperature
Common-mode rejection
Open-loop gain
12
65
60
0.7
0.7
30
µV/°C
dB
dB
GBW
MHz
V/µs
nV/√Hz
Slew rate
Noise at f = 1kHz
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TLV171-Q1 operational amplifier family provides high overall performance, making the device ideal for many
general-purpose applications. The excellent offset drift of only 1 µV/°C provides excellent stability over the entire
temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and
AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling
capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
8.1.1 Electrical Overstress
Designers often ask questions about the capability of an op amp to withstand electrical overstress. These
questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin.
Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA as stated in Absolute Maximum Ratings. Figure 29 shows how a series input resistor can be added to the
input to limit the input current. The added resistor contributes thermal noise at the amplifier input and its value
must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10 mA max
VOUT
TLV171-Q1
VIN
5 kΩ
Copyright © 2017, Texas Instruments Incorporated
Figure 29. Input Current Protection
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-
current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent it from being damaged. The energy
absorbed by the protection circuitry is then dissipated as heat.
When the operational amplifier connects into a circuit, the ESD protection components are intended to remain
inactive and not become involved in the application circuit operation. However, circumstances may arise where
an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that
some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow
occurs through ESD cells and rarely involves the absorption device.
If the ability of the supply to absorb this current is uncertain, external zener diodes may be added to the supply
pins. The zener voltage must be selected such that the diode does not turn on during normal operation.
However, the zener voltage must be low enough so that the zener diode conducts if the supply pin begins to rise
above the safe operating supply voltage level.
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8.2 Typical Application
8.2.1 Capacitive Load Drive Solution Using an Isolation Resistor
The TLVx171-Q1 device can be used capacitive loads such as cable shields, reference buffers, MOSFET gates,
and diodes. The circuit uses an isolation resistor (RISO) to stabilize the output of an op amp. RISO modifies the
open loop gain of the system to ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
CLOAD
+
VIN
-VS
œ
Figure 30. Unity-Gain Buffer with RISO Stability Compensation
8.2.1.1 Design Requirements
The design requirements are:
•
•
•
Supply voltage: 30 V (±15 V)
Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF
Phase margin: 45° and 60°
8.2.1.2 Detailed Design Procedure
Figure 31 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 31. Not shown in Figure 31 is the open-loop output resistance of the op amp, Ro.
1 + CLOAD × RISO × s
T(s) =
1 + R + R
× C
× s
o
ISO
LOAD
(1)
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro +
RISO) and CLOAD. Components RISO and CLOAD determine the frequency of the zero (fz). A stable system is
obtained by selecting RISO such that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20
dB/decade. Figure 31 shows the concept. The 1/β curve for a unity-gain buffer is 0 dB.
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Typical Application (continued)
120
100
80
60
40
20
0
AOL
1
fp
=
2 ì Œ ì
R
+ Ro ì C
ISO LOAD
(
)
40 dB
1
fz
=
2 ì Œ ì RISO ì CLOAD
1 dec
1/ꢀ
20 dB
dec
ROC =
100M
10M
10
100
1k
10k
100k
1M
Frequency (Hz)
Figure 31. Unity-Gain Amplifier with RISO Compensation
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and AC gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 4
lists the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For more
details on this design and other alternative devices that can be used in place of the TLVx171-Q1, see Capacitive
Load Drive Solution using an Isolation Resistor.
Table 4. Phase Margin versus Overshoot and AC Gain Peaking
PHASE MARGIN
OVERSHOOT
23.3%
AC GAIN PEAKING
2.35 dB
45°
60°
8.8%
0.28 dB
8.2.1.3 Application Curve
The TLVx171-Q1 series meets the supply voltage requirements of 30 V. The TLVx171-Q1 device was tested for
various capacitive loads and RISO was adjusted to achieve an overshoot corresponding to Table 4. Figure 32
shows the test results.
10000
45è Phase Margin
60è Phase Margin
1000
100
10
1
0.01
0.1
1
10
100
1000
Capacitive Load (nF)
D001
Figure 32. RISO vs CLOAD
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9 Power Supply Recommendations
The TLV171-Q1 family of devices is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For detailed information on bypass capacitor placement, see Layout.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. See Circuit Board
Layout Techniques for detailed information.
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace
perpendicular as opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in Figure 33, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
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10.2 Layout Example
Place components close
to device and to each
other to reduce parasitic
errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
N/C
N/C
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
œIN
+IN
Vœ
V+
OUTPUT
N/C
VIN
GND
GND
VSœ
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Copyright © 2017, Texas Instruments Incorporated
Figure 33. Operational Amplifier Board Layout for Noninverting Configuration
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
•
•
•
Applications Bulletin AB-028 (SBOA015)
Capacitive Load Drive Solution using an Isolation Resistor (TIDU032)
Circuit Board Layout Techniques (SLOA089)
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
TLV171-Q1
TLV2171-Q1
TLV4171-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
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11.3 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLV171QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1CJT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV171-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Catalog: TLV171
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV171QDBVRQ1
SOT-23
DBV
5
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
213.0 191.0 35.0
TLV171QDBVRQ1
5
3000
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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