TLV2352MUB [TI]
LinCMOSE DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS; LinCMOSE双通道低电压差分比较仪
| 型号： | TLV2352MUB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LinCMOSE DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS |
| 文件： | 总21页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
12
Wide Range of Supply Voltages
High Input Impedance . . . 10 Ω Typ
2 V to 8 V
Extremely Low Input Bias Current
5 pA Typ
Fully Characterized at 3 V and 5 V
Very-Low Supply-Current Drain
Common-Mode Input Voltage Range
Includes Ground
120 µA Typ at 3 V
Output Compatible With TTL, MOS, and
CMOS
Built-In ESD Protection
Fast Response Time . . . 200 ns Typ for
TTL-Level Input Step
symbol (each comparator)
description
The TLV2352 consists of two independent,
low-power comparators specifically designed for
single power-supply applications and operates
with power-supply rails as low as 2 V. When
powered from a 3-V supply, the typical supply
current is only 120 µA.
IN+
OUT
IN–
The TLV2352 is designed using the Texas Instruments LinCMOS technology and therefore features an
12
extremely high input impedance (typically greater than 10 Ω), which allows direct interfacing with
high-impedance sources. The outputs are N-channel open-drain configurations that require an external pullup
resistor to provide a positive output voltage swing, and they can be connected to achieve positive-logic
wired-AND relationships. The TLV2352I is fully characterized at 3 V and 5 V for operation from – 40°C to 85°C.
The TLV2352M is fully characterized at 3 V and 5 V for operation from – 55°C to 125°C.
The TLV2352 has internal electrostatic-discharge (ESD)-protection circuits and has been classified with a
1000-V ESD rating using Human Body Model testing. However, care should be exercised in handling this device
as exposure to ESD may result in degradation of the device parametric performance.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
V
max
CHIP
CARRIER
(FK)
CERAMIC
DIP
PLASTIC
DIP
PLASTIC
DIP
IO
SMALL
T
A
FORM
(Y)
TSSOP
(PW)
at 25°C
OUTLINE
‡
†
(JG)
(P)
(U)
(D)
–40°C to
85°C
5 mV
5 mV
TLV2352ID
—
—
—
TLV2352IP TLV2352IPWLE
—
TLV2352Y
–55°C to
125°C
TLV2352MFK
TLV2352MJG
—
—
TLV2352MU
†
‡
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLV2352IDR).
The PW packages are only available left-ended taped and reeled (e.g., TLV2352IPWLE)
These devices have limited built-in protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
TLV2352I . . . D OR P PACKAGE
TLV2352M . . . JG PACKAGE
(TOP VIEW)
TLV2254M
U PACKAGE
(TOP VIEW)
TLV2352I . . . PW PACKAGE
(TOP VIEW)
1OUT
1IN–
1IN+
/GND
V
DD+
1
2
3
4
8
7
6
5
1
1OUT
1IN–
1IN+
/GND
V
DD+
1
2
3
4
8
7
6
5
NC •
NC
V
2OUT
2IN–
2IN+
10
9
2OUT
2IN–
2IN+
2
3
4
5
2OUT
2IN–
2IN+
1OUT
1IN–
1IN+
/GND
DD+
8
V
DD–
V
DD–
7
V
6
DD–
NC – No internal connection
TLV2352M
FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
NC
NC
1IN–
NC
4
5
6
7
8
2OUT
17
16
15
14
NC
2IN–
NC
1IN+
NC
9 10 11 12 13
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
•
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
TLV2352Y chip information
These chips, when properly assembled, display characteristics similar to the TLV2352. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. This chip can be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
V
(7)
(8)
(5)
(4)
(3)
(6)
DD
(8)
(3)
(2)
IN+
IN–
+
–
(1)
OUT
(5)
(6)
+
IN+
IN–
(7)
OUT
–
57
(4)
GND
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
T max = 150°C
J
(1)
(2)
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
57
PIN (4) INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
DD
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±8 V
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 to 8 V
ID
I
Output voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
O
Input current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA
I
Output current, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
O
Duration of output short-circuit current to GND (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T : TLV2352I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
TLV2352M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, and PW Packages . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: FK, JG, and U Packages . . . . . . . . 300°C
†
Stress beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN–.
3. Short circuits from outputs to V
can cause excessive heating and eventual device destruction.
DD
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING
FACTOR
T
= 85°C
T = 125°C
A
POWER RATING
A
A
PACKAGE
POWER RATING
POWER RATING
D
FK
JG
P
PW
U
725 mW
1375 mW
1050 mW
1000 mW
525 mW
700 mW
5.8 mW/°C
11.0 mW/°C
8.4 mW/°C
8.0 mW/°C
4.2 mW/°C
5.5 mW/°C
377 mW
715 mW
546 mW
520 mW
273 mW
370 mW
—
275 mW
210 mW
—
—
150 mW
recommended operating conditions
MIN
MAX
8
UNIT
Supply voltage, V
DD
2
0
V
V
V
= 3 V
= 5 V
1.75
3.75
85
DD
Common-mode input voltage, V
V
IC
0
DD
TLV2352I
–40
–55
Operating free-air temperature, T
°C
A
TLV2352M
125
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
†
electrical characteristics at specified free-air temperature
TLV2352I
‡
PARAMETER
TEST CONDITIONS
V
= 3 V
DD
TYP
V
= 5 V
DD
TYP
UNIT
T
A
MIN
MAX MIN
MAX
25°C
Full range
25°C
1
1
5
5
7
1
1
5
5
7
V
Input offset voltage
Input offset current
Input bias current
V
IC
= V
min, See Note 4
ICR
mV
IO
pA
nA
pA
nA
I
IO
85°C
1
1
2
25°C
I
IB
85°C
2
25°C
0 to 2
0 to 4
Common-mode input
voltage range
V
ICR
V
0 to
1.75
0 to
3.75
Full range
25°C
Full range
25°C
0.1
0.1
nA
High-level output
current
I
V
ID
= 1 V
OH
1
300
600
1
400
700
µA
115
150
Low-level output
voltage
V
V
ID
V
ID
V
ID
= –1 V,
= –1 V,
= 1 V,
I
= 2 mA
mV
mA
µA
OL
OL
Full range
Low-level output
current
I
I
V
= 1.5 V
25°C
6
16
6
16
OL
OL
25°C
120
250
350
140
300
400
Supply current
No load
DD
Full range
†
‡
All characteristics are measured with zero common-mode input voltages unless otherwise noted.
Full range is –40°C to 85°C. IMPORTANT: See Parameter Measurement Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with V
= 5 V, 2 V with V
DD
= 3 V, or
DD
below 400 mV with a 10-kΩ resistor between the output and V . They can be verified by applying the limit value to the input and
DD
checking for the appropriate output state.
switching characteristics, V
= 3 V, T = 25°C
DD
A
TLV2352I
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
§
Response time
R
= 5.1 kΩ,
C
= 15 pF , See Note 5 100-mV input step with 5-mV overdrive
L
640
ns
L
§
C
includes probe and jig capacitance.
L
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses V = 1 V with
O
V
DD
= 3 V or V = 1.4 V with V
= 5 V.
O
DD
switching characteristics, V
= 5 V, T = 25°C
DD
A
TLV2352I
TYP
PARAMETER
TEST CONDITIONS
UNIT
MIN
MAX
100-mV input step with 5-mV overdrive
TTL-level input step
650
§
= 15 pF ,
Response time
R
= 5.1 kΩ,
See Note 5
ns
C
L
L
200
§
C
includes probe and jig capacitance.
L
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses V = 1 V with
O
V
DD
= 3 V or V = 1.4 V with V = 5 V.
DD
O
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
†
electrical characteristics at specified free-air temperature
TLV2352M
‡
PARAMETER
TEST CONDITIONS
V
= 3 V
V
= 5 V
UNIT
T
A
DD
TYP
DD
TYP
MIN
MAX MIN
MAX
5
25°C
Full range
25°C
1
1
5
5
1
1
5
V
IO
Input offset voltage
Input offset current
Input bias current
V
IC
= V
min, See Note 4
ICR
mV
10
10
pA
nA
pA
nA
I
IO
125°C
25°C
10
10
20
I
IB
125°C
25°C
20
0 to 2
0 to 4
Common-mode input
voltage range
V
ICR
V
0 to
1.75
0 to
3.75
Full range
25°C
Full range
25°C
0.1
0.1
nA
High-level output
current
I
V
ID
= 1 V
OH
1
300
600
1
400
700
µA
115
150
Low-level output
voltage
V
V
ID
V
ID
V
ID
= –1 V,
= –1 V,
= 1 V,
I
= 2 mA
mV
mA
µA
OL
OL
Full range
Low-level output
current
I
I
V
= 1.5 V
25°C
6
16
6
16
OL
OL
25°C
120
250
350
140
300
400
Supply current
No load
DD
Full range
†
‡
All characteristics are measured with zero common-mode input voltages unless otherwise noted.
Full range is –55°C to 125°C. IMPORTANT: See Parameter Measurement Information.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with V
= 5 V, 2 V with V
DD
= 3 V, or
DD
below 400 mV with a 10-kΩ resistor between the output and V . They can be verified by applying the limit value to the input and
DD
checking for the appropriate output state.
switching characteristics, V
= 3 V, T = 25°C
DD
A
TLV2352M
MIN TYP
PARAMETER
TEST CONDITIONS
UNIT
MAX
§
Response time
R
= 5.1 kΩ,
C
= 100 pF , See Note 5 100-mV input step with 5-mV overdrive
L
1400
ns
L
§
C
includes probe and jig capacitance.
L
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses V = 1 V with
O
V
DD
= 3 V or V = 1.4 V with V
= 5 V.
O
DD
switching characteristics, V
= 5 V, T = 25°C
DD
A
TLV2352M
MIN TYP
PARAMETER
TEST CONDITIONS
UNIT
MAX
1300
900
100-mV input step with 5-mV overdrive
TTL-level input step
§
See Note 5
= 100 pF ,
Response time
R
= 5.1 kΩ,
ns
C
L
L
§
C
includes probe and jig capacitance.
L
NOTE 5: The response time specified is the interval between the input step function and the instant when the output crosses V = 1 V with
O
V
DD
= 3 V or V = 1.4 V with V = 5 V.
DD
O
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
†
electrical characteristics at specified free-air temperature, T = 25°C
A
TLV2352Y
PARAMETER
TEST CONDITIONS
V
= 3 V
DD
TYP
V
= 5 V
DD
TYP
UNIT
MIN
MAX MIN
MAX
V
Input offset voltage
V
= V min, See Note 4
ICR
1
1
5
5
1
1
5
5
mV
pA
pA
V
IO
IC
I
IO
I
IB
Input offset current
Input bias current
V
ICR
Common-mode input voltage range
High-level output current
Low-level output voltage
Low-level output current
Supply current
0 to 2
0 to 4
I
V
ID
V
ID
V
ID
V
ID
= 1 V
0.1
115
16
0.1
150
16
nA
mV
mA
µA
OH
V
OL
= –1 V,
= –1 V,
= 1 V
I
= 2 mA
300
6
400
300
OL
I
I
V
= 1.5 V
6
OL
OL
No load
120
250
140
DD
†
All characteristics are measured with zero common-mode input voltages unless otherwise noted.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output above 4 V with V
= 5 V, 2 V with V
DD
= 3 V, or
DD
below 400 mV with a 10-kΩ resistor between the output and V . They can be verified by applying the limit value to the input and
DD
checking for the appropriate output state.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
SUPPLY CURRENT
vs
vs
LOW-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
1100
990
880
770
660
550
440
330
190
180
170
160
150
140
130
V
T
= 3 V
= 25°C
No Load
DD
A
V
= 5 V
DD
V
DD
= 3 V
120
110
100
90
220
110
0
0
2
4
6
8
10
12
14
16
–75 – 50 – 25
0
25
50
75
100 125
I
– Low-Level Output Current – mA
T
A
– Free-Air Temperature – °C
OL
Figure 1
Figure 2
COMMON-MODE INPUT VOLTAGE RANGE
OUTPUT FALL TIME
vs
vs
FREE-AIR TEMPERATURE
CAPACITIVE LOAD
3
2.5
2
50
45
40
35
30
25
20
15
V
= 3 V
V
DD
= 3 V
DD
Overdrive = 10 mV
Positive Limit
R
T
A
= 5.1 kΩ (pullup to V
= 25°C
)
DD
L
1.5
1
0.5
0
Negative Limit
10
5
–0.5
–1
–75 –50 –25
0
0
10 20 30 40 50 60 70 80 90 100
– Capacitive Load – pF
0
25
50
75
100 125
C
T
– Free-Air Temperature – °C
L
A
Figure 3
Figure 4
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
TYPICAL CHARACTERISTICS
HIGH-TO-LOW-LEVEL OUTPUT
PROPAGATION DELAY
HIGH-TO-LOW-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS OVERDRIVE VOLTAGES
FOR VARIOUS CAPACITIVE LOADS
V
= 3 V
V
= 3 V
= 15 pF
= 5.1 kΩ (pullup to V
= 25°C
DD
DD
L
L
Overdrive = 10 mV
C
R
T
R
T
= 5.1 kΩ (pullup to V
= 25°C
)
DD
)
L
DD
A
A
3
0
3
0
C
= 100 pF
L
20 mV
5 mV
C = 15 pF
L
10 mV
C
= 50 pF
L
100
0
100
0
0
100 200 300 400 500 600 700 800 900 1000
– High-to-Low-Level Output
0
100 200 300 400 500 600 700 800 900 1000
– High-to-Low-Level Output
t
t
PHL
PHL
Propagation Delay Time – ns
Propagation Delay Time – ns
Figure 5
Figure 6
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS OVERDRIVE VOLTAGES
FOR VARIOUS CAPACITIVE LOADS
V
C
R
= 3 V
= 15 pF
= 5.1 kΩ (pullup to V
= 25°C
V
= 3 V
DD
L
L
DD
Overdrive = 10 mV
)
R
T
A
= 5.1 kΩ (pullup to V
= 25°C
)
DD
DD
L
T
A
C = 50 pF
L
3
0
3
20 mV
C
= 15 pF
L
5 mV
0
10 mV
C
= 100 pF
L
100
0
100
0
0
100 200 300 400 500 600 700 800 900 1000
– Low-to-High-Level Output
0
100 200 300 400 500 600 700 800 900 1000
– Low-to-High-Level Output
t
t
PLH
PLH
Propagation Delay Time – ns
Propagation Delay Time – ns
Figure 7
Figure 8
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
The digital output stage of the TLV2352 can be damaged if it is held in the linear region of the transfer curve.
Conventional operational amplifier/comparator testing incorporates the use of a servo loop that is designed to force
the device output to a level within this linear region. Since the servo-loop method of testing cannot be used, the
following alternatives for measuring parameters such as input offset voltage, common-mode rejection, etc., are
offered.
To verify that the input offset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 9(a). With the noninverting input positive with respect to the inverting input, the output should be high. With
the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages can
be slewed as shown in Figure 9(b) for the V
accuracy.
test, rather than changing the input voltages to provide greater
ICR
5 V
1 V
5.1 kΩ
5.1 kΩ
+
–
+
–
Applied V
Limit
Applied V
Limit
IO
IO
V
O
V
O
– 4 V
(a) V WITH V = 0
IO IC
(b) V WITH V = 4 V
IO IC
Figure 9. Method for Verifying That Input Offset Voltage Is Within Specified Limits
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal but
opposite in polarity to the input offset voltage, the output changes states.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
Figure 10 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator in the linear region. The circuit consists of a switching-mode servo loop in which U1a generates a
triangular waveform of approximately 20-mV amplitude. U1b acts as a buffer with C2 and R4 removing any residual
dc offset. The signal is then applied to the inverting input of the comparator under test while the noninverting input
is driven by the output of the integrator formed by U1c through the voltage divider formed by R9 and R10. The loop
reaches a stable operating point when the output of the comparator under test has a duty cycle of exactly 50%, which
can only occur when the incoming triangle wave is sliced symmetrically or when the voltage at the noninverting input
exactly equals the input offset voltage.
Voltage dividers R9 and R10 provide a step up of the input offset voltage by a factor of 100 to make measurement
easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the reading; therefore, it is
suggested that their tolerance level be 1% or lower.
Measuring the extremely low values of input current requires isolation from all other sources of leakage current and
compensation for the leakage of the test socket and board. With a good picoammeter, the socket and board leakage
can be measured with no device in the socket. Subsequently, this open-socket leakage value can be subtracted from
the measurement obtained with a device in the socket to obtain the actual input current of the device.
V
DD
C3
0.68 µF
R5
1.8 kΩ, 1%
U1b 1/4
TLC2344
Buffer
C2
1 µF
U1c 1/4
+
TLC2344
R6
5.1 kΩ
–
+
–
DUT
–
+
R7
1 MΩ
R4
47 kΩ
V
IO
(×100)
Integrator
R1
240 kΩ
R8
1.8 kΩ, 1%
U1a 1/4
TLC2344
C4
0.1 µF
–
C1
0.1 µF
+
Triangle
Generator
R9
10 kΩ, 1%
R10
100 Ω, 1%
R2
10 kΩ
R3
100 Ω
Figure 10. Circuit for Input Offset Voltage Measurement
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
Propagationdelaytimeisdefinedastheintervalbetweentheapplicationofaninputstepfunctionandtheinstantwhen
the output crosses V = 1 V with V
= 3 V or when the output crosses V = 1.4 V with V
= 5 V. Propagation delay
O
DD
O
DD
time, low-to-high-level output, is measured from the leading edge of the input pulse while propagation delay time,
high-to-low-level output, is measured from the trailing edge of the input pulse. Propagation-delay-time measurement
at low input signal levels can be greatly affected by the input offset voltage. The offset voltage should be balanced
by the adjustment at the inverting input (as shown in Figure 11) so that the circuit is just at the transition point. Then
a low signal, for example 105-mV or 5-mV overdrive, causes the output to change states.
V
DD
Pulse
1 µF
Generator
5.1 kΩ
50 Ω
+
–
DUT
1 V
Input Offset Voltage
Compensation
Adjustment
10 Ω
10 Turn
C
L
1 kΩ
(see Note A)
0.1 µF
– 1 V
TEST CIRCUIT
Overdrive
Overdrive
Input
100 mV
Input
100 mV
90%
90%
Low-to-High
Level Output
High-to-Low
Level Output
V
= 1 V With V
or
= 1.4 V With V
= 3 V
DD
O
V
O
= 5 V
DD
10%
10%
t
t
r
f
t
t
PHL
PLH
VOLTAGE WAVEFORMS
NOTE A: C includes probe and jig capacitance.
L
Figure 11. Propagation Delay, Rise, and Fall Times Test Circuit and Voltage Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
A MAX
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Four center pins are connected to die mount pad.
E. Falls within JEDEC MS-012
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.740
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
MECHANICAL INFORMATION
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE PACKAGE
0.400 (10,20)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.130 (3,30) MIN
0°–15°
0.063 (1,60)
0.015 (0,38)
0.023 (0,58)
0.015 (0,38)
0.015 (0,38)
0.008 (0,20)
0.100 (2,54)
4040107/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only
E. Falls within MIL-STD-1835 GDIP1-T8
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
MECHANICAL INFORMATION
PLASTIC DUAL-IN-LINE PACKAGE
P (R-PDIP-T8)
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
Seating Plane
0.125 (3,18) MIN
0.100 (2,54)
0°–15°
0.021 (0,53)
0.015 (0,38)
0.010 (0,25)
M
0.010 (0,25) NOM
4040082/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
MECHANICAL INFORMATION
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,32
0,19
0,65
M
0,13
14
8
0,15 NOM
4,50
4,30
6,70
6,10
Gage Plane
0,25
1
7
0°–8°
0,75
0,50
A
Seating Plane
0,10
1,20 MAX
0,10 MIN
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4040064/D 10/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2352, TLV2352Y
LinCMOS DUAL LOW-VOLTAGE DIFFERENTIAL COMPARATORS
SLCS011B – MAY 1992 – REVISED MARCH 1999
MECHANICAL INFORMATION
CERAMIC DUAL FLATPACK
U (S-GDFP-F10)
0.250 (6,35)
0.246 (6,10)
0.006 (0,15)
0.004 (0,10)
0.080 (2,03)
0.050 (1,27)
0.045 (1,14)
0.026 (0,66)
0.300 (7,62)
0.350 (8,89)
0.350 (8,89)
0.250 (6,35)
0.250 (6,35)
0.019 (0,48)
1
10
0.015 (0,38)
0.050 (1,27)
0.250 (6,35)
5
6
0.025 (0,64)
0.005 (0,13)
1.000 (25,40)
0.750 (19,05)
4040179/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only.
E. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
22-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CFP
Drawing
5962-9688101Q2A
5962-9688101QHA
5962-9688101QPA
TLV2352ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
U
20
10
8
1
1
None
None
None
POST-PLATE Level-NC-NC-NC
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
CDIP
SOIC
JG
D
1
8
75
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
TLV2352IDR
TLV2352IP
ACTIVE
ACTIVE
ACTIVE
SOIC
PDIP
D
P
8
8
2500
50
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-NC-NC-NC
TLV2352IPW
TLV2352IPWLE
TLV2352IPWR
TLV2352MFKB
TLV2352MJG
TLV2352MJGB
TLV2352MUB
TSSOP
PW
PW
PW
FK
JG
JG
U
8
8
150
None
None
None
None
None
None
None
CU NIPDAU Level-1-220C-UNLIM
OBSOLETE TSSOP
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
LCCC
CDIP
CDIP
CFP
8
2000
CU NIPDAU Level-1-220C-UNLIM
POST-PLATE Level-NC-NC-NC
20
8
1
1
1
1
A42 SNPB
A42 SNPB
A42 SNPB
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
8
10
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号：
TLV2354IPWG4
QUAD COMPARATOR, 7000uV OFFSET-MAX, 640ns RESPONSE TIME, PDSO14, GREEN, PLASTIC, TSSOP-14
TI
©2020 ICPDF网 联系我们和版权申明