TLV237X [TI]
FAMILY OF 500-UA/CH 3-MHZ RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS; 家庭500 - UA / CH 3 MHz轨到轨输出运算放大器型号: | TLV237X |
厂家: | TEXAS INSTRUMENTS |
描述: | FAMILY OF 500-UA/CH 3-MHZ RAIL-TO-RAIL OUTPUT OPERATIONAL AMPLIFIERS |
文件: | 总22页 (文件大小:515K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SGLS275 − OCTOBER 2004
D
Qualification in Accordance With
AEC-Q100
D
D
D
D
Input Bias Current . . . 1 pA
†
Specified Temperature Range
−40°C to 125°C . . . Automotive Grade
Ultrasmall Packaging
D
Qualified for Automotive Applications
D
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
− 5-Pin SOT-23 (TLV271)
Ideal Upgrade for TLC27x Family
D
D
D
D
D
D
Rail-To-Rail Output
Operational Amplifier
Wide Bandwidth . . . 3 MHz
High Slew Rate . . . 2 .4 V/µs
Supply Voltage Range . . . 2.7 V to 16 V
Supply Current . . . 550 µA/Channel
Input Noise Voltage . . . 39 nV/√Hz
+
−
†
Contact Texas Instruments for details. Q100 qualification data
available on request.
description
The TLV27x takes the minimum operating supply voltage down to 2.7 V over the extended automotive
temperature range while adding the rail-to-rail output swing feature. This makes it an ideal alternative to the
TLC27x family for applications where rail-to-rail output swings are essential. The TLV27x also provides 3-MHz
bandwidth from only 550 µA.
Like the TLC27x, the TLV27x is fully specified for 5-V and 5-V supplies. The maximum recommended supply
voltage is 16 V, which allows the devices to be operated from a variety of rechargeable cells ( 8 V supplies down
to 1.35 V).
The CMOS inputs enable use in high-impedance sensor interfaces, with the lower voltage operation making
an attractive alternative for the TLC27x in battery-powered applications.
The 2.7-V operation makes it compatible with Li-Ion powered systems and the operating supply voltage range
of many micropower microcontrollers available today including Texas Instruments MSP430.
SELECTION OF SIGNAL AMPLIFIER PRODUCTS†
RAIL-
V
(µV)
Iq/Ch
GBW
SR
IO
DEVICE
TLV27x
V
(V)
I
IB
(pA)
SHUTDOWN
TO-
SINGLES/DUALS/QUADS
DD
(µA)
(MHz)
(V/µs)
RAIL
2.7−16
3−16
500
1100
500
300
150
250
300
550
675
550
1100
550
600
725
1
1
1
1
3
2.4
3.6
2.4
3.6
1.6
1.5
1.4
—
—
O
—
I/O
O
S/D/Q
S/D/Q
S/D/Q
D/Q
TLC27x
1.7
3
TLV237x
TLC227x
TLV246x
TLV247x
TLV244x
2.7−16
4−16
Yes
—
2.2
6.4
2.8
1.8
2.7−6
2.7−6
2.7−10
1300
Yes
Yes
—
I/O
I/O
O
S/D/Q
S/D/Q
D/Q
2
1
†
Typical values measured at 5 V, 25°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2001−2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS275 − OCTOBER 2004
FAMILY PACKAGE TABLE
PACKAGE TYPES
NUMBER OF
CHANNELS
UNIVERSAL
EVM BOARD
DEVICE
TLV271
†
SOT-23 TSSOP MSOP
SOIC
1
2
4
8
8
5
—
—
14
—
8
See the EVM
Selection Guide
(SLOU060)
TLV272
TLV274
—
—
14
—
†
Product Preview
TLV271 AVAILABLE OPTIONS
PACKAGED DEVICES
SOT-23
V
IO
MAX AT
25°C
T
A
SMALL OUTLINE
(D)
(DBV)
SYMBOL
−40°C to 125°C
5 mV
TLV271QDRQ1
TLV271QDBVRQ1
271Q
TLV272 AVAILABLE OPTIONS
PACKAGED DEVICES
MSOP
V
IO
MAX AT
25°C
T
A
SMALL OUTLINE
(D)
(DGK)
SYMBOL
†
−40°C to 125°C
5 mV
TLV272QDRQ1
TLV272QDGKRQ1
†
Product Preview
TLV274 AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
V
IO
MAX AT 25°C
SMALL OUTLINE
TSSOP
(PW)
(D)
−40°C to 125°C
5 mV
TLV274QDRQ1
TLV274QPWRQ1
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ ꢈ ꢀ ꢁꢂꢃ ꢄ ꢃ ꢆꢇ ꢅ ꢈ ꢀꢁꢂ ꢃꢄ ꢉꢆ ꢇꢅ
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SGLS275 − OCTOBER 2004
(1)
TLV27x PACKAGE PINOUTS
TLV271
TLV271
D PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
1
2
3
5
4
V
DD
OUT
GND
NC
IN−
NC
1
2
3
4
8
7
6
5
V
DD
IN+
OUT
NC
GND
IN−
IN+
TLV274
TLV272
D OR PW PACKAGE
D OR DGK PACKAGE
(TOP VIEW)
(TOP VIEW)
1OUT
1IN−
1IN+
GND
V
DD
1
2
3
4
8
7
6
5
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN−
1IN+
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
2OUT
2IN−
2IN+
V
DD
2IN+
2IN−
8
2OUT
NC − No internal connection
(1) SOT−23 may or may not be indicated
TYPICAL PIN 1 INDICATORS
Pin 1
Pin 1
Pin 1
Pin 1
Printed or
Molded Dot
Stripe
Bevel Edges
Molded ”U” Shape
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS275 − OCTOBER 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Differential input voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
ID
DD
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to V
Input current range, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA
Output current range, I
+ 0.2 V
I
DD
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
O
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
A
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
θ
θ
T
≤ 25°C
T = 25°C
A
POWER RATING
JC
JA
A
PACKAGE
(°C/W)
(°C/W)
POWER RATING
D (8)
38.3
176
710 mW
396 mW
D (14)
DBV (5)
DGK (8)
PW (14)
26.9
55
122.3
324.1
259.96
173.6
1022 mW
385 mW
481 mW
720 mW
531 mW
201 mW
250 mW
374 mW
54.23
29.3
recommended operating conditions
MIN
MAX
16
UNIT
Single supply
Split supply
2.7
1.35
0
Supply voltage, V
DD
V
8
Common-mode input voltage range, V
ICR
V
DD
−1.35
125
V
Operating free-air temperature, T
Q-suffix
−40
°C
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SGLS275 − OCTOBER 2004
electrical characteristics at specified free-air temperature, V
otherwise noted)
= 2.7 V, 5 V, and 15 V (unless
DD
dc performance
†
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
T
A
UNIT
25°C
Full range
25°C
0.5
5
7
V
Input offset voltage
Offset voltage drift
mV
V
R
= V /2,
= 10 kΩ,
V
R
= V /2,
= 50 Ω
IO
IC
L
DD
O DD
S
α
VIO
2
µV/°C
25°C
53
54
58
57
67
66
95
76
80
82
77
79
70
V
R
= 0 to V −1.35V,
DD
IC
S
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 2.7 V
= 5 V
= 50 Ω
Full range
25°C
80
85
V
R
= 0 to V −1.35V,
DD
= 50 Ω
IC
CMRR Common-mode rejection ratio
dB
Full range
25°C
S
V
R
= 0 to V −1.35V,
DD
= 50 Ω
IC
= 15 V
= 2.7 V
= 5 V
Full range
25°C
S
106
110
115
Full range
25°C
Large-signal differential voltage
amplification
V
= V /2,
DD
O(PP)
A
VD
dB
R = 10 kΩ
Full range
25°C
L
= 15 V
Full range
†
Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C.
input characteristics
PARAMETER
TEST CONDITIONS
T
MIN
TYP
MAX
60
UNIT
A
25°C
125°C
25°C
1
I
I
Input offset current
pA
IO
1000
60
V
V
= 15 V,
V = V /2,
IC DD
DD
= V /2, R = 50 Ω
1
O
DD
S
Input bias current
pA
IB
125°C
25°C
1000
r
Differential input resistance
1000
8
GΩ
i(d)
C
Common-mode input capacitance
f = 21 kHz
25°C
pF
IC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢋ
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SGLS275 − OCTOBER 2004
electrical characteristics at specified free-air temperature, V
otherwise noted)
= 2.7 V, 5 V, and 15 V (unless
DD
output characteristics
†
PARAMETER
TEST CONDITIONS
MIN
2.55
2.48
4.9
TYP
MAX
T
A
UNIT
25°C
Full range
25°C
2.58
V
V
V
V
V
V
V
V
V
V
V
V
= 2.7 V
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
4.93
V
V
V
V
= V /2, I
DD
= −1 mA
= −5 mA
= 1 mA
= 5 V
IC
IC
IC
IC
OH
OH
OL
OL
Full range
25°C
4.85
14.92 14.96
14.9
= 15 V
= 2.7 V
= 5 V
Full range
25°C
V
OH
High-level output voltage
V
1.88
1.42
4.58
4.44
14.7
14.6
2.1
4.68
14.8
0.1
Full range
25°C
= V /2, I
DD
Full range
25°C
= 15 V
= 2.7 V
= 5 V
Full range
25°C
0.15
0.22
0.1
Full range
25°C
0.05
0.05
0.5
= V /2, I
DD
Full range
25°C
0.15
0.08
0.1
= 15 V
= 2.7 V
= 5 V
Full range
25°C
V
OL
Low-level output voltage
V
0.7
Full range
25°C
1.15
0.4
0.28
0.19
= V /2, I
DD
= 5 mA
Full range
25°C
0.54
0.3
= 15 V
Full range
25°C
0.35
Positive rail
Negative rail
Positive rail
Negative rail
Positive rail
Negative rail
4
5
V
O
V
O
V
O
= 0.5 V from rail, V
= 0.5 V from rail, V
= 0.5 V from rail, V
= 2.7 V
= 5 V
DD
DD
DD
25°C
25°C
7
I
O
Output current
mA
25°C
8
25°C
13
12
= 15 V
25°C
†
‡
Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C.
Depending on package dissipation rating
6
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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ ꢈ ꢀ ꢁꢂꢃ ꢄ ꢃ ꢆꢇ ꢅ ꢈ ꢀꢁꢂ ꢃꢄ ꢉꢆ ꢇꢅ
ꢑ ꢋꢒ ꢓꢔ ꢕ ꢆꢌ ꢖꢗ ꢘꢋꢍ ꢁ ꢆꢀꢏ ꢆꢘꢋꢍ ꢁ ꢏ ꢙꢀ ꢚ ꢙꢀ
ꢏ ꢚꢛꢘ ꢋꢀ ꢍꢏ ꢜꢋꢁ ꢋꢌ ꢚ ꢁꢍ ꢊꢍ ꢛꢘ ꢝ
ꢊ
ꢋ
ꢌ
ꢍ
ꢁꢎ
ꢏ
ꢊ
ꢐ
ꢐ
ꢆµ
SGLS275 − OCTOBER 2004
electrical characteristics at specified free-air temperature, V
otherwise noted) (continued)
= 2.7 V, 5 V, and 15 V (unless
DD
power supply
†
PARAMETER
TEST CONDITIONS
T
A
MIN
TYP
470
MAX
560
UNIT
V
V
= 2.7 V
= 5 V
25°C
25°C
DD
550
750
660
DD
I
Supply current (per channel)
V
V
= V /2
DD
µA
DD
O
25°C
900
V
= 15 V
DD
IC
Full range
25°C
1200
70
80
Supply voltage rejection ratio
= 2.7 V to 15 V,
V
= V /2,
DD
DD
PSRR
dB
(∆V
DD
/∆V
IO
)
No load
Full range
65
†
Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C.
dynamic performance
†
PARAMETER
TEST CONDITIONS
MIN
TYP
2.4
3
MAX
UNIT
T
A
25°C
25°C
V
V
= 2.7 V
DD
R
= 2 kΩ, C = 10 pF
L
UGBW Unity gain bandwidth
MHz
L
= 5 V to 15 V
DD
25°C
1.4
1
2.1
V
V
V
= 2.7 V
V/µs
V/µs
V/µs
DD
DD
DD
Full range
25°C
1.4
1.2
1.9
1.4
2.4
2.1
V
C
= V /2,
DD
O(PP)
L
SR
Slew rate at unity gain
= 5 V
= 50 pF, R = 10 kΩ,
Full range
25°C
L
= 15 V
Full range
25°C
φ
m
Phase margin
Gain margin
65
18
°
R
R
= 2 kΩ
= 2 kΩ
C
C
= 10 pF
= 10 pF
L
L
L
25°C
dB
L
V
V
C
= 2.7 V,
DD
= 1 V, A = −1,
= 10 pF, R = 2 kΩ
0.1%
0.1%
2.9
2
(STEP)PP
V
L
L
t
s
Settling time
25°C
µs
V
V
C
= 5 V, 15 V,
= 1 V, A = −1,
= 47 pF, R = 2 kΩ
DD
(STEP)PP
V
L
L
†
Full range is −40°C to 125°C. If not specified, full range is −40°C to 125°C.
noise/distortion performance
PARAMETER
TEST CONDITIONS
MIN
TYP
0.02%
0.05%
0.18%
0.02%
0.09%
0.5%
39
MAX
UNIT
T
A
A
V
= 1
V
V
R
= 2.7 V,
DD
O(PP)
L
A
= 10
= 100
= 1
= V /2 V,
DD
25°C
25°C
V
= 2 kΩ, f = 10 kHz
A
V
THD + N Total harmonic distortion plus noise
A
V
V
V
R
= 5 V, 5 V,
= V /2 V,
DD
O(PP)
A
V
= 10
= 100
DD
= 2 kΩ, f = 10K
L
A
V
f = 1 kHz
f = 10 kHz
f = 1 kHz
nV/√Hz
fA/√Hz
V
I
Equivalent input noise voltage
Equivalent input noise current
25°C
25°C
n
35
0.6
n
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢅ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢃ
ꢆ
ꢇ
ꢅ
ꢈ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢉ
ꢆ
ꢇ
ꢅ
ꢊ
ꢋ
ꢌ
ꢍ
ꢁ
ꢎ
ꢏ
ꢊ
ꢐ
ꢏꢚ ꢛ ꢘꢋꢀ ꢍ ꢏꢜ ꢋ ꢁ ꢋꢌ ꢚꢁ ꢍ ꢊꢍ ꢛ ꢘꢝ
ꢐ
ꢑ
ꢆ µ
ꢋ
ꢒ
ꢓ
ꢔ
ꢕ
ꢆ
ꢌ
ꢖ
ꢗ
ꢘ
ꢋ
ꢍ
ꢁ
ꢆ
ꢀ
ꢏ
ꢆ
ꢘ
ꢋ
ꢍ
ꢁ
ꢏ
ꢙ
ꢀ
ꢚ
ꢙ
ꢀ
SGLS275 − OCTOBER 2004
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
1
CMRR
Common-mode rejection ratio
Input bias and offset current
Low-level output voltage
High-level output voltage
Peak-to-peak output voltage
Supply current
vs Frequency
vs Free-air temperature
vs Low-level output current
vs High-level output current
vs Frequency
2
V
V
V
3, 5, 7
4, 6, 8
9
OL
OH
O(PP)
I
vs Supply voltage
vs Frequency
10
DD
PSRR
Power supply rejection ratio
Differential voltage gain & phase
Gain-bandwidth product
11
A
VD
vs Frequency
12
vs Free-air temperature
vs Supply voltage
vs Free-air temperature
vs Capacitive load
vs Frequency
13
14
SR
Slew rate
15
φ
m
Phase margin
16
V
n
Equivalent input noise voltage
Voltage-follower large-signal pulse response
Voltage-follower small-signal pulse response
Inverting large-signal response
Inverting small-signal response
Crosstalk
17
18, 19
20
21, 22
23
vs Frequency
24
8
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ꢑ ꢋꢒ ꢓꢔ ꢕ ꢆꢌ ꢖꢗ ꢘꢋꢍ ꢁ ꢆꢀꢏ ꢆꢘꢋꢍ ꢁ ꢏ ꢙꢀ ꢚ ꢙꢀ
ꢊꢋ
ꢌ
ꢍ
ꢁꢎ
ꢏ
ꢊ
ꢐ
ꢐ
ꢆµ
ꢏ
ꢚꢛꢘ ꢋꢀ ꢍꢏ ꢜꢋꢁ ꢋꢌ ꢚ ꢁꢍ ꢊꢍ ꢛꢘ ꢝ
SGLS275 − OCTOBER 2004
TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO
LOW-LEVEL OUTPUT VOLTAGE
vs
INPUT BIAS AND OFFSET CURRENT
vs
vs
LOW-LEVEL OUTPUT CURRENT
FREE-AIR TEMPERATURE
FREQUENCY
2.80
2.40
2.00
1.60
1.20
0.80
0.40
0.00
300
250
200
150
100
50
120
V
= 2.7 V
DD
V
V
= 2.7 V, 5 V and 10 V
DD
= V /2
T
A
= 125 °C
100
80
IC
DD
V
= 5 V, 10 V
DD
60
V
= 2.7 V
DD
T
A
= 70 °C
40
20
0
T
A
= 25 °C
T
A
= 0 °C
0
T
A
= 40 °C
−50
0
2
4
6
8
10 12 14 16 18 20 22 24
10
100
1 k
10 k
100 k
1 M
−40−25−10 5 20 35 50 65 80 95 110 125
I
− Low-Level Output Current − mA
OL
f − Frequency − Hz
T
A
− Free-Air Temperature − °C
Figure 2
Figure 1
Figure 3
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
5.00
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
2.80
2.40
2.00
1.60
1.20
0.80
0.40
0.00
V
= 5 V
V
= 5 V
DD
CC
V
= 2.7 V
DD
4.50
4.00
3.50
3.00
T
= −40°C
A
T
= 125 °C
A
T
A
= 0°C
T
=−40°C
A
T
A
= 70 °C
T
= 125°C
= 70°C
A
2.50
2.00
T
= 25°C
T
A
A
T
= 25 °C
A
T
= 25°C
= 0°C
A
1.50
1.00
0.50
0.00
T
A
= 70°C
T
= 0 °C
A
T
A
T
A
= −40 °C
T
A
= 125°C
0
5
10 15 20 25 30 35 40 45
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
0
1
2
3
4
5
6
7
8
9
10 11 12
I
− Low-Level Output Current − mA
I
− High-Level Output Current − mA
I
− High-Level Output Current − mA
OL
OH
OH
Figure 5
Figure 4
Figure 6
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
FREQUENCY
11
10
8
10
8
V
= 10 V
DD
V
= 10 V
V
= 10 V
10
9
DD
DD
T
A
=125°C
A
V
= −10
T
=70°C
=25°C
R
C
T
= 2 kΩ
= 10 pF
= 25°C
8
A
L
L
A
T
A
= −40°C
7
T
A
6
6
6
THD = 5%
T
=0°C
A
5
T
= 0°C
A
4
4
V
= 5 V
DD
T
=−40°C
4
A
T
= 25°C
A
3
2
2
T
= 70°C
2
1
0
A
V
= 2.7 V
DD
T
A
= 125°C
0
0
10
100
1 k
10 k 100 k 1 M
10 M
20
40
60
80
100
120
0
0
20
40
60
80
100
120
f − Frequency − Hz
I
− Low-Level Output Current − mA
I
− High-Level Output Current − mA
OL
OH
Figure 8
Figure 7
Figure 9
9
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢅ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢃ ꢆꢇ ꢅ ꢈ ꢀꢁꢂ ꢃ ꢄꢉ ꢆꢇ ꢅ
ꢊ
ꢋ
ꢌ
ꢍ
ꢁ
ꢎ
ꢏ
ꢊ
ꢐ
ꢏꢚ ꢛ ꢘꢋꢀ ꢍ ꢏꢜ ꢋ ꢁ ꢋꢌ ꢚꢁ ꢍ ꢊꢍ ꢛ ꢘꢝ
ꢐ
ꢑ
ꢆ µ
ꢋ
ꢒ
ꢓ
ꢔ
ꢕ
ꢆ
ꢌ
ꢖ
ꢗ
ꢘ
ꢋ
ꢍ
ꢁ
ꢆ
ꢀ
ꢏ
ꢆ
ꢘ
ꢋ
ꢍ
ꢁ
ꢏ
ꢙ
ꢀ
ꢚ
ꢙ
ꢀ
SGLS275 − OCTOBER 2004
TYPICAL CHARACTERISTICS
POWER SUPPLY REJECTION RATIO
SUPPLY CURRENT
vs
vs
FREQUENCY
SUPPLY VOLTAGE
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
120
100
A
V
= 1
T
A
= 25°C
V
IC
= V / 2
DD
T
A
= 125°C
T
= 70°C
V
= 5 V, 10 V
A
DD
80
60
V
= 2.7 V
DD
T
A
= 25°C
40
T
A
= 0°C
T
A
= −40°C
20
0
10
100
1 k
10 k
100 k
1 M
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
f − Frequency − Hz
V
− Supply Voltage − V
DD
Figure 11
Figure 10
DIFFERENTIAL VOLTAGE GAIN AND PHASE
GAIN BANDWIDTH PRODUCT
vs
vs
FREQUENCY
FREE-AIR TEMPERATURE
180
135
90
120
100
80
4.0
3.5
V
= 10 V
Phase
DD
3.0
2.5
45
60
V
= 5 V
DD
0
40
2.0
1.5
1.0
Gain
V
= 2.7 V
DD
−45
−90
−135
−180
20
V
=5 V
0
DD
L
L
R =2 kΩ
C =10 pF
−20
0.5
0.0
T
=25°C
A
−40
10
−40 −25−10
5
20 35 50 65 80 95 110 125
100
1 k
10 k 100 k 1 M
10 M
T
A
− Free-Air Temperature − °C
f − Frequency − Hz
Figure 13
Figure 12
SLEW RATE
vs
FREE-AIR TEMPERATURE
SLEW RATE
vs
SUPPLY VOLTAGE
PHASE MARGIN
vs
CAPACITIVE LOAD
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
100
90
80
70
60
50
40
30
20
10
0
V
= 5 V
DD
R = 2 kΩ
SR−
3.0
2.5
2.0
L
T
= 25°C
= Open Loop
A
SR−
SR+
A
V
R
= 100
null
SR+
1.5
1.0
R
= 0
null
V
A
R
= 5 V
= 1
= 10 kΩ
= 50 pF
A
= 1
DD
V
L
L
V
L
L
R
C
T
= 10 kΩ
= 50 pF
= 25°C
R
= 50
null
0.5
0.0
C
A
V = 3 V
I
−40 −25 −10
5
20 35 50 65 80 95 110 125
2.5
4.5
6.5
8.5
10.5 12.5 14.5
10
100
1000
T
A
− Free-Air Temperature − °C
V
− Supply Voltage −V
CC
C
− Capacitive Load − pF
L
Figure 15
Figure 14
Figure 16
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇ ꢅ ꢈ ꢀ ꢁꢂꢃ ꢄ ꢃ ꢆꢇ ꢅ ꢈ ꢀꢁꢂ ꢃꢄ ꢉꢆ ꢇꢅ
ꢑ ꢋꢒ ꢓꢔ ꢕ ꢆꢌ ꢖꢗ ꢘꢋꢍ ꢁ ꢆꢀꢏ ꢆꢘꢋꢍ ꢁ ꢏ ꢙꢀ ꢚ ꢙꢀ
ꢏ ꢚꢛꢘ ꢋꢀ ꢍꢏ ꢜꢋꢁ ꢋꢌ ꢚ ꢁꢍ ꢊꢍ ꢛꢘ ꢝ
ꢊꢋ
ꢌ
ꢍ
ꢁꢎ
ꢏ
ꢊ
ꢐ
ꢐ
ꢆµ
SGLS275 − OCTOBER 2004
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
vs
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
FREQUENCY
100
4
V
= 2.7, 5, 10 V
DD
= 25°C
3
2
90
80
T
A
V
A
R
= 5 V
= 1
= 2 kΩ
= 10 pF
DD
V
L
L
1
0
V
70
60
I
C
V = 3 V
I
PP
50
T
= 25°C
A
40
30
3
2
20
1
0
V
O
10
0
0
2
4
6
8
10 12 14 16 18
10
100
1 k
10 k
100 k
f − Frequency − Hz
t − Time − µs
Figure 18
Figure 17
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
8
0.12
6
0.08
0.04
0.00
V
= 10 V
DD
= 1
V
A
= 5 V
= 1
DD
V
4
2
0
A
V
R
C
= 2 kΩ
= 10 pF
L
L
I
V
R
= 2 kΩ
I
L
V
V
I
C
= 10 pF
L
V = 6 V
T
A
PP
= 25°C
V = 100 mV
I
PP
T
A
= 25°C
0.12
0.08
0.04
0.00
6
4
2
0
V
O
O
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0
2
4
6
8
10 12 14 16 18
t − Time − µs
t − Time − µs
Figure 20
Figure 19
INVERTING LARGE-SIGNAL RESPONSE
4
INVERTING LARGE-SIGNAL RESPONSE
8
V
I
3
2
1
6
V
A
= 10 V
= V = −1
I
V
A
R
= 5 V
= 1
= 2 kΩ
= 10 pF
DD
V
DD
V
L
L
I
4
2
0
R
C
T
= 2 kΩ
= 10 pF
= 25°C
L
L
A
V
I
C
0
V = 3 V
PP
T
A
= 25°C
6
4
2
3
V
O
2
1
0
0
V
O
0
2
4
6
8
10 12 14 16
0
2
4
6
8
10 12 14 16
t − Time − µs
t − Time − µs
Figure 22
Figure 21
11
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ꢊ
ꢋ
ꢌ
ꢍ
ꢁ
ꢎ
ꢏ
ꢊ
ꢐ
ꢏꢚ ꢛ ꢘꢋꢀ ꢍ ꢏꢜ ꢋ ꢁ ꢋꢌ ꢚꢁ ꢍ ꢊꢍ ꢛ ꢘꢝ
ꢐ
ꢑ ꢋꢒ ꢓ ꢔ ꢕ ꢆꢌꢖꢗ ꢘꢋ ꢍ ꢁꢆꢀꢏ ꢆꢘꢋꢍ ꢁ ꢏ ꢙꢀ ꢚꢙꢀ
ꢆ µ
SGLS275 − OCTOBER 2004
TYPICAL CHARACTERISTICS
CROSSTALK
vs
FREQUENCY
INVERTING SMALL-SIGNAL RESPONSE
0
V
= 2.7, 5, & 15 V
DD
V = 1 V /2
−20
I
DD
0.10
A
V
= 1
R
T
A
= 2 kΩ
= 25°C
L
−40
−60
V
= 5 V
DD
0.05
0.00
A
= V = −1
V
I
V
I
R
C
= 2 kΩ
= 10 pF
L
L
V = 100 mV
I
pp
−80
0.10
0.05
0.00
T
= 25°C
A
V
O
−100
−120
−140
Crosstalk
10
100
1 k
10 k
100 k
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
f − Frequency − Hz
t − Time − µs
Figure 24
Figure 23
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s
phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than
10 pF, it is recommended that a resistor be placed in series (R
) with the output of the amplifier, as shown
NULL
in Figure 25. A minimum value of 20 Ω should work well for most applications.
R
F
R
G
R
NULL
−
+
Input
Output
LOAD
C
V
DD
/2
Figure 25. Driving a Capacitive Load
12
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ꢑ ꢋꢒ ꢓꢔ ꢕ ꢆꢌ ꢖꢗ ꢘꢋꢍ ꢁ ꢆꢀꢏ ꢆꢘꢋꢍ ꢁ ꢏ ꢙꢀ ꢚ ꢙꢀ
ꢏ ꢚꢛꢘ ꢋꢀ ꢍꢏ ꢜꢋꢁ ꢋꢌ ꢚ ꢁꢍ ꢊꢍ ꢛꢘ ꢝ
ꢊꢋ
ꢌ
ꢍ
ꢁ
ꢎ
ꢏ
ꢊ
ꢐ
ꢐ
ꢆµ
SGLS275 − OCTOBER 2004
APPLICATION INFORMATION
offset voltage
The output offset voltage (V ) is the sum of the input offset voltage (V ) and both input bias currents (I ) times
OO
IO
IB
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
R
F
I
IB−
R
G
+
R
R
−
+
F
F
V
I
V
+ V
1 ) ǒ Ǔ " I
R
1 ) ǒ Ǔ " I
R
V
O
ǒ Ǔ ǒ Ǔ
OO
IO
IB)
S
IB–
F
R
R
G
G
R
S
I
IB+
Figure 26. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 27).
R
R
F
G
V
R
R
O
F
1
ǒ
Ǔ
+
+
ǒ
1 )
Ǔ
V
1 ) sR1C1
I
G
V
DD
/2
−
1
V
O
f
+
–3dB
V
I
2pR1C1
R1
C1
Figure 27. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For the best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency
bandwidth. Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
R1
R2
f
+
–3dB
2pRC
C2
R
F
1
R
=
G
R
F
2 −
)
R
(
Q
G
V
DD
/2
Figure 28. 2-Pole Low-Pass Sallen-Key Filter
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢅ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢃ ꢆꢇ ꢅ ꢈ ꢀꢁꢂ ꢃ ꢄꢉ ꢆꢇ ꢅ
ꢊ
ꢋ
ꢌ
ꢍ
ꢁ
ꢎ
ꢏ
ꢊ
ꢐ
ꢏꢚ ꢛ ꢘꢋꢀ ꢍ ꢏꢜ ꢋ ꢁ ꢋꢌ ꢚꢁ ꢍ ꢊꢍ ꢛ ꢘꢝ
ꢐ
ꢑ ꢋꢒ ꢓ ꢔ ꢕ ꢆꢌꢖꢗ ꢘꢋ ꢍ ꢁꢆꢀꢏ ꢆꢘꢋꢍ ꢁ ꢏ ꢙꢀ ꢚꢙꢀ
ꢆ
µ
SGLS275 − OCTOBER 2004
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance of the TLV27x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
D
Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
D
Sockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
Short trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier. Its length should be kept as short as possible. This helps to minimize stray capacitance at the
input of the amplifier.
D
Surface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢑ ꢋꢒ ꢓꢔ ꢕ ꢆꢌ ꢖꢗ ꢘꢋꢍ ꢁ ꢆꢀꢏ ꢆꢘꢋꢍ ꢁ ꢏ ꢙꢀ ꢚ ꢙꢀ
ꢏ ꢚꢛꢘ ꢋꢀ ꢍꢏ ꢜꢋꢁ ꢋꢌ ꢚ ꢁꢍ ꢊꢍ ꢛꢘ ꢝ
ꢊꢋ
ꢌ
ꢍ
ꢁꢎ
ꢏ
ꢊ
ꢐ
ꢐ
ꢆµ
SGLS275 − OCTOBER 2004
APPLICATION INFORMATION
general power dissipation considerations
For a given θ , the maximum power dissipation is shown in Figure 29 and is calculated by the following formula:
JA
T
–T
MAX
A
P
+
ǒ Ǔ
D
q
JA
Where:
P
= Maximum power dissipation of TLV27x IC (watts)
= Absolute maximum junction temperature (150°C)
= Free-ambient air temperature (°C)
D
T
MAX
T
A
θ
= θ + θ
JA
JC CA
θ
θ
= Thermal coefficient from junction to case
JC
= Thermal coefficient from case to ambient air (°C/W)
CA
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
2
T
= 150°C
PDIP Package
J
Low-K Test PCB
1.75
θ
= 104°C/W
JA
1.5
1.25
1
MSOP Package
Low-K Test PCB
SOIC Package
Low-K Test PCB
θ
= 260°C/W
JA
θ
= 176°C/W
JA
0.75
0.5
SOT-23 Package
Low-K Test PCB
0.25
0
θ
= 324°C/W
JA
−55−40 −25 −10
5
20 35 50 65 80 95 110 125
T
A
− Free-Air Temperature − °C
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 29. Maximum Power Dissipation vs Free-Air Temperature
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆꢇꢅ ꢈ ꢀ ꢁꢂ ꢃ ꢄꢃ ꢆꢇ ꢅ ꢈ ꢀꢁꢂ ꢃ ꢄꢉ ꢆꢇ ꢅ
ꢊ
ꢋ
ꢌ
ꢍ
ꢁ
ꢎ
ꢏ
ꢊ
ꢐ
ꢏꢚ ꢛ ꢘꢋꢀ ꢍ ꢏꢜ ꢋ ꢁ ꢋꢌ ꢚꢁ ꢍ ꢊꢍ ꢛ ꢘꢝ
ꢐ
ꢑ ꢋꢒ ꢓ ꢔ ꢕ ꢆꢌꢖꢗ ꢘꢋ ꢍ ꢁꢆꢀꢏ ꢆꢘꢋꢍ ꢁ ꢏ ꢙꢀ ꢚꢙꢀ
ꢆ µ
SGLS275 − OCTOBER 2004
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 9.1, the model generation
software used with Microsim PSpice. The Boyle macromodel (see Note 2) and subcircuit in Figure 30 are
generated using TLV27x typical electrical and operating characteristics at T = 25°C. Using this information,
A
output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D
D
D
D
D
D
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
D
D
D
D
D
D
Unity-gain frequency
Common-mode rejection ratio
Phase margin
Quiescent power dissipation
Input bias current
DC output resistance
AC output resistance
Short-circuit output current limit
Open-loop voltage amplification
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
3
99
V
DD
+
−
egnd
rd1
11
rd2
12
rss
ro2
css
fb
rp
c1
7
+
c2
vlim
−
8
1
2
+
−
r2
9
6
IN+
IN−
vc
D
S
D
S
+
vb
ga
G
G
−
ro1
gcm
ioff
53
OUT
dp
5
dlp
dln
91
90
92
10
−
+
−
+
−
iss
dc
vlp
hlim
vln
−
+
GND
+ 54
4
de
ve
*DEVICE=amp_tlv27x_highVdd,OP AMP,NJF,INT
ga
6
0
11 12 16.272E−6
10 99 6.8698E−9
dc 1.3371E−6
vlim 1K
* amp_tlv_27x_highVdd operational amplifier ”macromodel”
gcm
iss
0
6
* subcircuit updated using Model Editor release 9.1 on 05/15/00
* at 14:40 Model Editor is an OrCAD product.
*
10
90
11
12
6
4
hlim
j1
J2
r2
rd1
rd2
ro1
ro2
rp
rss
vb
vc
ve
vlim
vlp
vln
.model
.model dy
.model jx1
.model jx2
.ends
0
2
10 jx1
* connections:
non-inverting input
| inverting input
1
10 jx2
*
*
*
*
*
9
100.00E3
61.456E3
61.456E3
10
| | positive power supply
| | | negative power supply
| | | | output
3
11
12
5
3
8
| | | | |
7
99
4
10
.subckt amp_tlv27x_highVdd 1 2 3 4 5
*
3
150.51E3
149.58E6
dc 0
10
9
99
0
c1
11
6
12 457.48E−15
c2
7
5.0000E−12
3
53
4
dc .78905
dc .78905
dc 0
dc 14.200
dc 14.200
css
dc
10
5
99 1.1431E−12
53 dy
54
7
8
de
54
90
92
4
99
7
5
dy
91
0
0
dlp
dln
dp
egnd
fb
91 dx
90 dx
92
dx
D(Is=800.00E−18)
3
0
dx
D(Is=800.00E−18 Rs=1m Cjo=10p)
poly(2) (3,0) (4,0) 0 .5 .5
NJF(Is=500.00E−15 Beta=198.03E−6 Vto=−1)
NJF(Is=500.00E−15 Beta=198.03E−6 Vto=−1)
99 poly(5) vb vc ve vlp vln 0
176.02E6 −1E3 1E3 180E6
−180E6
Figure 30. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
TLV271QDBVRQ1
TLV271QDRQ1
TLV272QDRQ1
TLV274QDRQ1
TLV274QPWRQ1
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
SOIC
D
D
8
2500
2500
2500
2000
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
8
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
SOIC
D
14
14
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
TSSOP
PW
None
CU NIPDAU Level-1-250C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号:
TLV2382IDGK
DUAL OP-AMP, 6500uV OFFSET-MAX, 0.16MHz BAND WIDTH, PDSO8, ULTRA SMALL, PLASTIC, MSOP-8
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