TLV5625 [TI]
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN; 2.7 V至5.5 V低功耗双8 - BIT DIGITAL- TO- ANALOG与电源转换器的降压
| 型号： | TLV5625 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN |
| 文件： | 总15页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
features
applications
Dual 8-Bit Voltage Output DAC
Programmable Internal Reference
Digital Servo Control Loops
Digital Offset and Gain Adjustment
Industrial Process Control
Programmable Settling Time
– 2.5 µs in Fast Mode
– 12 µs in Slow Mode
Machine and Motion Control Devices
Mass Storage Devices
Compatible With TMS320 and SPI Serial
Ports
D PACKAGE
(TOP VIEW)
Differential Nonlinearity <0.2 LSB Max
Monotonic Over Temperature
DIN
SCLK
CS
V
DD
OUTB
REF
1
2
3
4
8
7
6
5
description
The TLV5625 is a dual 8-bit voltage output DAC
with a flexible 3-wire serial interface. The serial
interface is compatible with TMS320, SPI ,
OUTA
AGND
QSPI , and Microwire
serial ports. It is
programmed with a 16-bit serial string containing
4 control and 8 data bits.
The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a
Class-AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC
allows the designer to optimize speed versus power dissipation.
Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It
is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges.
AVAILABLE OPTIONS
PACKAGE
T
A
SOIC
(D)
0°C to 70°C
TLV5625CD
TLV5625ID
–40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
Copyright 2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
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TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
functional block diagram
REF
AGND
V
DD
Power and
Speed Control
Power-On
Reset
2
x2
OUTA
DIN
8-Bit
DAC A
Latch
8
8
SCLK
CS
Serial
Interface
and
8
Buffer
Control
8
8
8-Bit
DAC B
Latch
x2
OUTB
Terminal Functions
TERMINAL
I/O/P
DESCRIPTION
NAME
NO.
5
AGND
CS
P
I
Ground
3
Chip select. Digital input active low, used to enable/disable inputs.
Digital serial data input
DIN
1
I
OUTA
OUTB
REF
4
O
O
I
DAC A analog voltage output
DAC B analog voltage output
Analog reference voltage input
Digital serial clock input
7
6
SCLK
2
I
V
DD
8
P
Positive power supply
2
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TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (V
to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V
+ 0.3 V
+ 0.3 V
DD
DD
Operating free-air temperature range, T : TLV5625C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLV5625I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
4.5
2.7
0.55
2
NOM
MAX
5.5
3.3
2
UNIT
V
V
= 5 V
= 3 V
5
3
V
DD
Supply voltage, V
DD
DD
Power on reset, POR
V
V
High-level digital input voltage, V
V
DD
V
DD
V
DD
V
DD
= 2.7 V to 5.5 V
= 2.7 V to 5.5 V
= 5 V (see Note 1)
= 3 V (see Note 1)
IH
Low-level digital input voltage, V
IL
0.8
V
Reference voltage, V to REF terminal
ref
AGND
AGND
2
2.048
1.024
V
–1.5
–1.5
V
DD
Reference voltage, V to REF terminal
ref
V
V
DD
Load resistance, R
kΩ
pF
MHz
L
Load capacitance, C
100
20
L
Clock frequency, f
CLK
TLV5625C
TLV5625I
0
70
Operating free-air temperature, T
°C
A
–40
85
NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (V –0.4 V)/2 causes clipping of the transfer function.
DD
3
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TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mA
µA
Fast
1.8
2.3
No load, All inputs = AGND or V
DAC latch = 0x800
,
DD
I
Power supply current
Slow
0.8
1
1
3
Power-down supply current
Power supply rejection ratio
Zero scale, See Note 2
Full scale, See Note 3
–65
–65
PSRR
dB
NOTES: 2. Power supply rejection ratio at zero scale is measured by varying V
and is given by:
and is given by:
DD
PSRR = 20 log [(E (V max) – E (V min)/V max]
ZS DD ZS DD DD
3. Power supply rejection ratio at full scale is measured by varying V
DD
PSRR = 20 log [(E (V max) – E (V min)/V max]
DD DD DD
G
G
static DAC specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
bits
Resolution
8
INL
Integral nonlinearity
See Note 4
See Note 5
See Note 6
See Note 7
±0.3
±0.5
±0.2
±12
LSB
DNL
Differential nonlinearity
±0.07
LSB
E
Zero-scale error (offset error at zero scale)
TC Zero-scale-error temperature coefficient
mV
ZS
ZS
E
10
ppm/°C
% full
scale V
E
Gain error
See Note 8
See Note 9
±0.5
G
E
G
T
Gain-error temperature coefficient
10
ppm/°C
C
NOTES: 4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale, excluding the effects of zero-code and full-scale errors.
5. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal
1-LSB amplitude change of any two adjacent codes.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
6
7. Zero-scale error temperature coefficient is given by: E
TC = [E
(T
)
E
(T
)]/2V × 10 /(T
ref max
– T
).
min
ZS
ZS max – ZS min
8. Gain error is the deviation from the ideal output (2V – 1 LSB) with an output load of 10 kΩ.
ref
6
9. Gain temperature coefficient is given by: E
T
[E (T ) E (T
G max – g
)]/2V × 10 /(T
min ref max
– T
).
min
G
C =
output specifications
PARAMETER
TEST CONDITIONS
= 10 kΩ
MIN
TYP
TYP
MAX
–0.4
UNIT
V
V
Output voltage range
R
0
V
V
O
L
DD
Output load regulation accuracy
V
4.096 V, 2.048 V R = 2 kΩ
±0.29
% FS
O =
L
reference input
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
I
Input voltage range
Input resistance
0
DD–1.5
R
C
10
5
MΩ
pF
I
I
Input capacitance
Fast
1.3
MHz
Reference input bandwidth
Reference feedthrough
REF = 0.2 V + 1.024 V dc
pp
Slow
525
–80
kHz
dB
REF = 1 V at 1 kHz + 1.024 V dc (see Note 10)
pp
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
4
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TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)
digital inputs
PARAMETER
High-level digital input current
TEST CONDITIONS
V = V
MIN
TYP
MAX
UNIT
µA
I
I
1
IH
I
DD
Low-level digital input current
Input capacitance
V = 0 V
I
–1
µA
IL
C
8
pF
i
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
2.5
12
1
MAX
UNIT
Fast
Slow
Fast
Slow
Fast
Slow
R
= 10 kΩ,
C
C
C
= 100 pF,
= 100 pF,
= 100 pF,
L
L
L
L
t
t
Output settling time, full scale
µs
s(FS)
See Note 11
R
= 10 kΩ,
L
Output settling time, code to code
µs
s(CC)
See Note 12
2
3
R
= 10 kΩ,
L
SR
Slew rate
V/µs
See Note 13
0.5
DIN = 0 to 1,
FCLK = 100 kHz,
Glitch energy
5
nV–s
CS = V
DD
SNR
Signal-to-noise ratio
52
48
54
49
SINAD
THD
Signal-to-noise + distortion
Total harmonic distortion
Spurious free dynamic range
f = 102 kSPS,
f
= 1 kHz,
C = 100 pF
L
s
out
dB
R
= 10 kΩ,
–50
50
–48
L
SFDR
48
NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.
12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.
5
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TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
digital input timing requirements
MIN NOM
MAX
UNIT
ns
t
t
t
t
t
t
Setup time, CS low before first negative SCLK edge
10
10
25
25
10
5
su(CS–CK)
su(C16-CS)
wH
th
Setup time, 16 negative SCLK edge before CS rising edge
ns
SCLK pulse width high
ns
SCLK pulse width low
ns
wL
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
ns
su(D)
ns
h(D)
timing requirements
t
t
wL
wH
SCLK
DIN
X
X
X
1
2
3
4
5 15
16
t
t
su(D) h(D)
D15
D14
D13
D12
D1
D0
X
t
su(C16-CS)
t
su(CS-CK)
CS
Figure 1. Timing Diagram
6
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TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
LOAD CURRENT
LOAD CURRENT
2.050
2.048
2.046
2.044
2.042
2.040
2.038
2.036
4.105
4.100
4.095
4.090
4.085
4.080
4.075
4.070
3 V Slow Mode, SOURCE
V
V
=3 V
REF
V
=5 V
DD
DD
=1 V
V
=2 V
REF
5 V Slow Mode, SOURCE
Full scale
Full scale
3 V Fast Mode, SOURCE
5 V Fast Mode, SOURCE
0.00 –0.01–0.02–0.05–0.10–0.20–0.51 –1.02–2.05
Load Current - mA
0.00 –0.02–0.04–0.10–0.20–0.41–1.02 –2.05–4.10
Load Current - mA
Figure 2
Figure 3
OUTPUT VOLTAGE
vs
LOAD CURRENT
OUTPUT VOLTAGE
vs
LOAD CURRENT
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0.00
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
V
V
=3 V
REF
V
V
=5 V
REF
DD
DD
=1 V
=2 V
Zero scale
Zero scale
3 V Slow Mode, SINK
5 V Slow Mode, SINK
5 V Fast Mode, SINK
3 V Fast Mode, SINK
0.00 0.01 0.02 0.05 0.10 0.20 0.51 1.02 2.05
Load Current - mA
0.00 0.02 0.04 0.10 0.20 0.41 1.02 2.05 4.09
Load Current - mA
Figure 4
Figure 5
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
V
V
=3 V
REF
DD
=1 V
Full scale
Fast Mode
Fast Mode
V
V
=5 V
REF
DD
=2 V
Full scale
Slow Mode
Slow Mode
–40.00–20.00 0.00 20.00 40.00 60.00 80.00 100.00120.00
–40.00–20.00 0.00 20.00 40.00 60.00 80.00 100.00120.00
T
A
- Free-Air Temperature - C
T
A
- Free-Air Temperature - C
Figure 6
Figure 7
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
0.00
–10.00
–20.00
–30.00
–40.00
–50.00
–60.00
–70.00
–80.00
–90.00
0.00
–10.00
–20.00
–30.00
–40.00
–50.00
–60.00
–70.00
–80.00
–90.00
V
= 1 V + 1 V
Sinewave,
V
= 1 V + 1 V
Sinewave,
P/P
REF
P/P
REF
Output Full Scale
Output Full Scale
3 V Slow Mode
3 V Fast Mode
5 V Slow Mode
5 V Fast Mode
1
10
100
1
10
100
f - Frequency - kHz
f - Frequency - kHz
Figure 8
Figure 9
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
–0.04
–0.06
–0.08
–0.10
0
255
64
128
192
Digital Output Code
Figure 10
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.5
0.4
0.3
0.2
0.1
–0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
255
64
128
192
Digital Output Code
Figure 11
9
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TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
general function
The TLV5625 is a dual 8-bit, single-supply DAC, based on a resistor-string architecture. It consists of a serial
interface, a speed and power-down control logic, a resistor string, and a rail-to-rail output buffer.
The output voltage (full scale determined by the reference) is given by:
CODE
2 REF
[V]
0x1000
WhereREFisthereferencevoltageandCODEisthedigitalinputvalueintherange0x000to0xFF0. Apower-on
reset initially puts the internal latches to a defined state (all bits zero).
serial interface
A falling edge of CS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling
edges of SCLK. After 16 bits have been transferred or CS rises, the content of the shift register is moved to the
target latches (DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data word.
Figure 2 shows examples of how to connect the TLV5625 to TMS320, SPI , and Microwire .
TMS320
DSP
TLV5625
SPI
TLV5625
CS
DIN
Microwire
I/O
TLV5625
CS
DIN
CS
FSX
DX
I/O
MOSI
SCK
DIN
SO
SK
CLKX
SCLK
SCLK
SCLK
Figure 12. Three-Wire Interface
Notes on SPI and Microwire : Before the controller starts the data transfer, the software has to generate a
falling edge on the pin connected to CS. If the word width is 8 bits (SPI and Microwire ) two write operations
must be performed to program the TLV5625. After the write operation(s), the holding registers or the control
th
register are updated automatically on the 16 positive clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
1
f
20 MHz
sclkmax
t
t
wlmin
whmin
The maximum update rate is:
1
f
1.25 MHz
updatemax
16 t
t
wlmin
whmin
Note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the
TLV5625 should also be considered.
10
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TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
data format
The 16-bit data word for the TLV5625 consists of two parts:
Program bits (D15..D12)
New data
(D11..D4)
D15
R1
D14
D13
D12
R0
D11
D10
D9
D8
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
SPD
PWR
MSB
8 Data bits
LSB
SPD: Speed control bit
PWR: Power control bit
1 → fast mode
1 → power down
0 → slow mode
0 → normal operation
On power up, SPD and PWD are reset to 0 (slow mode and normal operation)
The following table lists all possible combination of register-select bits:
register-select bits
R1
0
R0
0
REGISTER
Write data to DAC B and BUFFER
Write data to BUFFER
0
1
1
0
Write data to DAC A and update DAC B with BUFFER content
Reserved
1
1
The meaning of the 12 data bits depends on the register. If one of the DAC registers or the BUFFER is selected,
then the 12 data bits determine the new DAC value:
examples of operation
Set DAC A output, select fast mode:
Write new DAC A value and update DAC A output:
D15
1
D14
1
D13
0
D12
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
New DAC A output value
The DAC A output is updated on the rising clock edge after D0 is sampled.
Set DAC B output, select fast mode:
Write new DAC B value to BUFFER and update DAC B output:
D15
0
D14
1
D13
0
D12
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
New BUFFER content and DAC B output value
The DAC A output is updated on the rising clock edge after D0 is sampled.
Set DAC A value, set DAC B value, update both simultaneously, select slow mode:
1. Write data for DAC B to BUFFER:
D15
0
D14
0
D13
0
D12
1
D11
D10
D9
D8
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
New DAC B value
2. Write new DAC A value and update DAC A and B simultaneously:
D15
1
D14
0
D13
0
D12
0
D11
D10
D9
D8
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
New DAC A value
11
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SLAS233A – JULY 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
examples of operation (continued)
Both outputs are updated on the rising clock edge after D0 from the DAC A data word is sampled.
Set power-down mode:
D15
X
D14
X
D13
1
D12
X
D11
X
D10
X
D9
X
D8
X
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
X = Don’t care
linearity, offset, and gain error using single ended supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage
may not change with the first code, depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 13.
Output
Voltage
0 V
DAC Code
Negative
Offset
Figure 13. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage.
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground
currents are well managed and there are negligible voltage drops across the ground plane.
A0.1-µFceramic-capacitorbypassshouldbeconnectedbetweenV andAGNDandmountedwithshortleads
DD
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.
Figure 14 shows the ground plane layout and bypassing technique.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
Analog Ground Plane
1
2
3
4
8
7
6
5
0.1 µF
Figure 14. Power-Supply Bypassing
definitions of specifications and terminology
integral nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.
differential nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
zero-scale error (E
)
ZS
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
gain error (E )
G
Gain error is the error in slope of the DAC transfer function.
signal-to-noise ratio + distortion (S/N+D)
S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
spurious free dynamic range (SFDR)
SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious
signal within a specified bandwidth. The value for SFDR is expressed in decibels.
total harmonic distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal
and is expressed in decibels.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG
CONVERTER WITH POWER DOWN
SLAS233A – JULY 1999 – REVISED MARCH 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
M
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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